From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ej1-x62f.google.com (mail-ej1-x62f.google.com [IPv6:2a00:1450:4864:20::62f]) by sourceware.org (Postfix) with ESMTPS id AE0013858D37 for ; Fri, 4 Feb 2022 01:06:35 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org AE0013858D37 Received: by mail-ej1-x62f.google.com with SMTP id jx6so14357623ejb.0 for ; Thu, 03 Feb 2022 17:06:35 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=PK/xZwIY2voqFwb83+0iTZLKHEoUNGivASQMO8/MC9E=; b=RtmKDiqijbyA4qCoQhryRtGYjVkAj7dKxGYw72gwrkkHBdN/UqCUicFlJficw40wI5 lVQD8xIWu0M85PkgG41PE5ojIJS4cmJpaozQjIx2zH0h6o/4Zskd2e29mHGE5KtB0LeW 8GUetdB/VIH2nLwFdqgILfm1iS/w1L7aKHXy76A0Eqkog5y2DTibEKRhP+iz68iOfIqp JtHtzP24A5Y40K2C9ahXwrLwmkrZtnJdmHIc++8o1jGeTOtps9MSSZ+HIXsSAl6n/wg3 9aBaxBid7u5q/DrzkTT81xwJ+tv5XpFZzg5Y7JnJt92zyq6tWZVGJfzSwdjXE6G7+pdG TMKg== X-Gm-Message-State: AOAM5326XuKtsnDFvARvOnaWPM9TsIVQ+q0TWUXgmhRjBHmanL4IrEKl lHL9RFswfVPch+mqKa7L9kGszglMUo/MDC/oeYgNvA== X-Google-Smtp-Source: ABdhPJwFnLmN6bqm2kf3sh8JpPSEGfcZw4X5lo8Eu+zLOCj2cMfuC6bOEcu0GzgLZnhP24fkKfdCGW2/ysvjaaecnYM= X-Received: by 2002:a17:907:72c3:: with SMTP id du3mr424971ejc.457.1643936794653; Thu, 03 Feb 2022 17:06:34 -0800 (PST) MIME-Version: 1.0 References: <3b7e6310-1376-91a0-fe50-a6b7e5dd125b@gmail.com> <20220128182105.GF614@gate.crashing.org> In-Reply-To: <20220128182105.GF614@gate.crashing.org> From: Reshabh K Sharma Date: Thu, 3 Feb 2022 17:06:23 -0800 Message-ID: Subject: Re: Describe instructions with same reg in def and use or mutiple defs and attach write latency To: Segher Boessenkool Cc: Jeff Law , gcc-help@gcc.gnu.org X-Spam-Status: No, score=-1.7 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HTML_MESSAGE, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org Content-Type: text/plain; charset="UTF-8" X-Content-Filtered-By: Mailman/MimeDel 2.1.29 X-BeenThere: gcc-help@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-help mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Fri, 04 Feb 2022 01:06:38 -0000 On Fri, Jan 28, 2022 at 10:23 AM Segher Boessenkool < segher@kernel.crashing.org> wrote: > On Fri, Jan 28, 2022 at 10:39:54AM -0700, Jeff Law via Gcc-help wrote: > > On 1/26/2022 6:20 PM, Reshabh K Sharma via Gcc-help wrote: > > >I am trying to implement a post address update load instruction in our > > >downstream riscv backend. I want to attach write latency information to > a > > >use register. For example, rd = new_load rs1 rs2, I want to attach > separate > > >write latency information to both rd and rs1. > > > > > >I am unable to find how to describe instructions that have an operand as > > >both def and use, and later attach write latency information for the > > >instruction scheduler to work properly. > > > > > >It will also be very helpful if you can point me to the implementation > of > > >similar instructions in other backends, for example, LBZU in PowerPC, > ARM's > > >LWD post/pre address update versions and ARM's neon simd load with > update. > > I'm not sure the scheduler can model different latencies for the > > multiple outputs. If anyone knows for sure, it would be Vlad. > > You can use TARGET_SCHED_ADJUST_COST? > Thank you so much! I think target_sched_adjust_cost will do. Given two rtx_insn, x = exp_load addr offset and y = add addr z, these two instructions are the input arguments to target_sched_adjust_cost, how do I check that given rtx_insn is exp_load? (how do we check if rtx_insn is of type exp_load, add or any other target specific instruction?) and how do I check if there is a read after read dependency for addr operand and not the offset. > It may not matter in practice though. I'd hazard a guess these things > > hang out in the reorder buffer until both outputs are ready and only > > then will it move into the retirement queue. > > The GCC scheduling description says when results are ready, not when the > instructions (can) finish or complete (aka retire). I do agree this > case doesn't matter so much, cases where it does matter will have their > dependency chains broken much earlier :-) > > > Segher Thanks again for the help! Reshabh