From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ed1-x531.google.com (mail-ed1-x531.google.com [IPv6:2a00:1450:4864:20::531]) by sourceware.org (Postfix) with ESMTPS id A52D83858C20 for ; Wed, 16 Feb 2022 19:41:50 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org A52D83858C20 Received: by mail-ed1-x531.google.com with SMTP id f17so5780118edd.2 for ; Wed, 16 Feb 2022 11:41:50 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:references:in-reply-to:from:date :message-id:subject:to:cc; bh=BixiHV/BdzUluuYm2c48VcWuAF5JQYObDHFL49NXow8=; b=tVtDodjtbl7/nY5gtwJhzc0Otrj4SVVokWQI9BTKE1+A1/F3K4ZX1N6yTp3liEvqtv p947Y6aY8sycwM60j+d9GcZydvQzOSqSMkFx+IygHSxq3j797z4SZGvCVo7iXNv8X7Rh GrP/ldmVd8TAW8XZ8yXKBQvVvOVJdJEKGUkTy/U+m6SvuZpeUOXnWuRV7W4VOM9W4C6n 8UWVKocCgKJwoBwuTcuv9ii0me9jevrAvJEX8TqaW3z2PCbONlWpN4G3WfPbpsa2GKie mlzhHG9INL6X3e9L/uhbm2nR3tOQkd4v0SS9gYwOVOaBs150FseQb5QztJVzs44E+AiM 0fCA== X-Gm-Message-State: AOAM533FtZjJ/xawH0veaTVRYHQo6ZZUGJ+t7C1/2FNtuh7zFJDnivuT lkrdmISxHP1arFyL0/R5s9xOR26R2QqdoHeC3wGVXQ== X-Google-Smtp-Source: ABdhPJzRhabQlGKNcLWghSkWNP+NdweJypSveOA4m4sLGE2+uSXyWh6lqGVNmHba75BaPOvuaUJuEoSP4gFerx/XtJw= X-Received: by 2002:aa7:df1a:0:b0:409:5174:68a9 with SMTP id c26-20020aa7df1a000000b00409517468a9mr4780747edy.145.1645040508731; Wed, 16 Feb 2022 11:41:48 -0800 (PST) MIME-Version: 1.0 References: <3b7e6310-1376-91a0-fe50-a6b7e5dd125b@gmail.com> <20220128182105.GF614@gate.crashing.org> <20220204013156.GD614@gate.crashing.org> In-Reply-To: <20220204013156.GD614@gate.crashing.org> From: Reshabh K Sharma Date: Wed, 16 Feb 2022 11:41:37 -0800 Message-ID: Subject: Re: Describe instructions with same reg in def and use or mutiple defs and attach write latency To: Segher Boessenkool Cc: Jeff Law , gcc-help@gcc.gnu.org X-Spam-Status: No, score=-1.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, HTML_MESSAGE, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org Content-Type: text/plain; charset="UTF-8" X-Content-Filtered-By: Mailman/MimeDel 2.1.29 X-BeenThere: gcc-help@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-help mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 16 Feb 2022 19:41:52 -0000 On Thu, Feb 3, 2022 at 5:33 PM Segher Boessenkool < segher@kernel.crashing.org> wrote: > Hi! > > On Thu, Feb 03, 2022 at 05:06:23PM -0800, Reshabh K Sharma wrote: > > On Fri, Jan 28, 2022 at 10:23 AM Segher Boessenkool < > > segher@kernel.crashing.org> wrote: > > > You can use TARGET_SCHED_ADJUST_COST? > > > > Thank you so much! I think target_sched_adjust_cost will do. > > Given two rtx_insn, > > x = exp_load addr offset and > > y = add addr z, > > these two instructions are the input arguments to > target_sched_adjust_cost, > > > > how do I check that given rtx_insn is exp_load? (how do we check if > > rtx_insn is of type exp_load, add or any other target specific > instruction?) > > and how do I check if there is a read after read dependency for addr > > operand and not the offset. > > "type" is just an insn attribute, so you would use > if (get_attr_type (insn) == TYPE_EXP_LOAD) > or similar. > Thank you so much! Initially I added an instruction in binutils inside opcode/riscv-opc.c as, "{"flwr", 0, INSN_CLASS_I, "D,s,t", MATCH_FLWR, MASK_FLWR, match_opcode, INSN_DREF|INSN_4_BYTE }," for a custom instruction, flwr rd, rs1, rs2 I wanted to add scheduling cost to rd and rs, I was suggested to use TARGET_SCHED_ADJUST_COST but there I need to check if the instruction is FLWR and as suggested I tried using get_attr_type. I realized that first I need to set the type then use get_attr_type. I also couldn't find any other place to set the attribute other than define_insn but this custom instruction was just going to be used in inline asm right now so there was no equivalent rtl from which I can lower into this but since I was not able to find any other way to set the attribute, I decided to add a pattern (hoping it to be unmatchable) where I could add the attribute, so inside riscv.md I added the define_insn for flwr and used set_attr but I'm not able to find any instruction in the TARGET_SCHED_ADJUST_COST for the specific type attr. 1. Does inline asm compilation flow goes through the TARGET_SCHED_ADJUST_COST? 2. Is there a better way to do this? / Am I missing something? > Segher > Many thanks, Reshabh