From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-yb1-xb2e.google.com (mail-yb1-xb2e.google.com [IPv6:2607:f8b0:4864:20::b2e]) by sourceware.org (Postfix) with ESMTPS id 2A2593858027 for ; Tue, 22 Feb 2022 19:00:37 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 2A2593858027 Received: by mail-yb1-xb2e.google.com with SMTP id v186so43288049ybg.1 for ; Tue, 22 Feb 2022 11:00:37 -0800 (PST) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:mime-version:from:date:message-id:subject:to; bh=wZMiioNEUSEccbaC3LW2Gz2WMyt0dzv7i6wuclo9QfE=; b=1W74yECxFwEVcmMC6ZyLygym3NBq0MkvcBXL6KreujcI7ybaUwACGmaQI5OEQFkIBe d+vS8zpr+CcEmY2sLF9051WgBKl2+3xlP0UVUUQk2OJcVCbFbj/pTcS1a+WhcmndULGz X/NuTEjM/z/g0T5QGmb+hWLD6kVhsdw1ituXZLJxHp6cLxiQIl2v5WXRIJHUqCejpJWX HbqYinc/3w8nmFR/UGVgsmTAqS6OkfLzqfjoxxysgtP0bfi8U5l7RCZ16c7Emdn5PRcN yfPpnOSBokwXlPtj2ziNyYhhcCF1EEETkyeljGZfMOh3817UNwQoUA7PWn3jBfgsgt3j LlPw== X-Gm-Message-State: AOAM530SyvkzOzZeTNg0FFy02WXFyXTEB6tzi0805TmFiUtQgqOucsbA KbZj+jL01zSNgA+5mqzgUVb93cCu0wsEWYOMxM4hpoqLXtY= X-Google-Smtp-Source: ABdhPJyiZ+5rRXS4UWaHetu1E20gVyuSyWV3x3x/WRsWR+razNXZIHr0j4pwklYyYlIUPqn+0QD+LS5GFwgxwuZSYZs= X-Received: by 2002:a25:ac46:0:b0:624:4382:4ecd with SMTP id r6-20020a25ac46000000b0062443824ecdmr18733194ybd.108.1645556436513; Tue, 22 Feb 2022 11:00:36 -0800 (PST) MIME-Version: 1.0 From: William Tambe Date: Tue, 22 Feb 2022 13:00:25 -0600 Message-ID: Subject: Make GCC move instructions between a multi-cycle instruction and the next instruction that depends on its result. To: gcc-help Content-Type: text/plain; charset="UTF-8" X-Spam-Status: No, score=0.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-help@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-help mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Tue, 22 Feb 2022 19:00:38 -0000 In this CPU, A multi-cycle instruction, once decoded, runs in parallel as other decoded single/multi-cycle instructions. A single/multi-cycle instruction takes two operands, where the first operand receives the result of computing both operands. An example of multi-cycle instruction is "div". An example of single-cycle instruction is "add". GCC should be able to transform following: ```` add %0 %5 add %1 %6 div %4 %5 #<-- Multi-cycle instruction. add %4 %7 #<-- Next instruction that depends on its result. add %3 %7 add %2 %7 ``` To: ``` div %4 %5 #<-- Multi-cycle instruction. add %0 %5 add %1 %6 add %3 %7 add %2 %7 add %4 %7 #<-- Next instruction that depends on its result. ``` Without above transformation, `add %4 %7` would cause the cpu to wait on `div %4 %5` when it could have executed instructions that do not depend on the result of "div".