* Question on Processor pipeline description in GCC online doc
@ 2013-01-29 17:35 Terry Guo
2013-01-30 15:20 ` Ian Lance Taylor
0 siblings, 1 reply; 2+ messages in thread
From: Terry Guo @ 2013-01-29 17:35 UTC (permalink / raw)
To: gcc-help
Hi there,
I am trying to under GCC pipeline description by reading its online
doc at http://gcc.gnu.org/onlinedocs/gccint/Processor-pipeline-description.html#Processor-pipeline-description.
The following example in the online doc confused me:
(define_insn_reservation "div" 8 (eq_attr "type" "div")
"i1_pipeline, div*7, div + (port0 | port1)")
My understanding is that the first cycle will use i1_pipeline unit and
the next 7 cycles will use div unit, the 9th cycles will use either
"div + port0" or "div + port1" unit. So in sum, this div instruction
is going to need 9 cycles, not the 8. Or the "div*7" would be "div*6"?
Could some one please help to clarify? Thanks in advance.
BR,
Terry
^ permalink raw reply [flat|nested] 2+ messages in thread
* Re: Question on Processor pipeline description in GCC online doc
2013-01-29 17:35 Question on Processor pipeline description in GCC online doc Terry Guo
@ 2013-01-30 15:20 ` Ian Lance Taylor
0 siblings, 0 replies; 2+ messages in thread
From: Ian Lance Taylor @ 2013-01-30 15:20 UTC (permalink / raw)
To: Terry Guo; +Cc: gcc-help
On Tue, Jan 29, 2013 at 7:47 AM, Terry Guo <flameroc@gmail.com> wrote:
>
> I am trying to under GCC pipeline description by reading its online
> doc at http://gcc.gnu.org/onlinedocs/gccint/Processor-pipeline-description.html#Processor-pipeline-description.
> The following example in the online doc confused me:
>
> (define_insn_reservation "div" 8 (eq_attr "type" "div")
> "i1_pipeline, div*7, div + (port0 | port1)")
>
> My understanding is that the first cycle will use i1_pipeline unit and
> the next 7 cycles will use div unit, the 9th cycles will use either
> "div + port0" or "div + port1" unit. So in sum, this div instruction
> is going to need 9 cycles, not the 8. Or the "div*7" would be "div*6"?
> Could some one please help to clarify? Thanks in advance.
Presumably there is a register bypass in the last cycle, so that the
next instruction can use the result directly without waiting for the
write back to the register file.
Ian
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