* Information regarding scheduler description
@ 2012-01-02 6:53 ganesh gopalasubramanian
2012-01-05 13:01 ` Fwd: " ganesh gopalasubramanian
0 siblings, 1 reply; 3+ messages in thread
From: ganesh gopalasubramanian @ 2012-01-02 6:53 UTC (permalink / raw)
To: gcc-help
Hi,
I am trying to describe my processor pipeline.
Consider that I am having 5 instructions (instruction1,
instruction2... instruction5).
For four of those instructions, I have described the instruction
reservations along with the functional units and their alternatives
available for each cycle.
For the fifth instruction, I haven't described the instruction reservation.
What will happen now? Will the instruction be stalling my pipeline.
Consider that five instruction instruction are generated as below.
instruction1,
instruction2,
instruction3,
instruction4,
instruction5
My scheduler description supports the following
1. instruction1 & instruction2 can be issued as a single bundle.
2. instruction3 & instruction4 can be issued as a single bundle.
Now, I don't have description about instruction5, will it stall my
pipeline and get issued as a separation instruction bundle (assuming
issue rate as 1)?
Or should I describe the instruction reservation (for instruction5)
separately along with stall information?
Regards
Ganesh
^ permalink raw reply [flat|nested] 3+ messages in thread
* Fwd: Information regarding scheduler description
2012-01-02 6:53 Information regarding scheduler description ganesh gopalasubramanian
@ 2012-01-05 13:01 ` ganesh gopalasubramanian
2012-01-10 18:05 ` Vladimir Makarov
0 siblings, 1 reply; 3+ messages in thread
From: ganesh gopalasubramanian @ 2012-01-05 13:01 UTC (permalink / raw)
To: vmakarov; +Cc: gcc-help
Hi Makarov,
I posted a mail couple of days back.
Could you throw some light on this?
Thanks
Ganesh
---------- Forwarded message ----------
From: ganesh gopalasubramanian <gganeshgcc@gmail.com>
Date: Mon, Jan 2, 2012 at 12:22 PM
Subject: Information regarding scheduler description
To: gcc-help@gcc.gnu.org
Hi,
I am trying to describe my processor pipeline.
Consider that I am having 5 instructions (instruction1,
instruction2... instruction5).
For four of those instructions, I have described the instruction
reservations along with the functional units and their alternatives
available for each cycle.
For the fifth instruction, I haven't described the instruction reservation.
What will happen now? Will the instruction be stalling my pipeline.
Consider that five instruction instruction are generated as below.
instruction1,
instruction2,
instruction3,
instruction4,
instruction5
My scheduler description supports the following
1. instruction1 & instruction2 can be issued as a single bundle.
2. instruction3 & instruction4 can be issued as a single bundle.
Now, I don't have description about instruction5, will it stall my
pipeline and get issued as a separation instruction bundle (assuming
issue rate as 1)?
Or should I describe the instruction reservation (for instruction5)
separately along with stall information?
Regards
Ganesh
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: Fwd: Information regarding scheduler description
2012-01-05 13:01 ` Fwd: " ganesh gopalasubramanian
@ 2012-01-10 18:05 ` Vladimir Makarov
0 siblings, 0 replies; 3+ messages in thread
From: Vladimir Makarov @ 2012-01-10 18:05 UTC (permalink / raw)
To: ganesh gopalasubramanian; +Cc: gcc-help
On 01/05/2012 08:01 AM, ganesh gopalasubramanian wrote:
> Hi Makarov,
>
> I posted a mail couple of days back.
> Could you throw some light on this?
>
> Thanks
> Ganesh
>
>
> ---------- Forwarded message ----------
> From: ganesh gopalasubramanian<gganeshgcc@gmail.com>
> Date: Mon, Jan 2, 2012 at 12:22 PM
> Subject: Information regarding scheduler description
> To: gcc-help@gcc.gnu.org
>
>
> Hi,
>
> I am trying to describe my processor pipeline.
>
> Consider that I am having 5 instructions (instruction1,
> instruction2... instruction5).
> For four of those instructions, I have described the instruction
> reservations along with the functional units and their alternatives
> available for each cycle.
> For the fifth instruction, I haven't described the instruction reservation.
> What will happen now? Will the instruction be stalling my pipeline.
>
> Consider that five instruction instruction are generated as below.
>
> instruction1,
> instruction2,
> instruction3,
> instruction4,
> instruction5
>
> My scheduler description supports the following
>
> 1. instruction1& instruction2 can be issued as a single bundle.
> 2. instruction3& instruction4 can be issued as a single bundle.
>
> Now, I don't have description about instruction5, will it stall my
> pipeline and get issued as a separation instruction bundle (assuming
> issue rate as 1)?
As I remember that absence of description means no reservation at all
and if all input data for such insn are ready and there is no constraint
from the issue rate, the scheduler will consider that there is no
pipeline stall at all and will issue the insn at any time.
The issue rate is upper bound for number of real insns (which excludes
USE/CLOBBER and debug insns) can be issued on the cycle. So if you set
it to 1, the scheduler believes that each insn starts on a new simulated
cycle. In this case, insns #1, #2, #3, and #4 will be considered to be
issued on new cycle too. I guess that is not what you want as I
understand the bundle means issuing insns in the bundle on the same cycle.
You should always describe each insn reservation unless setting the
issue rate is not enough for describing issue rules for specific insn.
> Or should I describe the instruction reservation (for instruction5)
> separately along with stall information?
>
> Regards
> Ganesh
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