Add assembly instruction to GCC

Add assembly instruction to GCC

[Amir Ghanbari]

Hello all,

I'm trying to expand X86 ISA. So I have added some hardware to X86 (in
Gem5 Simulator) and I have updated X86 decoder to support those
instructions. In order to call those instructions I use GCC inline
assembly ".byte" directive. something like this : ".byte 0xF0, 0x0F,
0x23;"
The problem is when I compile my code using GCC, it changes the
instructions that i have created. For instance:
I intend to have something generated like this:

 403ce3: 48 89 eb               mov    %rbp,%rbx
 403ce6: 48 83 e3 fe           and    $0xfffffffffffffffe,%rbx
 403cea: 48 8b 7c 24 08      mov    0x8(%rsp),%rdi
 403cef: f0 0f 23                 lock (bad)
 403cf2: 48 89 04 24           mov    %rax,(%rsp)
 403cf6: 4c 8b 34 24           mov    (%rsp),%r14

but GCC generates something like this:

 403ce3: 48 89 eb               mov    %rbp,%rbx
 403ce6: 48 83 e3 fe           and    $0xfffffffffffffffe,%rbx
 403cea: 48 8b 7c 24 08      mov    0x8(%rsp),%rdi
 403cef: f0 0f                     lock mov (bad),%db1    ====> GCC
screws up this part
 403cf1: 23 48 89               and    -0x77(%rax),%ecx  ==> and this
 403cf4: 04 24                    add    $0x24,%al         ====> and this
 403cf6: 4c 8b 34 24           mov    (%rsp),%r14

Is there a way to tell GCC that "F0 0F 23" is a unique instruction so
it wouldn't mix it with other instructions?
Thank you,
--
Amir

Re: Add assembly instruction to GCC

[Amir Ghanbari]

I think I figured out the problem. The byte sequence generation by GCC
was correct; the problem was with the byte sequence that I have
chosen. "F0 0F" is used for locked opcodes and according to the link
below, mentioned by Mike Shell, can only be used with certain
instructions.
http://pdos.csail.mit.edu/6.858/2011/readings/i386/LOCK.htm
I changed my byte to 3 byte opcode "0F 38 50" and everything is fine
now. Now both disassembly and execution are what I need them to be.
Thank you very much for your time.
--
Amir

On Sat, Apr 14, 2012 at 12:38 AM, Ian Lance Taylor <iant@google.com> wrote:
> Amir Ghanbari <a.ghanbari1990@gmail.com> writes:
>
>> The problem is that the binary being generated is not exactly what I
>> want.
>
> What is the precise byte sequence that you want, and what is the precise
> byte sequence that you are getting?  Don't show us the disassembly; show
> us the bytes.
>
>> I need to make GCC
>> treat that "F0 0F 23" as an instruction and put it in the binary
>> intact and don't mix it with other instructions.
>
> I'm sorry, I don't know what this means.  GCC generates assembly code
> and the assembler generates bytes.
>
> Ian

Re: Add assembly instruction to GCC

[Ian Lance Taylor]

Amir Ghanbari <a.ghanbari1990@gmail.com> writes:

> The problem is that the binary being generated is not exactly what I
> want.

What is the precise byte sequence that you want, and what is the precise
byte sequence that you are getting?  Don't show us the disassembly; show
us the bytes.

> I need to make GCC
> treat that "F0 0F 23" as an instruction and put it in the binary
> intact and don't mix it with other instructions.

I'm sorry, I don't know what this means.  GCC generates assembly code
and the assembler generates bytes.

Ian

Re: Add assembly instruction to GCC

[Michael Shell]

On Fri, 13 Apr 2012 09:24:13 -0400
Amir Ghanbari <a.ghanbari1990@gmail.com> wrote:

> The problem is that the binary being generated is not exactly what I
> want. when I simulate my code, I get an "invalid opcode" error and the
> address of the instruction is exactly where the disassembly get
> screwed up. So I believe that's what's happening. I need to make GCC
> treat that "F0 0F 23" as an instruction and put it in the binary
> intact and don't mix it with other instructions.


If I may, I think the problem is because in vanilla i386, LOCK
cannot be used with MOV:

http://pdos.csail.mit.edu/6.858/2011/readings/i386/LOCK.htm

"An undefined opcode trap will be generated if a LOCK prefix is used
 with any instruction not listed above."

thus the invalid opcode error and the confused disassembler.


  Cheers,

  Mike Shell

Re: Add assembly instruction to GCC

[Andrew Haley]

On 04/13/2012 03:58 PM, Amir Ghanbari wrote:
> Ok, let me get this straight. I'm not sure how the binary files are
> structured. Shouldn't the address of each instruction be in the binary
> file?

No, it's a continuous stream of bytes.  Instruction boundaries are
not marked.

> if I have something like:
>>>>     401ba0 :  f0 0f                     lock mov (bad),%db1"
>>>>     401ba2 :  23 48 89               and    -0x77(%rax),%ecx"
> is it the same as:
>>>>     401ba0 :  f0 0f 23                 lock (bad)
>>>>     401ba3 :  48 89
> aren't those two forms different(they're gonna have different addresses)?

No, they're the same.

> I want GCC to discriminate between these two forms and do it like the
> latter (if those two are different in a binary sense).

It can't.

Andrew.

Re: Add assembly instruction to GCC

[Dr. H. Nikolaus Schaller]

Am 13.04.2012 um 16:58 schrieb Amir Ghanbari:

> Ok, let me get this straight. I'm not sure how the binary files are
> structured. Shouldn't the address of each instruction be in the binary
> file?
> if I have something like:
>>>>    401ba0 :  f0 0f                     lock mov (bad),%db1"
>>>>    401ba2 :  23 48 89               and    -0x77(%rax),%ecx"
> is it the same as:
>>>>    401ba0 :  f0 0f 23                 lock (bad)
>>>>    401ba3 :  48 89
> aren't those two forms different(they're gonna have different addresses)?
> I want GCC to discriminate between these two forms and do it like the
> latter (if those two are different in a binary sense).

as others already said:

any compiler, assembler and binary file will just generate

... f0 0f 23 48 89 ...

i.e. a byte sequence.

The structure you are looking for is pure virtual. It is done by a DISassembler.

So you have to change your DISassembler.

> 
> On Fri, Apr 13, 2012 at 9:24 AM, Amir Ghanbari <a.ghanbari1990@gmail.com> wrote:
>> The problem is that the binary being generated is not exactly what I
>> want. when I simulate my code, I get an "invalid opcode" error and the
>> address of the instruction is exactly where the disassembly get
>> screwed up. So I believe that's what's happening. I need to make GCC
>> treat that "F0 0F 23" as an instruction and put it in the binary
>> intact and don't mix it with other instructions.
>> I tried defining a machine instruction in GCC for ia64, but I couldn't
>> figure out how to generate the assembly for that instruction.
>> 
>> On Fri, Apr 13, 2012 at 1:15 AM, Ian Lance Taylor <iant@google.com> wrote:
>>> 
>>> Amir Ghanbari <a.ghanbari1990@gmail.com> writes:
>>> 
>>>> I'm trying to expand X86 ISA. So I have added some hardware to X86 (in
>>>> Gem5 Simulator) and I have updated X86 decoder to support those
>>>> instructions. In order to call those instructions I use GCC inline
>>>> assembly ".byte" directive. something like this : ".byte 0xF0, 0x0F,
>>>> 0x23;"
>>>> The problem is when I compile my code using GCC, it changes the
>>>> instructions that i have created. For instance:
>>>> I intend to have something generated like this:
>>>> 
>>>>     48 89 eb               mov    %rbp,%rbx
>>>>     48 83 e3 fe           and    $0xfffffffffffffffe,%rbx
>>>>     48 8b 7c 24 08      mov    0x8(%rsp),%rdi
>>>>     f0 0f 23                lock (bad)
>>>>     48 89 04 24          mov    %rax,(%rsp)
>>>>     4c 8b 34 24          mov    (%rsp),%r14
>>>> 
>>>> but GCC generates something like this:
>>>> 
>>>>     48 89 eb               mov    %rbp,%rbx"
>>>>     48 83 e3 fe           and    $0xfffffffffffffffe,%rbx"
>>>>     48 8b 7c 24 08      mov    0x8(%rsp),%rdi"
>>>>     f0 0f                     lock mov (bad),%db1"
>>>>     23 48 89               and    -0x77(%rax),%ecx"
>>>>     04 24                    add    $0x24,%al"
>>>>     4c 8b 34 24           mov    (%rsp),%r14"
>>>> 
>>>> Is there a way to tell GCC that "F0 0F 23" is a unique instruction so
>>>> it wouldn't mix it with other instructions?
>>> 
>>> I don't understand what you are asking.  GCC does not generate any
>>> output that looks like the lines quoted above.  It looks like you are
>>> showing us the output of a disassembler, but GCC does not include a
>>> disassembler.  And it looks like the bytes that the disassembler is
>>> showing are the bytes that you want, they just aren't being disassembled
>>> the way you want them to be.  It sounds like you need to change your
>>> disassembler to support your instruction.
>>> 
>>> Ian

Re: Add assembly instruction to GCC

[Amir Ghanbari]

Ok, let me get this straight. I'm not sure how the binary files are
structured. Shouldn't the address of each instruction be in the binary
file?
if I have something like:
>>>     401ba0 :  f0 0f                     lock mov (bad),%db1"
>>>     401ba2 :  23 48 89               and    -0x77(%rax),%ecx"
is it the same as:
>>>     401ba0 :  f0 0f 23                 lock (bad)
>>>     401ba3 :  48 89
aren't those two forms different(they're gonna have different addresses)?
I want GCC to discriminate between these two forms and do it like the
latter (if those two are different in a binary sense).

On Fri, Apr 13, 2012 at 9:24 AM, Amir Ghanbari <a.ghanbari1990@gmail.com> wrote:
> The problem is that the binary being generated is not exactly what I
> want. when I simulate my code, I get an "invalid opcode" error and the
> address of the instruction is exactly where the disassembly get
> screwed up. So I believe that's what's happening. I need to make GCC
> treat that "F0 0F 23" as an instruction and put it in the binary
> intact and don't mix it with other instructions.
> I tried defining a machine instruction in GCC for ia64, but I couldn't
> figure out how to generate the assembly for that instruction.
>
> On Fri, Apr 13, 2012 at 1:15 AM, Ian Lance Taylor <iant@google.com> wrote:
>>
>> Amir Ghanbari <a.ghanbari1990@gmail.com> writes:
>>
>> > I'm trying to expand X86 ISA. So I have added some hardware to X86 (in
>> > Gem5 Simulator) and I have updated X86 decoder to support those
>> > instructions. In order to call those instructions I use GCC inline
>> > assembly ".byte" directive. something like this : ".byte 0xF0, 0x0F,
>> > 0x23;"
>> > The problem is when I compile my code using GCC, it changes the
>> > instructions that i have created. For instance:
>> > I intend to have something generated like this:
>> >
>> >     48 89 eb               mov    %rbp,%rbx
>> >     48 83 e3 fe           and    $0xfffffffffffffffe,%rbx
>> >     48 8b 7c 24 08      mov    0x8(%rsp),%rdi
>> >     f0 0f 23                lock (bad)
>> >     48 89 04 24          mov    %rax,(%rsp)
>> >     4c 8b 34 24          mov    (%rsp),%r14
>> >
>> > but GCC generates something like this:
>> >
>> >     48 89 eb               mov    %rbp,%rbx"
>> >     48 83 e3 fe           and    $0xfffffffffffffffe,%rbx"
>> >     48 8b 7c 24 08      mov    0x8(%rsp),%rdi"
>> >     f0 0f                     lock mov (bad),%db1"
>> >     23 48 89               and    -0x77(%rax),%ecx"
>> >     04 24                    add    $0x24,%al"
>> >     4c 8b 34 24           mov    (%rsp),%r14"
>> >
>> > Is there a way to tell GCC that "F0 0F 23" is a unique instruction so
>> > it wouldn't mix it with other instructions?
>>
>> I don't understand what you are asking.  GCC does not generate any
>> output that looks like the lines quoted above.  It looks like you are
>> showing us the output of a disassembler, but GCC does not include a
>> disassembler.  And it looks like the bytes that the disassembler is
>> showing are the bytes that you want, they just aren't being disassembled
>> the way you want them to be.  It sounds like you need to change your
>> disassembler to support your instruction.
>>
>> Ian

Re: Add assembly instruction to GCC

[Andrew Haley]

On 04/13/2012 02:24 PM, Amir Ghanbari wrote:
> The problem is that the binary being generated is not exactly what I
> want. when I simulate my code, I get an "invalid opcode" error and the
> address of the instruction is exactly where the disassembly get
> screwed up. So I believe that's what's happening. I need to make GCC
> treat that "F0 0F 23" as an instruction and put it in the binary
> intact and don't mix it with other instructions.

GCC has done that.  It's here:

>>>     f0 0f                     lock mov (bad),%db1"
>>>     23 48 89               and    -0x77(%rax),%ecx"

This is your f0 0f 23, just as you asked.

Andrew.

Re: Add assembly instruction to GCC

[Amir Ghanbari]

The problem is that the binary being generated is not exactly what I
want. when I simulate my code, I get an "invalid opcode" error and the
address of the instruction is exactly where the disassembly get
screwed up. So I believe that's what's happening. I need to make GCC
treat that "F0 0F 23" as an instruction and put it in the binary
intact and don't mix it with other instructions.
I tried defining a machine instruction in GCC for ia64, but I couldn't
figure out how to generate the assembly for that instruction.

On Fri, Apr 13, 2012 at 1:15 AM, Ian Lance Taylor <iant@google.com> wrote:
>
> Amir Ghanbari <a.ghanbari1990@gmail.com> writes:
>
> > I'm trying to expand X86 ISA. So I have added some hardware to X86 (in
> > Gem5 Simulator) and I have updated X86 decoder to support those
> > instructions. In order to call those instructions I use GCC inline
> > assembly ".byte" directive. something like this : ".byte 0xF0, 0x0F,
> > 0x23;"
> > The problem is when I compile my code using GCC, it changes the
> > instructions that i have created. For instance:
> > I intend to have something generated like this:
> >
> >     48 89 eb               mov    %rbp,%rbx
> >     48 83 e3 fe           and    $0xfffffffffffffffe,%rbx
> >     48 8b 7c 24 08      mov    0x8(%rsp),%rdi
> >     f0 0f 23                lock (bad)
> >     48 89 04 24          mov    %rax,(%rsp)
> >     4c 8b 34 24          mov    (%rsp),%r14
> >
> > but GCC generates something like this:
> >
> >     48 89 eb               mov    %rbp,%rbx"
> >     48 83 e3 fe           and    $0xfffffffffffffffe,%rbx"
> >     48 8b 7c 24 08      mov    0x8(%rsp),%rdi"
> >     f0 0f                     lock mov (bad),%db1"
> >     23 48 89               and    -0x77(%rax),%ecx"
> >     04 24                    add    $0x24,%al"
> >     4c 8b 34 24           mov    (%rsp),%r14"
> >
> > Is there a way to tell GCC that "F0 0F 23" is a unique instruction so
> > it wouldn't mix it with other instructions?
>
> I don't understand what you are asking.  GCC does not generate any
> output that looks like the lines quoted above.  It looks like you are
> showing us the output of a disassembler, but GCC does not include a
> disassembler.  And it looks like the bytes that the disassembler is
> showing are the bytes that you want, they just aren't being disassembled
> the way you want them to be.  It sounds like you need to change your
> disassembler to support your instruction.
>
> Ian

Re: Add assembly instruction to GCC

[Ian Lance Taylor]

Amir Ghanbari <a.ghanbari1990@gmail.com> writes:

> I'm trying to expand X86 ISA. So I have added some hardware to X86 (in
> Gem5 Simulator) and I have updated X86 decoder to support those
> instructions. In order to call those instructions I use GCC inline
> assembly ".byte" directive. something like this : ".byte 0xF0, 0x0F,
> 0x23;"
> The problem is when I compile my code using GCC, it changes the
> instructions that i have created. For instance:
> I intend to have something generated like this:
>
>     48 89 eb               mov    %rbp,%rbx
>     48 83 e3 fe           and    $0xfffffffffffffffe,%rbx
>     48 8b 7c 24 08      mov    0x8(%rsp),%rdi
>     f0 0f 23                lock (bad)
>     48 89 04 24          mov    %rax,(%rsp)
>     4c 8b 34 24          mov    (%rsp),%r14
>
> but GCC generates something like this:
>
>     48 89 eb               mov    %rbp,%rbx"
>     48 83 e3 fe           and    $0xfffffffffffffffe,%rbx"
>     48 8b 7c 24 08      mov    0x8(%rsp),%rdi"
>     f0 0f                     lock mov (bad),%db1"
>     23 48 89               and    -0x77(%rax),%ecx"
>     04 24                    add    $0x24,%al"
>     4c 8b 34 24           mov    (%rsp),%r14"
>
> Is there a way to tell GCC that "F0 0F 23" is a unique instruction so
> it wouldn't mix it with other instructions?

I don't understand what you are asking.  GCC does not generate any
output that looks like the lines quoted above.  It looks like you are
showing us the output of a disassembler, but GCC does not include a
disassembler.  And it looks like the bytes that the disassembler is
showing are the bytes that you want, they just aren't being disassembled
the way you want them to be.  It sounds like you need to change your
disassembler to support your instruction.

Ian

Add assembly instruction to GCC

[Amir Ghanbari]

Hello all,

I'm trying to expand X86 ISA. So I have added some hardware to X86 (in
Gem5 Simulator) and I have updated X86 decoder to support those
instructions. In order to call those instructions I use GCC inline
assembly ".byte" directive. something like this : ".byte 0xF0, 0x0F,
0x23;"
The problem is when I compile my code using GCC, it changes the
instructions that i have created. For instance:
I intend to have something generated like this:

    48 89 eb               mov    %rbp,%rbx
    48 83 e3 fe           and    $0xfffffffffffffffe,%rbx
    48 8b 7c 24 08      mov    0x8(%rsp),%rdi
    f0 0f 23                lock (bad)
    48 89 04 24          mov    %rax,(%rsp)
    4c 8b 34 24          mov    (%rsp),%r14

but GCC generates something like this:

    48 89 eb               mov    %rbp,%rbx"
    48 83 e3 fe           and    $0xfffffffffffffffe,%rbx"
    48 8b 7c 24 08      mov    0x8(%rsp),%rdi"
    f0 0f                     lock mov (bad),%db1"
    23 48 89               and    -0x77(%rax),%ecx"
    04 24                    add    $0x24,%al"
    4c 8b 34 24           mov    (%rsp),%r14"

Is there a way to tell GCC that "F0 0F 23" is a unique instruction so
it wouldn't mix it with other instructions?
Thank you,
--
Amir