From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 10632 invoked by alias); 5 Jun 2013 04:30:04 -0000 Mailing-List: contact gcc-help-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-help-owner@gcc.gnu.org Received: (qmail 10547 invoked by uid 89); 5 Jun 2013 04:29:58 -0000 X-Spam-SWARE-Status: No, score=-4.5 required=5.0 tests=AWL,BAYES_00,KHOP_THREADED,RCVD_IN_DNSWL_LOW,RCVD_IN_HOSTKARMA_YE,RP_MATCHES_RCVD,SPF_PASS autolearn=ham version=3.3.1 Received: from mail-ie0-f177.google.com (HELO mail-ie0-f177.google.com) (209.85.223.177) by sourceware.org (qpsmtpd/0.84/v0.84-167-ge50287c) with ESMTP; Wed, 05 Jun 2013 04:29:58 +0000 Received: by mail-ie0-f177.google.com with SMTP id u16so2327092iet.8 for ; Tue, 04 Jun 2013 21:29:56 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=google.com; s=20120113; h=mime-version:in-reply-to:references:date:message-id:subject:from:to :cc:content-type:x-gm-message-state; bh=046EAl6l9Bw+6KbXzRItZthcoqx6jXDy2W9KJTjKxvU=; b=l7DKYMnDi0JFPJDJoqwZzuv4mFlct9SQuFdo7ASPBTWtrRtBbGFYDQx33a88DIJdih aW07vsij1pVPjXtq9mQy2CwuSJaweAjxt7yIEPDItTJWQbnKihITyexLoHYh5a72AKjT OGwWO0Eq0FgBjgLsMiMzdg4lOPgi8wfMpK757OcytokvnVUTKv5xBGgv9NGJs4J6QLiD dPokdENaTDozCoeNv5aTfD5bbKPEKsE1j6EVPXTajMjy1UQ1nrH46Ok5QFpIpDrzdKyq t/PMH8o5SilT2Lj7zNdoTck0UlnTFnNpqfhWCjcPouybhKibksVcrtAfEfk5reQeL54a uzHA== MIME-Version: 1.0 X-Received: by 10.50.6.107 with SMTP id z11mr2386424igz.17.1370406596231; Tue, 04 Jun 2013 21:29:56 -0700 (PDT) Received: by 10.64.9.39 with HTTP; Tue, 4 Jun 2013 21:29:55 -0700 (PDT) In-Reply-To: <51AEA657.9080607@yahoo.com> References: <51AE7119.5090000@yahoo.com> <51AEA657.9080607@yahoo.com> Date: Wed, 05 Jun 2013 04:30:00 -0000 Message-ID: Subject: Re: Question about __builtin_ia32_mfence and memory barriers From: Ian Lance Taylor To: dw Cc: "gcc-help@gcc.gnu.org" Content-Type: text/plain; charset=ISO-8859-1 X-Gm-Message-State: ALoCoQk3f1oM9GGziVjGNwEzhBw1BRujJ6t/kBKRIBpCfNGfIqTFraFrvbEQa1uPwjTNlk3EY6dhspnwCqlhPsDVFIcsvwgq2xP9twF+5UuMIzmbrqGAXhdoOemgqzyLzXF7dSyGdKoSg666LTjWb5jVeAdV9pbnr4Ivio2O5VDSdkfudVZvK5q7uz+IzGO4B9GSooYgf33I X-SW-Source: 2013-06/txt/msg00030.txt.bz2 On Tue, Jun 4, 2013 at 7:45 PM, dw wrote: > And while I get an mfence instruction with this: > > __atomic_thread_fence(__ATOMIC_SEQ_CST); > > It doesn't produce quite the same instruction ordering as: > > asm volatile ("mfence" ::: "memory"); > > Which makes me think that whatever __ATOMIC_SEQ_CST means, it's not the same > as the "memory" clobber. It's not the same as the "memory" clobber, but it should have the effect of providing both an mfence instruction and a compiler memory barrier. > Also, I'm looking to support SFENCE and LFENCE, > which these don't appear to support at all. That is true. I think the only supported way to get those is the Intel intrinsics _mm_sfence and _mm_lfence. Ian