From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 25122 invoked by alias); 11 Jun 2013 00:41:23 -0000 Mailing-List: contact gcc-help-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-help-owner@gcc.gnu.org Received: (qmail 25092 invoked by uid 89); 11 Jun 2013 00:41:23 -0000 X-Spam-SWARE-Status: No, score=-3.0 required=5.0 tests=AWL,BAYES_00,FREEMAIL_FROM,KHOP_THREADED,RCVD_IN_DNSWL_LOW,RCVD_IN_HOSTKARMA_YE,SPF_PASS autolearn=ham version=3.3.1 Received: from mail-lb0-f178.google.com (HELO mail-lb0-f178.google.com) (209.85.217.178) by sourceware.org (qpsmtpd/0.84/v0.84-167-ge50287c) with ESMTP; Tue, 11 Jun 2013 00:41:22 +0000 Received: by mail-lb0-f178.google.com with SMTP id y6so5344698lbh.23 for ; Mon, 10 Jun 2013 17:41:19 -0700 (PDT) MIME-Version: 1.0 X-Received: by 10.152.4.163 with SMTP id l3mr6158565lal.60.1370911278421; Mon, 10 Jun 2013 17:41:18 -0700 (PDT) Received: by 10.114.79.233 with HTTP; Mon, 10 Jun 2013 17:41:18 -0700 (PDT) In-Reply-To: References: Date: Tue, 11 Jun 2013 00:41:00 -0000 Message-ID: Subject: Re: Thumb inline assembly From: Kalai Rajah N To: Ian Lance Taylor Cc: "gcc-help@gcc.gnu.org" Content-Type: text/plain; charset=ISO-8859-1 X-SW-Source: 2013-06/txt/msg00066.txt.bz2 Here is the C code that I used ... #include // NVIC Interrupt Set-Enable Registers #define NVIC_ISER0 0xE000E100 #define NVIC_ISER1 0xE000E104 #define NVIC_ISER2 0xE000E108 #define NVIC_ISER3 0xE000E10C #define NVIC_ISER4 0xE000E110 #define NVIC_ISER5 0xE000E114 #define NVIC_ISER6 0xE000E118 #define NVIC_ISER7 0xE000E11C //reset values #define RESET 0x00000000 //status flag #define GOOD 0x600DC0DE #define DEAD 0xDEADC0DE #define BAD 0xBAADC0DE void check_reset_value(int addr, int reset, int status){ asm volatile( "ldr r2, =8 /* number of register */ \n\t" "ldr r1, =%0 /* load the nvic_iser* register */ \n\t" "read_reg:\n\t" "sub r2, r2, #1\n\t" "ldr r0, [r1]\n\t" "add r1, r1, #4 /* go to the next register */ \n\t" "cmp r0, %1\n\t" "beq read_reg_ok\n\t" "ldr r3, =%2\n\t" "str r3, [%4] /* update status flag */\n\t" "read_reg_ok:\n\t" "cmp r2, #0\n\t" "bne read_reg\n\t" "ldr r3, =%3\n\t" "str r3, [%4] /* update status flag */\n\t" : : "r" (addr), "r" (reset), "r" (BAD), "r" (GOOD), "r" (status) //: "r0", "r1", "r2", "r3" //: ); } int main() { volatile int nvic_iser_status = DEAD; check_reset_value(NVIC_ISER0, RESET, nvic_iser_status); } This is on cortex-m3, so I'm passing -mthumb -mcpu=cortex-m3 to the compiler On Mon, Jun 10, 2013 at 5:31 PM, Ian Lance Taylor wrote: >> From: Kalai Rajah N >> Date: Mon, Jun 10, 2013 at 5:19 PM >> Subject: Re: Thumb inline assembly >> To: Ian Lance Taylor >> >> >> If the clobber-list is removed, the errors are on r1,r2, r3 and the >> generated assembly code is ... > > When you clobber r0 through r3 they can't be used as input registers. > > I still haven't seen a complete standalone test case, but perhaps GCC > is in ARM mode but you are generating Thumb assembly code. > > Ian