ARM register constraint

ARM register constraint

[Shaun Jackman]

I took this function from the ARM documentation to load an unaligned pointer. 
It has one constraint that I can't seem to express though. %0 must be less 
than %3. (ie r1 and r2, not r2 and r1) or the ldmia will end up with the 
values swapped in those two registers. How can I express this constraint to 
GCC?

Please cc me as I'm not a member of this list,
Thanks,
Shaun

/**
 * unaligned load
 */
uint32
ld32( const uint32* p)
{
	uint32 ret, a, b;
	// enter with address in %1 (32 bits)
	// uses %2, %3; result in %0.
	// Note %0 must be less than %3 e.g. 0,1
	asm(
			"\n\t@ get word aligned address"
			"\n\tbic %2,%1,#3"
			"\n\t@ get 64 bits containing answer"
			"\n\tldmia %2,{%0,%3}"
			"\n\t@ correction factor in bytes"
			"\n\tand %2,%1,#3"
			"\n\t@ ...now in bits and test if aligned"
			"\n\tmovs %2,%2,lsl#3"
			"\n\t@ produce bottom of result word ; (if not aligned)"
			"\n\tmovne %0,%0,lsr %2"
			"\n\t@ get other shift amount"
			"\n\trsbne %2,%2,#32"
			"\n\t@ combine two halves to get result"
			"\n\torrne %0,%0,%3,lsl %2"
			: "=r" (ret), "+r" (p), "=r" (a), "=r" (b));
	return ret;
}