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From: Andrew Haley <aph@redhat.com>
To: Zdenek Sojka <zsojka@seznam.cz>
Cc: gcc-help@gcc.gnu.org
Subject: Re: [x86 inline asm]: width of register arguments
Date: Tue, 02 Jul 2019 10:41:00 -0000	[thread overview]
Message-ID: <c02cb21c-7b80-3493-72c9-8eb659ab1c95@redhat.com> (raw)
In-Reply-To: <P25.2}Wj.e}LAv6wZ8i.1T6ksQ@seznam.cz>

On 7/2/19 6:37 AM, Zdenek Sojka wrote:
> Ok, shame - it seems to behave so in my experiments:

It's more complicated than that. Sometimes the size of the operand is
in the name of the instruction and sometimes you need to force the
size yourself.

For example, with int a, x:

  asm("mov %1, %0" : "=&r"(a) : "r"(x));

generates

	mov %edx, %eax

but

  asm("mov %b1, %b0" : "=&r"(a) : "r"(x));

generates

	mov %dl, %al

For a real-world example,

static __inline void
outb_p (unsigned char __value, unsigned short int __port)
{
  __asm__ __volatile__ ("outb %b0,%w1\noutb %%al,$0x80": :"a" (__value),
                  "Nd" (__port));
}

On x86 the special asm out single letter directives following a '%'
are defined in i386.md.

I'm a bit paranoid about this stuff because my memory of GCC's inline
asm goes back decades to when it was far more fragile than it is now.

-- 
Andrew Haley  (he/him)
Java Platform Lead Engineer
Red Hat UK Ltd. <https://www.redhat.com>
https://keybase.io/andrewhaley
EAC8 43EB D3EF DB98 CC77 2FAD A5CD 6035 332F A671

  reply	other threads:[~2019-07-02 10:41 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-06-24 12:19 Zdenek Sojka
2019-06-29 16:10 ` Andrew Haley
2019-07-02  5:37   ` Zdenek Sojka
2019-07-02 10:41     ` Andrew Haley [this message]
2019-07-02 15:19       ` Segher Boessenkool
2019-07-03  7:32         ` Zdenek Sojka
2019-07-03 13:57           ` Segher Boessenkool

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