From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail.gigawatt.nl (mail.gigawatt.nl [IPv6:2001:41d0:801:2000::19e9]) by sourceware.org (Postfix) with ESMTPS id 8F6393857802 for ; Mon, 5 Oct 2020 13:26:21 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.3.2 sourceware.org 8F6393857802 Received: from [192.168.1.8] (hvdijk.plus.com [81.174.157.28]) by mail.gigawatt.nl (Postfix) with ESMTPSA id A2E9F130; Mon, 5 Oct 2020 15:26:19 +0200 (CEST) DKIM-Filter: OpenDKIM Filter v2.11.0 mail.gigawatt.nl A2E9F130 Subject: Re: Inline assembly and value extensions To: Segher Boessenkool Cc: gcc-help@gcc.gnu.org References: <8985cc81-573c-b011-4e02-aa9829524133@gigawatt.nl> <3c338ceb-1dfa-5c15-8295-5b5a7dd4bad7@gigawatt.nl> <20201005125328.GA2672@gate.crashing.org> From: Harald van Dijk Message-ID: Date: Mon, 5 Oct 2020 14:26:19 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.1.1 MIME-Version: 1.0 In-Reply-To: <20201005125328.GA2672@gate.crashing.org> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit X-Spam-Status: No, score=-3.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, NICE_REPLY_A, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.2 X-Spam-Checker-Version: SpamAssassin 3.4.2 (2018-09-13) on server2.sourceware.org X-BeenThere: gcc-help@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-help mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 05 Oct 2020 13:26:24 -0000 On 05/10/2020 13:53, Segher Boessenkool wrote: > On Sat, Oct 03, 2020 at 09:42:40PM +0100, Harald van Dijk via Gcc-help wrote: >> On 22/08/2020 16:30, Harald van Dijk wrote: >>> This function gets an extra "movl %eax, %eax" between the hand-written >>> movl and the generated ret, which can be seen online at >>> . This extra movl is there to ensure the >>> high bits of %rax are zero, but the initial movl already achieves that. >>> How can I inform GCC that it does not need to emit that extra movl? > > If your asm returns a 32-bit value, then GCC will not know what is in > the top 32 bits of the 64-bit register. > >>> Likewise, is there an easy way to provide an inline assembly statement >>> with a zero-extended pointer input? This one I am able to work around, >>> as it is possible to instead of passing in a pointer value p, pass in an >>> integer value (uint64_t)(uint32_t)p, but the workaround is kind of hard >>> to read and I would like to avoid that if possible. > > You can use much less chatty names for those very basic types (like u64 > and u32), that makes it more readable. Hiding what you do will not make > it more readable, that is just obfuscation, so using macros is not such > a good idea. Inline asm is hard enough when you can see all there is > right in front of your eyes. I am not trying to hide anything. I am trying to pass in a pointer value in the same way that they are passed in all other cases. In the x32 ABI, the way pointer values are passed is by passing them in 64-bit registers with the high 32 bits zeroed, except in inline assembly. I'm trying to get the inline assembly to not be a special case. >>> I looked the documentation for either relevant inline assembly >>> constraints or relevant variable / type attributes, but was unable to >>> find any. The most promising search result was the mode attribute, I was >>> hoping it might be possible to give result a mode(DI) attribute, but the >>> compiler rejects that. > > Constraints just say which register (or memory addressed how, or what > kind of constnt). The normal way to say something should have a certain > mode is by giving it a corresponding type in C (so SImode is "int" in C, > and DImode is "long long"; "long" is either, it depends on your ABI; > "u64" and "u32" should always be clear ;-) ) In the x32 ABI, pointers do not have a single mode. They are SImode, except when passed as parameters or returned, in which case they are DImode (see the ix86_promote_function_mode function I mentioned). This is really the source of the problems. The value that I want to return is a pointer, and the assembly is returning a pointer. There should not be any need for extra code to convert the value returned from the assembly to the value returned from the function, since they are already the same type, but there is, because they are not the same mode. >> I have now found that forcing a different mode appears to be exactly how >> the zero-extension of arguments and return values is implemented: that >> is what ix86_promote_function_mode does. >> >> The fact that this is not an option through variable attributes or >> inline assembly constraints looks like an unfortunate limitation of the >> inline assembly functionality, there is currently just no way to do what >> I am after. I very much hope to be proved wrong, but will try to just >> pick a workaround that does not look too bad. >> >>> Is there another approach that I can use instead? > > You use a 64-bit expression (or preferably even a 64-bit variable). The > same is true for outputs from the asm. That does not work for outputs though. Without informing GCC somehow that the high 32 bits of that 64-bit expression are zero, it will still emit an extra extension. > One way of making the code easier to read is to actually use 64-bit > variables for all these things in the asm, and then assign them from and > to the 32-bit things. > > int x; > char *p; > u64 xx = x; > u64 pp = (u64)p; > asm("smth %0,%1" : "+r"(pp), "+r"(xx)); > p = (char *)pp; > x = xx; See for what happens when I modify the example I had provided to use a 64-bit variable like you suggested: that requires adding a cast in the return statement, and now it's that conversion that forces the extra "movl %eax, %eax". It cannot be avoided that way. > Segher