ins instruction is not produced in the assembly code (mips32r2)

ins instruction is not produced in the assembly code (mips32r2)

[fanqifei]

Hello,
I am tring to compile a small c file using gcc4.1.2.
The source code:
struct test_foo {
unsigned int a:18;
unsigned int b:2;
unsigned int c:12;
};

struct test_foo x;
unsigned int foo()
{
    unsigned int a=x.b;
    x.b=2;
    return a;
}

the command: mipsel-linux-gcc -mips32r2 -O2 -c -Wall foo.c -o foo.o

The corresponding disassembly code:
foo.o:     file format elf32-tradlittlemips
Disassembly of section .text:
00000000 <foo>:
   0:   3c1c0000    lui gp,0x0
   4:   279c0000    addiu   gp,gp,0
   8:   0399e021    addu    gp,gp,t9
   c:   8f850000    lw  a1,0(gp)
  10:   3c03fff3    lui v1,0xfff3
  14:   3463ffff    ori v1,v1,0xffff
  18:   8ca20000    lw  v0,0(a1)
  1c:   3c040008    lui a0,0x8
  20:   00431824    and v1,v0,v1
  24:   00641825    or  v1,v1,a0
  28:   7c420c80    ext v0,v0,0x12,0x2
  2c:   03e00008    jr  ra
  30:   aca30000    sw  v1,0(a1)

The statement x.b=2 can be simply translated to lb and ins
instructions( ins is in mips32r2).

I wonder how ins instrution can be produced.
More specifically, how can gcc generates the insv pattern in RTL?
Is it related to the coding style -- using bit filed or logical
operations(shift, and ...)?

Thanks.
Qifei

Re: ins instruction is not produced in the assembly code (mips32r2)

[Andrew Haley]

On 01/12/2010 07:28 AM, fanqifei wrote:
>>> I still not understand when the insn "insv" in target.md can be used
>>> in the RTL representation of the code.
>>
>> I already told you in my previous message.  Did you not see it?

> 
> Hi Andrew, I did see it. But that's not exactly what I want.
> Is the builtin function the only way to utilize ins instruction?
> According to the webpage
> http://gcc.gnu.org/ml/gcc-patches/2005-05/msg02430.html, the builtin
> functions are introduced for the DSP extension. As INS instruction is
> introduced in MIPS32 R2 too(not exactly the same as in DSP extension),
> I guess there must be another method to utilize ins instruction of
> MIPS32R2 except inline asm or builtin functions.

I grepped through the gcc back-end.  There is code to use insv and
extv in bitfield accesses.  I'm not really sure what is going on in
your case.

I think David Daney is right: make sure that with the latest
development version of gcc and the correct options this still happens,
and file a bug report.

Andrew.

Re: ins instruction is not produced in the assembly code (mips32r2)

[fanqifei]

> > I still not understand when the insn "insv" in target.md can be used
> > in the RTL representation of the code.
>
> I already told you in my previous message.  Did you not see it?
>
>  __builtin_mips_insv
>
> Andrew.
>

Hi Andrew, I did see it. But that's not exactly what I want.
Is the builtin function the only way to utilize ins instruction?
According to the webpage
http://gcc.gnu.org/ml/gcc-patches/2005-05/msg02430.html, the builtin
functions are introduced for the DSP extension. As INS instruction is
introduced in MIPS32 R2 too(not exactly the same as in DSP extension),
I guess there must be another method to utilize ins instruction of
MIPS32R2 except inline asm or builtin functions.
More specifically, can gcc recognize the pattern of ins and output ins
instruction in the assembly file? Even for other cpu architecture(not
MIPS) which has similar instruction like ins.
I really appreciate your help.

-fanqifei

Re: ins instruction is not produced in the assembly code (mips32r2)

[David Daney]

fanqifei wrote:
> Is there anyone can help?
> I am curious about how the insv pattern can be used in the compiling process.
> Otherwise, I have to write inline assembly code.
> Thanks very much!
> 

You don't state which compiler version you are using.  I would suggest 
trying a GCC-4.5 snapshot.  I know that some work has been recently done 
to make better use of INS.

If GCC-4.5 doesn't help, you could file a GCC bug report about this 
missed optimization.

David Daney



> 2009/12/16 fanqifei <fanqifei@gmail.com>:
>> Hello,
>> I am tring to compile a small c file using gcc4.1.2.
>> The source code:
>> struct test_foo {
>> unsigned int a:18;
>> unsigned int b:2;
>> unsigned int c:12;
>> };
>>
>> struct test_foo x;
>> unsigned int foo()
>> {
>>     unsigned int a=x.b;
>>     x.b=2;
>>     return a;
>> }
>>
>> the command: mipsel-linux-gcc -mips32r2 -O2 -c -Wall foo.c -o foo.o
>>
>> The corresponding disassembly code:
>> foo.o:     file format elf32-tradlittlemips
>> Disassembly of section .text:
>> 00000000 <foo>:
>>    0:   3c1c0000    lui gp,0x0
>>    4:   279c0000    addiu   gp,gp,0
>>    8:   0399e021    addu    gp,gp,t9
>>    c:   8f850000    lw  a1,0(gp)
>>   10:   3c03fff3    lui v1,0xfff3
>>   14:   3463ffff    ori v1,v1,0xffff
>>   18:   8ca20000    lw  v0,0(a1)
>>   1c:   3c040008    lui a0,0x8
>>   20:   00431824    and v1,v0,v1
>>   24:   00641825    or  v1,v1,a0
>>   28:   7c420c80    ext v0,v0,0x12,0x2
>>   2c:   03e00008    jr  ra
>>   30:   aca30000    sw  v1,0(a1)
>> The statement x.b=2 can be simply translated to lb and ins instructions( ins
>> is in mips32r2).
>>
>> I wonder how ins instrution can be produced.
>> More specifically, how can gcc generates the insv pattern in RTL?
>> Is it related to the coding style -- using bit filed or logical
>> operations(shift, and ...)?
>> Thanks.
>> Qifei
>>
>>
> 
> 
> 

Re: ins instruction is not produced in the assembly code (mips32r2)

[Andrew Haley]

fanqifei wrote:
> Thanks, Andrew.

Please don't top-post.

> I still not understand when the insn "insv" in target.md can be used
> in the RTL representation of the code.

I already told you in my previous message.  Did you not see it?

 __builtin_mips_insv

Andrew.


> 2009/12/18 Andrew Haley <aph@redhat.com>:
>> fanqifei wrote:
>>> The instruction sequence generated by gcc can be simply rewritten by
>>> three instructions.
>>> Apparently gcc should find the expression storing to bit-field and use
>>> pattern insv. But it didn't.
>>>
>>> gcc:
>>>  10:   3c03fff3    lui v1,0xfff3
>>>  14:   3463ffff    ori v1,v1,0xffff
>>>  18:   8ca20000    lw  v0,0(a1)
>>>  1c:   3c040008    lui a0,0x8
>>>  20:   00431824    and v1,v0,v1
>>>  24:   00641825    or  v1,v1,a0
>>>
>>> with ins:
>>> lw v0,0(a1)
>>> ori a0, $0, 2
>>> ins v0,v0,19,18
>> I can't see anything in gcc that would use an ins instruction to do that.
>>
>> Andrew.
>>
> 
> 
> 

Re: ins instruction is not produced in the assembly code (mips32r2)

[fanqifei]

Thanks, Andrew.
I still not understand when the insn "insv" in target.md can be used
in the RTL representation of the code.

2009/12/18 Andrew Haley <aph@redhat.com>:
> fanqifei wrote:
>> The instruction sequence generated by gcc can be simply rewritten by
>> three instructions.
>> Apparently gcc should find the expression storing to bit-field and use
>> pattern insv. But it didn't.
>>
>> gcc:
>>  10:   3c03fff3    lui v1,0xfff3
>>  14:   3463ffff    ori v1,v1,0xffff
>>  18:   8ca20000    lw  v0,0(a1)
>>  1c:   3c040008    lui a0,0x8
>>  20:   00431824    and v1,v0,v1
>>  24:   00641825    or  v1,v1,a0
>>
>> with ins:
>> lw v0,0(a1)
>> ori a0, $0, 2
>> ins v0,v0,19,18
>
> I can't see anything in gcc that would use an ins instruction to do that.
>
> Andrew.
>



-- 
        Qifei Fan

Re: ins instruction is not produced in the assembly code (mips32r2)

[Andrew Haley]

fanqifei wrote:
> The instruction sequence generated by gcc can be simply rewritten by
> three instructions.
> Apparently gcc should find the expression storing to bit-field and use
> pattern insv. But it didn't.
> 
> gcc:
>  10:   3c03fff3    lui v1,0xfff3
>  14:   3463ffff    ori v1,v1,0xffff
>  18:   8ca20000    lw  v0,0(a1)
>  1c:   3c040008    lui a0,0x8
>  20:   00431824    and v1,v0,v1
>  24:   00641825    or  v1,v1,a0
> 
> with ins:
> lw v0,0(a1)
> ori a0, $0, 2
> ins v0,v0,19,18

I can't see anything in gcc that would use an ins instruction to do that.

Andrew.

Re: ins instruction is not produced in the assembly code (mips32r2)

[fanqifei]

code size and execution time can be saved if ins is used in the assembly code.
I don't want to write assembly code by hand. But hope gcc can generate
it automatically.
My code is not all such assignments but contains some.

2009/12/18 Ineiev <ineiev@gmail.com>:
> On 12/18/09, fanqifei <fanqifei@gmail.com> wrote:
>> 2009/12/18 Ineiev <ineiev@gmail.com>:
>>> On 12/18/09, fanqifei <fanqifei@gmail.com> wrote:
>>>> Otherwise, I have to write inline assembly code.
>>>
>>> Out of curiosity --- why do you think your executable has to use this
>>> pattern?
>> The instruction sequence generated by gcc can be simply rewritten by
>> three instructions.
>
> I see, thank you.
>
>> Apparently gcc should find the expression storing to bit-field and use
>> pattern insv. But it didn't.
>
> I'm sorry (really), as I know nothing about the target architecture,
> this is not apparent _for me_.
>
> What I don't understand is why you _has_ to code it in assembler?
> is your program essentially nothing but such assignments?
> or the code gcc provides assigns something wrong?
>
> I bag your pardon if this is too off-topic,
> Ineiev
>



-- 
        Qifei Fan

Re: ins instruction is not produced in the assembly code (mips32r2)

[Ineiev]

On 12/18/09, fanqifei <fanqifei@gmail.com> wrote:
> 2009/12/18 Ineiev <ineiev@gmail.com>:
>> On 12/18/09, fanqifei <fanqifei@gmail.com> wrote:
>>> Otherwise, I have to write inline assembly code.
>>
>> Out of curiosity --- why do you think your executable has to use this
>> pattern?
> The instruction sequence generated by gcc can be simply rewritten by
> three instructions.

I see, thank you.

> Apparently gcc should find the expression storing to bit-field and use
> pattern insv. But it didn't.

I'm sorry (really), as I know nothing about the target architecture,
this is not apparent _for me_.

What I don't understand is why you _has_ to code it in assembler?
is your program essentially nothing but such assignments?
or the code gcc provides assigns something wrong?

I bag your pardon if this is too off-topic,
Ineiev

Re: ins instruction is not produced in the assembly code (mips32r2)

[fanqifei]

The instruction sequence generated by gcc can be simply rewritten by
three instructions.
Apparently gcc should find the expression storing to bit-field and use
pattern insv. But it didn't.

gcc:
 10:   3c03fff3    lui v1,0xfff3
 14:   3463ffff    ori v1,v1,0xffff
 18:   8ca20000    lw  v0,0(a1)
 1c:   3c040008    lui a0,0x8
 20:   00431824    and v1,v0,v1
 24:   00641825    or  v1,v1,a0

with ins:
lw v0,0(a1)
ori a0, $0, 2
ins v0,v0,19,18


2009/12/18 Ineiev <ineiev@gmail.com>:
> On 12/18/09, fanqifei <fanqifei@gmail.com> wrote:
>> Is there anyone can help?
>> I am curious about how the insv pattern can be used in the compiling
>> process.
>> Otherwise, I have to write inline assembly code.
>
> Out of curiosity --- why do you think your executable has to use this pattern?
>
> Regards,
> Ineiev
>

-- 
        Qifei Fan

Re: ins instruction is not produced in the assembly code (mips32r2)

[Ineiev]

On 12/18/09, fanqifei <fanqifei@gmail.com> wrote:
> Is there anyone can help?
> I am curious about how the insv pattern can be used in the compiling
> process.
> Otherwise, I have to write inline assembly code.

Out of curiosity --- why do you think your executable has to use this pattern?

Regards,
Ineiev

Re: ins instruction is not produced in the assembly code (mips32r2)

[Andrew Haley]

fanqifei wrote:
> Is there anyone can help?
> I am curious about how the insv pattern can be used in the compiling process.
> Otherwise, I have to write inline assembly code.

Use __builtin_mips_insv (i32, i32)

Andrew.


> Thanks very much!
> 
> 2009/12/16 fanqifei <fanqifei@gmail.com>:
>> Hello,
>> I am tring to compile a small c file using gcc4.1.2.
>> The source code:
>> struct test_foo {
>> unsigned int a:18;
>> unsigned int b:2;
>> unsigned int c:12;
>> };
>>
>> struct test_foo x;
>> unsigned int foo()
>> {
>>     unsigned int a=x.b;
>>     x.b=2;
>>     return a;
>> }
>>
>> the command: mipsel-linux-gcc -mips32r2 -O2 -c -Wall foo.c -o foo.o
>>
>> The corresponding disassembly code:
>> foo.o:     file format elf32-tradlittlemips
>> Disassembly of section .text:
>> 00000000 <foo>:
>>    0:   3c1c0000    lui gp,0x0
>>    4:   279c0000    addiu   gp,gp,0
>>    8:   0399e021    addu    gp,gp,t9
>>    c:   8f850000    lw  a1,0(gp)
>>   10:   3c03fff3    lui v1,0xfff3
>>   14:   3463ffff    ori v1,v1,0xffff
>>   18:   8ca20000    lw  v0,0(a1)
>>   1c:   3c040008    lui a0,0x8
>>   20:   00431824    and v1,v0,v1
>>   24:   00641825    or  v1,v1,a0
>>   28:   7c420c80    ext v0,v0,0x12,0x2
>>   2c:   03e00008    jr  ra
>>   30:   aca30000    sw  v1,0(a1)
>> The statement x.b=2 can be simply translated to lb and ins instructions( ins
>> is in mips32r2).
>>
>> I wonder how ins instrution can be produced.
>> More specifically, how can gcc generates the insv pattern in RTL?
>> Is it related to the coding style -- using bit filed or logical
>> operations(shift, and ...)?
>> Thanks.
>> Qifei
>>
>>
> 
> 
> 

Re: ins instruction is not produced in the assembly code (mips32r2)

[fanqifei]

Is there anyone can help?
I am curious about how the insv pattern can be used in the compiling process.
Otherwise, I have to write inline assembly code.
Thanks very much!

2009/12/16 fanqifei <fanqifei@gmail.com>:
> Hello,
> I am tring to compile a small c file using gcc4.1.2.
> The source code:
> struct test_foo {
> unsigned int a:18;
> unsigned int b:2;
> unsigned int c:12;
> };
>
> struct test_foo x;
> unsigned int foo()
> {
>     unsigned int a=x.b;
>     x.b=2;
>     return a;
> }
>
> the command: mipsel-linux-gcc -mips32r2 -O2 -c -Wall foo.c -o foo.o
>
> The corresponding disassembly code:
> foo.o:     file format elf32-tradlittlemips
> Disassembly of section .text:
> 00000000 <foo>:
>    0:   3c1c0000    lui gp,0x0
>    4:   279c0000    addiu   gp,gp,0
>    8:   0399e021    addu    gp,gp,t9
>    c:   8f850000    lw  a1,0(gp)
>   10:   3c03fff3    lui v1,0xfff3
>   14:   3463ffff    ori v1,v1,0xffff
>   18:   8ca20000    lw  v0,0(a1)
>   1c:   3c040008    lui a0,0x8
>   20:   00431824    and v1,v0,v1
>   24:   00641825    or  v1,v1,a0
>   28:   7c420c80    ext v0,v0,0x12,0x2
>   2c:   03e00008    jr  ra
>   30:   aca30000    sw  v1,0(a1)
> The statement x.b=2 can be simply translated to lb and ins instructions( ins
> is in mips32r2).
>
> I wonder how ins instrution can be produced.
> More specifically, how can gcc generates the insv pattern in RTL?
> Is it related to the coding style -- using bit filed or logical
> operations(shift, and ...)?
> Thanks.
> Qifei
>
>



-- 
        Qifei Fan