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Date: Fri, 18 Dec 2009 10:57:00 -0000
Message-ID: <f94afa700912180250k5d33110y222a2faf5cabd98e@mail.gmail.com>
Subject: Re: ins instruction is not produced in the assembly code (mips32r2)
From: fanqifei <fanqifei@gmail.com>
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Is there anyone can help?
I am curious about how the insv pattern can be used in the compiling proces=
s.
Otherwise, I have to write inline assembly code.
Thanks very much!

2009/12/16 fanqifei <fanqifei@gmail.com>:
> Hello,
> I am tring to compile a small c file using gcc4.1.2.
> The source code:
> struct test_foo {
> unsigned int a:18;
> unsigned int b:2;
> unsigned int c:12;
> };
>
> struct test_foo x;
> unsigned int foo()
> {
> =A0=A0=A0 unsigned int a=3Dx.b;
> =A0=A0=A0 x.b=3D2;
> =A0=A0=A0 return a;
> }
>
> the command: mipsel-linux-gcc -mips32r2 -O2 -c -Wall foo.c -o foo.o
>
> The corresponding disassembly code:
> foo.o:=A0=A0=A0=A0 file format elf32-tradlittlemips
> Disassembly of section .text:
> 00000000 <foo>:
> =A0=A0 0:=A0=A0 3c1c0000=A0=A0=A0 lui gp,0x0
> =A0=A0 4:=A0=A0 279c0000=A0=A0=A0 addiu=A0=A0 gp,gp,0
> =A0=A0 8:=A0=A0 0399e021=A0=A0=A0 addu=A0=A0=A0 gp,gp,t9
> =A0=A0 c:=A0=A0 8f850000=A0=A0=A0 lw=A0 a1,0(gp)
> =A0 10:=A0=A0 3c03fff3=A0=A0=A0 lui v1,0xfff3
> =A0 14:=A0=A0 3463ffff=A0=A0=A0 ori v1,v1,0xffff
> =A0 18:=A0=A0 8ca20000=A0=A0=A0 lw=A0 v0,0(a1)
> =A0 1c:=A0=A0 3c040008=A0=A0=A0 lui a0,0x8
> =A0 20:=A0=A0 00431824=A0=A0=A0 and v1,v0,v1
> =A0 24:=A0=A0 00641825=A0=A0=A0 or=A0 v1,v1,a0
> =A0 28:=A0=A0 7c420c80=A0=A0=A0 ext v0,v0,0x12,0x2
> =A0 2c:=A0=A0 03e00008=A0=A0=A0 jr=A0 ra
> =A0 30:=A0=A0 aca30000=A0=A0=A0 sw=A0 v1,0(a1)
> The statement x.b=3D2 can be simply translated to lb and ins instructions=
( ins
> is in mips32r2).
>
> I wonder how ins instrution can be produced.
> More specifically,=A0how can=A0gcc generates the insv pattern in RTL?
> Is it related to the coding style -- using bit filed or logical
> operations(shift, and ...)?
> Thanks.
> Qifei
>
>



--=20
        Qifei Fan