Help required for c to VCG GDL flow chart

Help required for c to VCG GDL flow chart

[Sharad Pratap]

 I am developing a c2vcg program which takes C Program text

  and produces GDL of flow chart usable for VCG (Visual

  Compiler Graphics,) This program can now work for normal

  ANSI C some time fails on some special. In this I simply written

  a Bison Grammer file generating GDL according to Sources.

  I want for my program to  work  for  GNU C, But I am not getting

  any starting point here. I didn't understand whether GEM could help

  for this.

  Please tell whether it is possible to integrate this program/module

  in GCC or it should be totally seperate from it. work as independent

  program. If it is good to integrate in GCC so please tell how should

  I start it in GCC me a starting point.

  This is my gram.y view for one construct.

 iteration_statement:
  FOR '(' ';' ';' ')' statement
         {
         crtnode (++node, strdup ("for (;;)"), "rhomb", NULL);
         crtedge (EDGE, node, $6->flows->entry, NULL, NULL);
         crtoutsedge (BENTNEAR/*EDGE*/, &($6->flows->outs), node, FORWARD);
         crtoutsedge (BACK, &($6->flows->cnt), node, FORWARD);

         $$ = $6;
         $$->flows->entry = node;
         $$->flows->sttyp = LOOP;
         push_link (&($$->flows->outs), crtnodtyp (node, LOOP));
         push_list (&($$->flows->outs), $6->flows->brk);
         $$->flows->brk = NULL;
         }

  Regard
       Sharad

adding movz to machine description

[Petar Bajic]

I need to add conditional move instructions to gcc dlx port.
I found implemented pattern 'movmodecc' for conditional move instruction 
that look like this:
if (condition)
    a = b;
else
   a = c;

but my "movz" look like this

if (c == 0)
    a = b;

or asm: movz r1, r2, r3  ;; ((if r3 == 0, move r2 to r1))

there is no 'else'  branch.

In md file it's easy to describe first case:

(define_insn "movsicc_internal"
  [(set (match_operand:SI 0 "register_operand" "=d,d")
  (if_then_else:SI
  (match_operator 1 "comparison_operator" [(match_operand:SI 4 
"register_operand" "=d,d") (const_int 0)])
  (match_operand:SI 2 "register_operand" "=d,d")
  (match_operand:SI 3 "register_operand" "=d,d")))]

"movc\\t%0, %2, %3, %1" ;;theoretic conditional move with else branch
[(set_attr "mode" "SI")]

But I can't seem to describe what I need: conditional move without else 
branch.
Any help is appreciated. Im new here.

Petar 

Re: adding movz to machine description

[Ian Lance Taylor]

"Petar Bajic" <petar.bajic@micronasnit.com> writes:

> I need to add conditional move instructions to gcc dlx port.
> I found implemented pattern 'movmodecc' for conditional move
> instruction that look like this:
> if (condition)
>     a = b;
> else
>    a = c;
> 
> but my "movz" look like this
> 
> if (c == 0)
>     a = b;
> 
> or asm: movz r1, r2, r3  ;; ((if r3 == 0, move r2 to r1))
> 
> there is no 'else'  branch.
> 
> In md file it's easy to describe first case:
> 
> (define_insn "movsicc_internal"
>   [(set (match_operand:SI 0 "register_operand" "=d,d")
>   (if_then_else:SI
>   (match_operator 1 "comparison_operator" [(match_operand:SI 4
> "register_operand" "=d,d") (const_int 0)])
>   (match_operand:SI 2 "register_operand" "=d,d")
>   (match_operand:SI 3 "register_operand" "=d,d")))]
> 
> "movc\\t%0, %2, %3, %1" ;;theoretic conditional move with else branch
> [(set_attr "mode" "SI")]
> 
> But I can't seem to describe what I need: conditional move without
> else branch.
> Any help is appreciated. Im new here.

Write it as a define_expand which generates, more or less,
    (set a c)
    (set a (if_then_else (eq b 0) d (match_dup a)))

Ian

Re: adding movz to machine description

[Petar Bajic]

----- Original Message ----- 
From: "Ian Lance Taylor" <iant@google.com>
To: "Petar Bajic" <petar.bajic@micronasnit.com>
Cc: <gcc-help@gcc.gnu.org>
Sent: Friday, July 07, 2006 7:39 PM
Subject: Re: adding movz to machine description


> "Petar Bajic" <petar.bajic@micronasnit.com> writes:
>
>> I need to add conditional move instructions without else branch to gcc 
>> dlx port.
>> Any help is appreciated. Im new here.
>
>
> Write it as a define_expand which generates, more or less,
>    (set a c)
>    (set a (if_then_else (eq b 0) d (match_dup a)))
>
> Ian
>


If I write define_expand like this :

(define_expand "movsicc_movz"
  [(set (match_operand:SI 0 "register_operand" "=d,d")
  (if_then_else (eq (match_operand:SI 2 "register_operand" "=d,d") 
(const_int 0))
     (match_operand:SI 1 "register_operand" "=d,d") (match_dup 0)))]
  ""
  "{dlx_emit_cond_move(operands[0], operands[1], operands[2]); DONE;}" )


it never gets used/generated 

Re: adding movz to machine description

[Ian Lance Taylor]

"Petar Bajic" <petar.bajic@micronasnit.com> writes:

> If I write define_expand like this :
> 
> (define_expand "movsicc_movz"
>   [(set (match_operand:SI 0 "register_operand" "=d,d")
>   (if_then_else (eq (match_operand:SI 2 "register_operand" "=d,d")
> (const_int 0))
>      (match_operand:SI 1 "register_operand" "=d,d") (match_dup 0)))]
>   ""
>   "{dlx_emit_cond_move(operands[0], operands[1], operands[2]); DONE;}" )
> 
> 
> it never gets used/generated

In order for a define_expand to be used by the machine independent
code, it must have a standard name, as listed here:
    http://gcc.gnu.org/onlinedocs/gccint/Standard-Names.html

In this case you should call it simply "movsicc", not "movsicc_movz".

Ian

Re: adding movz to machine description

[Petar Bajic]

----- Original Message ----- 
From: "Ian Lance Taylor" <iant@google.com>
To: "Petar Bajic" <petar.bajic@micronasnit.com>
Cc: <gcc-help@gcc.gnu.org>
Sent: Thursday, July 13, 2006 9:51 AM
Subject: Re: adding movz to machine description


> "Petar Bajic" <petar.bajic@micronasnit.com> writes:
>
>> If I write define_expand like this :
>>
>> (define_expand "movsicc_movz"
>>   [(set (match_operand:SI 0 "register_operand" "=d,d")
>>   (if_then_else (eq (match_operand:SI 2 "register_operand" "=d,d")
>> (const_int 0))
>>      (match_operand:SI 1 "register_operand" "=d,d") (match_dup 0)))]
>>   ""
>>   "{dlx_emit_cond_move(operands[0], operands[1], operands[2]); DONE;}" )
>>
>>
>> it never gets used/generated
>
> In order for a define_expand to be used by the machine independent
> code, it must have a standard name, as listed here:
>    http://gcc.gnu.org/onlinedocs/gccint/Standard-Names.html
>
> In this case you should call it simply "movsicc", not "movsicc_movz".
>
> Ian
>

define_expand is used but instruction is not generated

(define_expand "movsicc"
    [(set (match_operand:SI 0 "register_operand" "=d,d")
     (if_then_else:SI (eq:SI (match_operand:SI 2 "register_operand" "=d,d") 
(const_int 0))
        (match_operand:SI 1 "register_operand" "=d,d")
 (match_dup 0)))]
  ""
  "
{
  dlx_emit_cond_move(operands[0], operands[1], operands[2]);
  DONE;
}")

In function dlx_emitcond_move I try to emit my instruction "movsicc_movz".
Comment is printed out, but instruction is not generated.
dlx_emit_cond_move (rtx dest, rtx src1, rtx test_rtx)

{

printf("dlx_emit_cond_move called");



emit_insn(gen_movsicc_movz(dest, src1, test_rtx));

return TRUE;

}

and finally instruction is defined like this:

(define_insn "movsicc_movz"
  [(set (match_operand:SI 0 "register_operand" "=d,d")
   (if_then_else:SI (match_operand:SI 1 "comparison_operator" "")
    (match_operand:SI 2 "register_operand" "=d,d")
    (match_dup 0)))]
  ""
  "movz\\t%0,%2,%1"
  [(set_attr "type" "condmove")
   (set_attr "mode" "SI")])

I also have regular patern movsicc_insn wich is always used, and if I skip 
it's definition, I can't build compiler (errpor "gen_movsicc_move not 
defined")

(define_insn "movsicc_internal"
  [(set (match_operand:SI 0 "register_operand" "=j,j")
  (if_then_else:SI
  (match_operator 1 "comparison_operator" [(match_operand:SI 4 
"register_operand" "=k,k") (const_int 0)])
  (match_operand:SI 2 "register_operand" "=d,d")
  (match_operand:SI 3 "register_operand" "=d,d")))]
  ""
  "movz\\t%0,%2,%4\\n\\tmovn\\t%0,%3,%4"
  [(set_attr "type" "condmove")
   (set_attr "mode" "SI")])

What do I have to do to make compiler use movsicc_movz when appropriate?



Petar

Re: adding movz to machine description

[Ian Lance Taylor]

"Petar Bajic" <petar.bajic@micronasnit.com> writes:

> define_expand is used but instruction is not generated

...

> What do I have to do to make compiler use movsicc_movz when appropriate?

What do you mean when you say that the instruction is not generated?
Your code looks OK.  Look at the .expand debugging dump (use -da to
generate all the RTL debugging dump files); do you see the instruction
there?  If so, trace it forward to see what happens to it.

Ian

Re: adding movz to machine description

[Rask Ingemann Lambertsen]

On Fri, Jul 07, 2006 at 04:25:08PM +0200, Petar Bajic wrote:
> but my "movz" look like this
> 
> if (c == 0)
>    a = b;
> 
> or asm: movz r1, r2, r3  ;; ((if r3 == 0, move r2 to r1))
> 
> there is no 'else'  branch.

There _is_ an 'else' branch:

if (r3 == 0)
  r1 = r2;
else
  r1 = r1;

With that, the insn definition is easy enough:

(define_insn "*movz"
	[(set (match_operand:SI 0 "register_operand" "=d")
	      (if_then_else (eq (match_operand:SI 1 "register_operand" "d")
				(const_int 0))
			    (match_operand:SI 2 "register_operand" "d")
			    (match_operand:SI 3 "register_operand" "0")))]
	""
	"movz\t%0, %2, %1"
)

This is not all that different from the "*movsicc_noc" pattern in i386.md.
You may want to add a reverse conditional pattern too, i.e. with (ne ...)
instead of (eq ...) and operands 2 and 3 swapped.

As for the expander, I don't know enough of our target machine to write one,
and I'm not sure you need one. Passes such as combine, ce1, ce2 and ce3 may
create "*movz".

Having read the rest of the thread, I suggest you reread the documentation
about define_expand, in particular the description of the DONE and FAIL
macros for the preparation statements and how they affect the generation of
the RTL template.

-- 
Rask Ingemann Lambertsen

Re: adding movz to machine description

[Petar Bajic]

I finally made it work, these rules will successfully emit both movz and 
movn instructions.
Thank you for help.

(define_insn "movsicc_movz"
  [(set (match_operand:SI 0 "register_operand" "=d")
   (if_then_else:SI (eq (match_operand:SI 1 "register_operand" 
"d")(const_int 0))
    (match_operand:SI 2 "register_operand" "d")
    (match_dup 0) ))]
  ""
  "movz\\t%0,%2,%1"
  [(set_attr "type" "condmove")
   (set_attr "mode" "SI")])

(define_insn "movsicc_movn"
  [(set (match_operand:SI 0 "register_operand" "=d")
   (if_then_else:SI (ne (match_operand:SI 1 "register_operand" 
"d")(const_int 0))
    (match_operand:SI 2 "register_operand" "d")
    (match_dup 0) ))]
  ""
  "movn\\t%0,%2,%1"
  [(set_attr "type" "condmove")
   (set_attr "mode" "SI")])



(define_expand "movsicc"
    [(set (match_operand:SI 0 "register_operand" "=d")
     (if_then_else:SI
       (match_operator 1 "comparison_operator" [(match_operand:SI 4 
"register_operand" "d") (const_int 0)])
        (match_operand:SI 2 "register_operand" "d")
 (match_operand:SI 3 "register_operand" "d") ))]
  ""
  "
{
if (operands[2] != operands[0])
{
 emit_insn (gen_movsi (operands[0], operands[3]));
 if (GET_CODE(operands[1]) == EQ)
 {
    dlx_emit_cond_move_z(operands[0], operands[2], operands[3]);
    DONE;
   }
   else if (GET_CODE(operands[1]) == NE)
   {
    dlx_emit_cond_move_n(operands[0], operands[2], operands[3]);
    DONE;
   }
   else
    FAIL;
}
else
{
 if (GET_CODE(operands[1]) == NE)
 {
    dlx_emit_cond_move_z(operands[0], operands[3], operands[3]);
    DONE;
   }
   else if (GET_CODE(operands[1]) == EQ)
   {
    dlx_emit_cond_move_n(operands[0], operands[3], operands[3]);
    DONE;
   }
   else
    FAIL;
}
}")


(define_insn "movsicc_internal"
  [(set (match_operand:SI 0 "register_operand" "=j,j,j,j,j")
  (if_then_else:SI
  (match_operator 1 "comparison_operator" [(match_operand:SI 4 
"register_operand" "k,k,k,k,k") (const_int 0)])
  (match_operand:SI 2 "register_operand" "d,i,d,I,d")
  (match_operand:SI 3 "register_operand" "d,d,i,d,I")))]
  "(GET_CODE(operands[1]) == EQ)"
  "movz\\t%0,%2,%4\\n\\tmovn\\t%0,%3,%4"
  [(set_attr "type" "condmove")
   (set_attr "length" "2")
   (set_attr "mode" "SI")])


And in dlx.c functions dlx_emit_cond_move_n and dlx_emit_cond_move_z look 
like this:

int

dlx_emit_cond_move_z (rtx dest, rtx src1, rtx src2)

{

dlx_compare_op0 = force_reg(SImode, dlx_compare_op0);

emit_insn(gen_movsicc_movz(dest, dlx_compare_op0, src1));

}

int

dlx_emit_cond_move_n (rtx dest, rtx src1, rtx src2)

{

dlx_compare_op0 = force_reg(SImode, dlx_compare_op0);

emit_insn(gen_movsicc_movn(dest, dlx_compare_op0, src1));

}

best regards,
Petar Bajic

----- Original Message ----- 
From: "Ian Lance Taylor" <iant@google.com>
To: "Petar Bajic" <petar.bajic@micronasnit.com>
Cc: <gcc-help@gcc.gnu.org>
Sent: Tuesday, July 25, 2006 3:39 PM
Subject: Re: adding movz to machine description


> "Petar Bajic" <petar.bajic@micronasnit.com> writes:
>
>> > It may be correct for the pattern to not be matched with expand.  It's
>> > OK if the if-conversion pass picks it up, which seems to be what is
>> > happening for you.
>> >
>> > If the generated code you are getting is wrong, then problem is likely
>> > in the define_insn patterns somewhere.  They don't correct represent
>> > what the instruction does, or they don't correctly implement it.
>> >
>> > Ian
>>
>> After some modifications, I managed to make gcc use my define_expand -
>> I see it in debug.11.ce1 and following files, but then it disapears in
>> debug.17.combine, and in the end it does not appear in asm code. How
>> to find out what kills it? :)
>
> That means that the combine pass has replaced it with something else
> which is equivalent which the combine pass thought would be cheaper.
> Look at the generated RTL to see what it turned into.  If the
> resulting code is less efficient to run, then you need to adjust your
> costs (the TARGET_RTX_COSTS hook).
>
> Ian 

Re: adding movz to machine description

[Ian Lance Taylor]

"Petar Bajic" <petar.bajic@micronasnit.com> writes:

> How come else branch got hanging like that?

It's really impossible to say without more information.  The RTL
transformation you showed is clearly correct.

I strongly encourage you to look closely at the RTL and figure out how
it is being generated and how it is being changed.  This is not
impossible.  When you run into trouble, ask very specific questions
and provide all the information required to understand them.  General
questions like the above are difficult and time-consuming to answer.
Remember that we are all volunteers.  Thanks.

Ian

Re: adding movz to machine description

[Petar Bajic]

> That means that the combine pass has replaced it with something else
> which is equivalent which the combine pass thought would be cheaper.
> Look at the generated RTL to see what it turned into.  If the
> resulting code is less efficient to run, then you need to adjust your
> costs (the TARGET_RTX_COSTS hook).
>
> Ian

Finally, my instruction is generated.
There is off course one problem, when If Then Else is replaced with my 
pattern,

(define_expand "movsicc"
    [(set (match_operand:SI 0 "register_operand" "=d,d")
     (if_then_else:SI
       ;;(match_operator 1 "comparison_operator" [(match_operand:SI 3 
"register_operand" "=d,d") (const_int 0)])
       (eq:SI (match_operand:SI 1 "register_operand" "=d,d") (const_int 0))
        (match_operand:SI 2 "register_operand" "=d,d")
 (match_dup:SI 0)))]
  ""
  "
{
  dlx_compare_op0 = force_reg(SImode, dlx_compare_op0);
  emit_insn(gen_movsicc_movz(operands[0], , dlx_compare_op0, operands[2], , 
operands[0], ));
  DONE;
}")

previous initialization of destination register is lost.
for example,
d = 7;
if (a > b)
 d = in1;
return d;

obviously, d should remain 7 if condition is not true.

pattern is replaced with


(insn 50 18 51 0 (set (reg:SI 47)
        (const_int 7 [0x7])) 40 {movsi_general} (nil)         ////this use 
to be d = 7;
    (nil))

(insn 51 50 33 0 (set (reg/v:SI 37 [ d ])
        (if_then_else:SI (reg:SI 45)
            (reg/v:SI 42 [ h ])
            (reg/v:SI 37 [ d ]))) 0 {movsicc_movz} (nil)       //// now d is 
not initialised??
    (nil))


and in next step, insn 50 is removed!
How come else branch got hanging like that? 

Re: adding movz to machine description

[Ian Lance Taylor]

"Petar Bajic" <petar.bajic@micronasnit.com> writes:

> > It may be correct for the pattern to not be matched with expand.  It's
> > OK if the if-conversion pass picks it up, which seems to be what is
> > happening for you.
> >
> > If the generated code you are getting is wrong, then problem is likely
> > in the define_insn patterns somewhere.  They don't correct represent
> > what the instruction does, or they don't correctly implement it.
> >
> > Ian
> 
> After some modifications, I managed to make gcc use my define_expand -
> I see it in debug.11.ce1 and following files, but then it disapears in
> debug.17.combine, and in the end it does not appear in asm code. How
> to find out what kills it? :)

That means that the combine pass has replaced it with something else
which is equivalent which the combine pass thought would be cheaper.
Look at the generated RTL to see what it turned into.  If the
resulting code is less efficient to run, then you need to adjust your
costs (the TARGET_RTX_COSTS hook).

Ian

Re: adding movz to machine description

[Petar Bajic]

> It may be correct for the pattern to not be matched with expand.  It's
> OK if the if-conversion pass picks it up, which seems to be what is
> happening for you.
>
> If the generated code you are getting is wrong, then problem is likely
> in the define_insn patterns somewhere.  They don't correct represent
> what the instruction does, or they don't correctly implement it.
>
> Ian

After some modifications, I managed to make gcc use my define_expand - I see 
it in debug.11.ce1 and following files, but then it disapears in 
debug.17.combine, and in the end it does not appear in asm code. How to find 
out what kills it? :) 

Re: adding movz to machine description

[Ian Lance Taylor]

"Petar Bajic" <petar.bajic@micronasnit.com> writes:

> > It's not generated, like it's not in the asm code. Instead, movsi_insn is
> > used and bad asm code is generated.
> >
> > for c code :
> > if (in1 == 0)
> >    out = in2;
> > return out;
> >
> > I expect asm to look like this
> > lw r2,4(r30)  ; in2
> > lw r16,(r30)  ; in1
> > movz r1, r2, r16
> >
> > instead, code looks like this
> >
> > lw r2,4(r30)
> > lw r16,(r30)
> > movz r1,r2,r16
> > movn r1,r16,r16
> >
> > expand debug file is in attach, I don't see that movsicc_expand is used...
> > (although this is my first time to look at expand files)
> > movsicc_insn first appears in short.c.11.ce1
> >
> > can you see why pattern is not matched with expand?

Looking back at your earlier message, you had this:

(define_expand "movsicc"
  [(set (match_operand:SI 0 "register_operand" "=d,d")
     (if_then_else:SI (eq:SI (match_operand:SI 2 "register_operand" "=d,d") (const_int 0))
       (match_operand:SI 1 "register_operand" "=d,d")
       (match_dup 0)))]

The match_dup suggests that the first and last operands must be the
same, in which case "movz r1,r2,r16" is not permitted.

It may be correct for the pattern to not be matched with expand.  It's
OK if the if-conversion pass picks it up, which seems to be what is
happening for you.

If the generated code you are getting is wrong, then problem is likely
in the define_insn patterns somewhere.  They don't correct represent
what the instruction does, or they don't correctly implement it.

Ian

adding movz to machine description

[Petar Bajic]

[-- Attachment #1: Type: text/plain, Size: 993 bytes --]

> ----- Original Message ----- 
> From: "Ian Lance Taylor" <iant@google.com>
>
>> What do you mean when you say that the instruction is not generated?
>> Your code looks OK.  Look at the .expand debugging dump (use -da to
>> generate all the RTL debugging dump files); do you see the instruction
>> there?  If so, trace it forward to see what happens to it.
>>
>> Ian
>>
>
> It's not generated, like it's not in the asm code. Instead, movsi_insn is
> used and bad asm code is generated.
>
> for c code :
> if (in1 == 0)
>    out = in2;
> return out;
>
> I expect asm to look like this
> lw r2,4(r30)  ; in2
> lw r16,(r30)  ; in1
> movz r1, r2, r16
>
> instead, code looks like this
>
> lw r2,4(r30)
> lw r16,(r30)
> movz r1,r2,r16
> movn r1,r16,r16
>
> expand debug file is in attach, I don't see that movsicc_expand is used...
> (although this is my first time to look at expand files)
> movsicc_insn first appears in short.c.11.ce1
>
> can you see why pattern is not matched with expand?
> 

[-- Attachment #2: short.c.00.expand --]
[-- Type: application/octet-stream, Size: 3936 bytes --]


;; Function main (main)


;; Generating RTL for tree basic block 0

;; Generating RTL for tree basic block 1

;; Generating RTL for tree basic block 2

;; Generating RTL for tree basic block 3


;;
;; Full RTL generated for this function:
;;
(note 2 0 11 NOTE_INSN_DELETED)

;; Start of basic block 0, registers live: (nil)
(note 11 2 6 0 [bb 0] NOTE_INSN_BASIC_BLOCK)

(insn 6 11 7 0 (set (reg/v:SI 39 [ k ])
        (mem/i:SI (reg/f:SI 32 virtual-incoming-args) [2 k+0 S4 A32])) -1 (nil)
    (expr_list:REG_EQUIV (mem/i:SI (reg/f:SI 32 virtual-incoming-args) [2 k+0 S4 A32])
        (nil)))

(insn 7 6 8 0 (set (reg/v:SI 40 [ m ])
        (mem/i:SI (plus:SI (reg/f:SI 32 virtual-incoming-args)
                (const_int 4 [0x4])) [2 m+0 S4 A32])) -1 (nil)
    (expr_list:REG_EQUIV (mem/i:SI (plus:SI (reg/f:SI 32 virtual-incoming-args)
                (const_int 4 [0x4])) [2 m+0 S4 A32])
        (nil)))

(note 8 7 9 0 NOTE_INSN_FUNCTION_BEG)

(note 9 8 10 0 NOTE_INSN_DELETED)

(call_insn 10 9 12 0 (parallel [
            (call (mem:QI (symbol_ref:SI ("__main") [flags 0x41]) [0 S1 A8])
                (const_int 0 [0x0]))
            (clobber (reg:SI 31 r31))
        ]) -1 (nil)
    (expr_list:REG_EH_REGION (const_int 0 [0x0])
        (nil))
    (nil))
;; End of basic block 0, registers live:
 (nil)

;; Start of basic block 1, registers live: (nil)
(note 12 10 14 1 [bb 1] NOTE_INSN_BASIC_BLOCK)

(insn 14 12 15 1 (set:SI (reg:SI 41)
        (ne:SI (reg/v:SI 39 [ k ])
            (const_int 0 [0x0]))) -1 (nil)
    (nil))

(jump_insn 15 14 16 1 (set (pc)
        (if_then_else (ne:SI (const_int 0 [0x0])
                (reg:SI 41))
            (label_ref 21)
            (pc))) -1 (nil)
    (expr_list:REG_BR_PROB (const_int 3300 [0xce4])
        (nil)))
;; End of basic block 1, registers live:
 (nil)

;; Start of basic block 2, registers live: (nil)
(code_label 16 15 17 2 3 "" [0 uses])

(note 17 16 18 2 [bb 2] NOTE_INSN_BASIC_BLOCK)

(insn 18 17 19 2 (set (reg/v:SI 37 [ f ])
        (reg/v:SI 40 [ m ])) -1 (nil)
    (nil))

(jump_insn 19 18 20 2 (set (pc)
        (label_ref 24)) -1 (nil)
    (nil))
;; End of basic block 2, registers live:
 (nil)

(barrier 20 19 21)

;; Start of basic block 3, registers live: (nil)
(code_label 21 20 22 3 2 "" [1 uses])

(note 22 21 23 3 [bb 3] NOTE_INSN_BASIC_BLOCK)

(insn 23 22 24 3 (set (reg/v:SI 37 [ f ])
        (const_int 0 [0x0])) -1 (nil)
    (nil))
;; End of basic block 3, registers live:
 (nil)

;; Start of basic block 4, registers live: (nil)
(code_label 24 23 25 4 4 "" [1 uses])

(note 25 24 26 4 [bb 4] NOTE_INSN_BASIC_BLOCK)

(insn 26 25 27 4 (set (reg:SI 38 [ <result> ])
        (reg/v:SI 37 [ f ])) -1 (nil)
    (nil))

(jump_insn 27 26 28 4 (set (pc)
        (label_ref 31)) -1 (nil)
    (nil))
;; End of basic block 4, registers live:
 (nil)

(barrier 28 27 29)

(note 29 28 39 NOTE_INSN_FUNCTION_END)

;; Start of basic block 5, registers live: (nil)
(note 39 29 33 5 [bb 5] NOTE_INSN_BASIC_BLOCK)

(insn 33 39 34 5 (clobber (reg/i:SI 1 r1)) -1 (nil)
    (nil))

(insn 34 33 35 5 (clobber (reg:SI 38 [ <result> ])) -1 (nil)
    (nil))

(jump_insn 35 34 36 5 (set (pc)
        (label_ref 37)) -1 (nil)
    (nil))
;; End of basic block 5, registers live:
 (nil)

(barrier 36 35 31)

;; Start of basic block 6, registers live: (nil)
(code_label 31 36 40 6 1 "" [1 uses])

(note 40 31 32 6 [bb 6] NOTE_INSN_BASIC_BLOCK)

(insn 32 40 37 6 (set (reg/i:SI 1 r1)
        (reg:SI 38 [ <result> ])) -1 (nil)
    (nil))
;; End of basic block 6, registers live:
 (nil)

;; Start of basic block 7, registers live: (nil)
(code_label 37 32 41 7 5 "" [1 uses])

(note 41 37 38 7 [bb 7] NOTE_INSN_BASIC_BLOCK)

(insn 38 41 0 7 (use (reg/i:SI 1 r1)) -1 (nil)
    (nil))
;; End of basic block 7, registers live:
 (nil)


[-- Attachment #3: short.c.11.ce1 --]
[-- Type: application/octet-stream, Size: 3057 bytes --]


;; Function main

43 registers.

Register 37 used 2 times across 0 insns; set 2 times; user var; dies in 0 places.

Register 39 used 1 times across 0 insns; set 1 time; user var; dies in 0 places.

Register 40 used 1 times across 0 insns; set 1 time; user var; dies in 0 places.

Register 41 used 1 times across 0 insns; set 1 time; dies in 0 places.

4 basic blocks, 6 edges.

Basic block 0 prev -1, next 1, loop_depth 0, count 0, freq 10000, maybe hot.
Predecessors:  ENTRY [100.0%]  (fallthru)
Successors:  2 [33.0%]  1 [67.0%]  (fallthru)

Basic block 1 prev 0, next 2, loop_depth 0, count 0, freq 6700, maybe hot.
Predecessors:  0 [67.0%]  (fallthru)
Successors:  3 [100.0%] 

Basic block 2 prev 1, next 3, loop_depth 0, count 0, freq 3300, maybe hot.
Predecessors:  0 [33.0%] 
Successors:  3 [100.0%]  (fallthru)

Basic block 3 prev 2, next -2, loop_depth 0, count 0, freq 10000, maybe hot.
Predecessors:  1 [100.0%]  2 [100.0%]  (fallthru)
Successors:  EXIT [100.0%]  (fallthru)



try_optimize_cfg iteration 1


IF-THEN-ELSE block found, pass 1, start block 0 [insn 11], then 1 [17], else 2 [21], join 3 [24]
Conversion succeeded on pass 1.

1 possible IF blocks searched.
1 IF blocks converted.
3 true changes made.




try_optimize_cfg iteration 1

(note 2 0 11 NOTE_INSN_DELETED)

;; Start of basic block 0, registers live: (nil)
(note 11 2 6 0 [bb 0] NOTE_INSN_BASIC_BLOCK)

(insn 6 11 7 0 (set (reg/v:SI 39 [ k ])
        (mem/i:SI (reg/f:SI 30 r30) [2 k+0 S4 A32])) 40 {movsi_general} (nil)
    (expr_list:REG_EQUIV (mem/i:SI (reg/f:SI 30 r30) [2 k+0 S4 A32])
        (nil)))

(insn 7 6 8 0 (set (reg/v:SI 40 [ m ])
        (mem/i:SI (plus:SI (reg/f:SI 30 r30)
                (const_int 4 [0x4])) [2 m+0 S4 A32])) 40 {movsi_general} (nil)
    (expr_list:REG_EQUIV (mem/i:SI (plus:SI (reg/f:SI 30 r30)
                (const_int 4 [0x4])) [2 m+0 S4 A32])
        (nil)))

(note 8 7 10 0 NOTE_INSN_FUNCTION_BEG)

(call_insn 10 8 14 0 (parallel [
            (call (mem:QI (symbol_ref:SI ("__main") [flags 0x41]) [0 S1 A8])
                (const_int 0 [0x0]))
            (clobber (reg:SI 31 r31))
        ]) -1 (nil)
    (expr_list:REG_EH_REGION (const_int 0 [0x0])
        (nil))
    (nil))

(insn 14 10 46 0 (set:SI (reg:SI 41)
        (ne:SI (reg/v:SI 39 [ k ])
            (const_int 0 [0x0]))) 61 {set_internal} (nil)
    (nil))

(insn 46 14 47 0 (set (reg:SI 43)
        (const_int 0 [0x0])) 40 {movsi_general} (nil)
    (nil))

(insn 47 46 29 0 (set (reg/v:SI 37 [ f ])
        (if_then_else:SI (eq (reg:SI 41)
                (const_int 0 [0x0]))
            (reg/v:SI 40 [ m ])
            (reg/v:SI 37 [ f ]))) 1 {movsicc_internal} (nil)
    (nil))

(note 29 47 32 0 NOTE_INSN_FUNCTION_END)

(insn 32 29 38 0 (set (reg/i:SI 1 r1 [ <result> ])
        (reg/v:SI 37 [ f ])) 40 {movsi_general} (nil)
    (nil))

(insn 38 32 0 0 (use (reg/i:SI 1 r1 [ <result> ])) -1 (nil)
    (nil))
;; End of basic block 0, registers live:
 (nil)