Re: Question about RTL for bitwise AND

[Ian Lance Taylor <ian@airs.com>]

"Matt Lee" <reachmatt.lee@gmail.com> writes:

>  I am using powerpc-eabi-gcc (version 3.4.1) and I have a question
> about the RTL that is produced for,
> 
>  test.c
>  int a;
> 
>  if (a & 2) {
>   // Do something
>  } else
>   // Do something else
>  }
> 
> 
>  I see in test.c.01.rtl,
> 
>  (insn 12 11 13 (set (reg:SI 122)
>          (lshiftrt:SI (reg:SI 121)
>              (const_int 1 [0x1]))) -1 (nil)
>      (nil))
> 
>  (insn 13 12 14 (parallel [
>              (set (reg:SI 123)
>                  (and:SI (reg:SI 122)
>                      (const_int 1 [0x1])))
>              (clobber (scratch:CC))
>          ]) -1 (nil)
>      (nil))
> 
> 
>  My question is, why is a logical shift right required? Wouldn't a
> direct bit-wise AND with const_int 2 suffice?

In general this kind of decision is made based on target specific
costs.  See prefer_and_bit_test in dojump.c.

For the PowerPC, you should look at later optimization passes.  It
seems possible that the two instructions above will get combined into
a single rlwinm instruction.  Although I haven't tried it.

>  This is causing problems in my (other) port where I can do only
> single-bit shifts. In the worst case, a & 0x80000000 the final
> assembly contains 31 right shifts. This is a big optimization problem.

Fix your costs to indicate this.

Ian