* [Patch, AArch64] Implement SIMD Absolute Difference Instructions
@ 2013-01-30 5:46 Hurugalawadi, Naveen
2013-02-26 15:23 ` Marcus Shawcroft
2013-02-26 15:29 ` Marcus Shawcroft
0 siblings, 2 replies; 10+ messages in thread
From: Hurugalawadi, Naveen @ 2013-01-30 5:46 UTC (permalink / raw)
To: gcc-patches
[-- Attachment #1: Type: text/plain, Size: 1219 bytes --]
Hi,
Please find attached the patch that implements absolute difference
instructions for aarch64 target.
The patch modifies the testcase vect.c and vect-fp.c to check the
generated instructions and also their functionality.
Please review the patch and let me know if there should be any
modifications?
Build and tested on aarch64-thunder-elf (using Cavium's internal
simulator).
Thanks,
Naveen.H.S
gcc/
2013-01-30 Naveen H.S <Naveen.Hurugalawadi@caviumnetworks.com>
* config/aarch64/aarch64-simd.md (simd_fabd): New Attribute.
(abd<mode>_3): New pattern.
(aba<mode>_3): New pattern.
(fabd<mode>_3): New pattern.
gcc/testsuite/
2013-01-30 Naveen H.S <Naveen.Hurugalawadi@caviumnetworks.com>
* gcc.target/aarch64/vect.c: Test and result vector added
for sabd and saba instructions.
* gcc.target/aarch64/vect-compile.c: Check for sabd and saba
instructions in assembly.
* gcc.target/aarch64/vect.x: Add sabd and saba test functions.
* gcc.target/aarch64/vect-fp.c: Test and result vector added
for fabd instruction.
* gcc.target/aarch64/vect-fp-compile.c: Check for fabd
instruction in assembly.
* gcc.target/aarch64/vect-fp.x: Add fabd test function.
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: simd-abd.patch --]
[-- Type: text/x-patch; name="simd-abd.patch", Size: 6242 bytes --]
--- gcc/config/aarch64/aarch64-simd.md 2013-01-29 11:37:04.705429514 +0530
+++ gcc/config/aarch64/aarch64-simd.md 2013-01-29 16:58:07.401718855 +0530
@@ -44,6 +44,7 @@
; simd_dup duplicate element.
; simd_dupgp duplicate general purpose register.
; simd_ext bitwise extract from pair.
+; simd_fabd floating absolute difference and accumulate.
; simd_fadd floating point add/sub.
; simd_fcmp floating point compare.
; simd_fcvti floating point convert to integer.
@@ -148,6 +149,7 @@
simd_dupgp,\
simd_ext,\
simd_fadd,\
+ simd_fabd,\
simd_fcmp,\
simd_fcvti,\
simd_fcvtl,\
@@ -520,6 +522,40 @@
(set_attr "simd_mode" "<MODE>")]
)
+(define_insn "abd<mode>_3"
+ [(set (match_operand:VDQ_BHSI 0 "register_operand" "=w")
+ (abs:VDQ_BHSI (minus:VDQ_BHSI
+ (match_operand:VDQ_BHSI 1 "register_operand" "w")
+ (match_operand:VDQ_BHSI 2 "register_operand" "w"))))]
+ "TARGET_SIMD"
+ "sabd\t%0.<Vtype>, %1.<Vtype>, %2.<Vtype>"
+ [(set_attr "simd_type" "simd_abd")
+ (set_attr "simd_mode" "<MODE>")]
+)
+
+(define_insn "aba<mode>_3"
+ [(set (match_operand:VDQ_BHSI 0 "register_operand" "=w")
+ (plus:VDQ_BHSI (abs:VDQ_BHSI (minus:VDQ_BHSI
+ (match_operand:VDQ_BHSI 1 "register_operand" "w")
+ (match_operand:VDQ_BHSI 2 "register_operand" "w")))
+ (match_operand:VDQ_BHSI 3 "register_operand" "0")))]
+ "TARGET_SIMD"
+ "saba\t%0.<Vtype>, %1.<Vtype>, %2.<Vtype>"
+ [(set_attr "simd_type" "simd_abd")
+ (set_attr "simd_mode" "<MODE>")]
+)
+
+(define_insn "fabd<mode>_3"
+ [(set (match_operand:VDQF 0 "register_operand" "=w")
+ (abs:VDQF (minus:VDQF
+ (match_operand:VDQF 1 "register_operand" "w")
+ (match_operand:VDQF 2 "register_operand" "w"))))]
+ "TARGET_SIMD"
+ "fabd\t%0.<Vtype>, %1.<Vtype>, %2.<Vtype>"
+ [(set_attr "simd_type" "simd_fabd")
+ (set_attr "simd_mode" "<MODE>")]
+)
+
(define_insn "and<mode>3"
[(set (match_operand:VDQ 0 "register_operand" "=w")
(and:VDQ (match_operand:VDQ 1 "register_operand" "w")
--- gcc/testsuite/gcc.target/aarch64/vect.c 2013-01-24 20:10:09.703833384 +0530
+++ gcc/testsuite/gcc.target/aarch64/vect.c 2013-01-30 10:30:05.089505837 +0530
@@ -55,6 +55,8 @@ int main (void)
int smin_vector[] = {0, -1, -2, -3, -4, -5, -6, -7, -8, -9, -10, -11, -12, -13, -14, -15};
unsigned int umax_vector[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15};
unsigned int umin_vector[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15};
+ int sabd_vector[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
+ int saba_vector[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
int reduce_smax_value = 0;
int reduce_smin_value = -15;
unsigned int reduce_umax_value = 15;
@@ -81,6 +83,8 @@ int main (void)
TEST (smin, s);
TEST (umax, u);
TEST (umin, u);
+ TEST (sabd, s);
+ TEST (saba, s);
TESTV (reduce_smax, s);
TESTV (reduce_smin, s);
TESTV (reduce_umax, u);
--- gcc/testsuite/gcc.target/aarch64/vect-compile.c 2013-01-24 20:10:09.703833384 +0530
+++ gcc/testsuite/gcc.target/aarch64/vect-compile.c 2013-01-29 14:11:16.909568490 +0530
@@ -16,5 +16,7 @@
/* { dg-final { scan-assembler "uminv" } } */
/* { dg-final { scan-assembler "smaxv" } } */
/* { dg-final { scan-assembler "sminv" } } */
+/* { dg-final { scan-assembler "sabd" } } */
+/* { dg-final { scan-assembler "saba" } } */
/* { dg-final { scan-assembler-times "addv" 2} } */
/* { dg-final { scan-assembler-times "addp" 2} } */
--- gcc/testsuite/gcc.target/aarch64/vect-fp.c 2013-01-24 20:10:09.703833384 +0530
+++ gcc/testsuite/gcc.target/aarch64/vect-fp.c 2013-01-30 10:40:23.877491750 +0530
@@ -117,6 +117,16 @@ int main (void)
9.0, 10.0, 11.0, 12.0,
13.0, 14.0, 15.0, 16.0 };
+ F32 fabd_F32_vector[] = { 1.0f, 1.0f, 1.0f, 1.0f,
+ 1.0f, 1.0f, 1.0f, 1.0f,
+ 1.0f, 1.0f, 1.0f, 1.0f,
+ 1.0f, 1.0f, 1.0f, 1.0f };
+
+ F64 fabd_F64_vector[] = { 1.0, 1.0, 1.0, 1.0,
+ 1.0, 1.0, 1.0, 1.0,
+ 1.0, 1.0, 1.0, 1.0,
+ 1.0, 1.0, 1.0, 1.0 };
+
/* Setup input vectors. */
for (i=1; i<=16; i++)
{
@@ -132,6 +142,7 @@ int main (void)
TEST (div, 3);
TEST (neg, 2);
TEST (abs, 2);
+ TEST (fabd, 3);
return 0;
}
--- gcc/testsuite/gcc.target/aarch64/vect-fp-compile.c 2013-01-24 20:10:09.703833384 +0530
+++ gcc/testsuite/gcc.target/aarch64/vect-fp-compile.c 2013-01-29 14:11:16.909568490 +0530
@@ -11,3 +11,4 @@
/* { dg-final { scan-assembler "fdiv\\tv" } } */
/* { dg-final { scan-assembler "fneg\\tv" } } */
/* { dg-final { scan-assembler "fabs\\tv" } } */
+/* { dg-final { scan-assembler "fabd\\tv" } } */
--- gcc/testsuite/gcc.target/aarch64/vect-fp.x 2013-01-24 20:10:09.703833384 +0530
+++ gcc/testsuite/gcc.target/aarch64/vect-fp.x 2013-01-29 14:11:16.909568490 +0530
@@ -7,6 +7,16 @@ typedef double *__restrict__ pRF64;
extern float fabsf (float);
extern double fabs (double);
+#define DEF3a(fname, type, op) \
+ void fname##_##type (pR##type a, \
+ pR##type b, \
+ pR##type c) \
+ { \
+ int i; \
+ for (i=0; i<16; i++) \
+ a[i] = op (b[i] - c[i]); \
+ }
+
#define DEF3(fname, type, op) \
void fname##_##type (pR##type a, \
pR##type b, \
@@ -27,6 +37,10 @@ extern double fabs (double);
}
+#define DEFN3a(fname, op) \
+ DEF3a (fname, F32, op) \
+ DEF3a (fname, F64, op)
+
#define DEFN3(fname, op) \
DEF3 (fname, F32, op) \
DEF3 (fname, F64, op)
@@ -42,3 +56,5 @@ DEFN3 (div, /)
DEFN2 (neg, -)
DEF2 (abs, F32, fabsf)
DEF2 (abs, F64, fabs)
+DEF3a (fabd, F32, fabsf)
+DEF3a (fabd, F64, fabs)
--- gcc/testsuite/gcc.target/aarch64/vect.x 2013-01-24 20:10:09.703833384 +0530
+++ gcc/testsuite/gcc.target/aarch64/vect.x 2013-01-29 18:37:32.321808454 +0530
@@ -138,3 +138,18 @@ long long reduce_add_s64 (pRINT64 a)
return s;
}
+
+void sabd (pRINT a, pRINT b, pRINT c)
+{
+ int i;
+ for (i=0;i<16;i++)
+ c[i] = abs (a[i] - b[i]);
+}
+
+void saba (pRINT a, pRINT b, pRINT c)
+{
+ int i;
+ for (i=0;i<16;i++)
+ c[i] += abs (a[i] - b[i]);
+}
+
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [Patch, AArch64] Implement SIMD Absolute Difference Instructions
2013-01-30 5:46 [Patch, AArch64] Implement SIMD Absolute Difference Instructions Hurugalawadi, Naveen
@ 2013-02-26 15:23 ` Marcus Shawcroft
2013-02-27 5:15 ` Hurugalawadi, Naveen
2013-02-26 15:29 ` Marcus Shawcroft
1 sibling, 1 reply; 10+ messages in thread
From: Marcus Shawcroft @ 2013-02-26 15:23 UTC (permalink / raw)
To: Hurugalawadi, Naveen; +Cc: gcc-patches
Hi Naveen,
Please accept my apologies for the delay in responding to your patch.
On 30/01/13 05:46, Hurugalawadi, Naveen wrote:
> +(define_insn "abd<mode>_3"
> + [(set (match_operand:VDQ_BHSI 0 "register_operand" "=w")
> + (abs:VDQ_BHSI (minus:VDQ_BHSI
Please drop the trailing white space, here and on the following patterns.
> --- gcc/testsuite/gcc.target/aarch64/vect-fp.x 2013-01-24 20:10:09.703833384 +0530
> +++ gcc/testsuite/gcc.target/aarch64/vect-fp.x 2013-01-29 14:11:16.909568490 +0530
> @@ -7,6 +7,16 @@ typedef double *__restrict__ pRF64;
> extern float fabsf (float);
> extern double fabs (double);
>
> +#define DEF3a(fname, type, op) \
> + void fname##_##type (pR##type a, \
> + pR##type b, \
> + pR##type c) \
> + { \
> + int i; \
> + for (i=0; i<16; i++) \
GNU style, spaces around '=' and '<'.
> --- gcc/testsuite/gcc.target/aarch64/vect.x 2013-01-24 20:10:09.703833384 +0530
> +++ gcc/testsuite/gcc.target/aarch64/vect.x 2013-01-29 18:37:32.321808454 +0530
> @@ -138,3 +138,18 @@ long long reduce_add_s64 (pRINT64 a)
>
> return s;
> }
> +
> +void sabd (pRINT a, pRINT b, pRINT c)
> +{
> + int i;
> + for (i=0;i<16;i++)
> + c[i] = abs (a[i] - b[i]);
> +}
> +
> +void saba (pRINT a, pRINT b, pRINT c)
> +{
> + int i;
> + for (i=0;i<16;i++)
> + c[i] += abs (a[i] - b[i]);
> +}
> +
GNU style please.
Cheers
/Marcus
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [Patch, AArch64] Implement SIMD Absolute Difference Instructions
2013-01-30 5:46 [Patch, AArch64] Implement SIMD Absolute Difference Instructions Hurugalawadi, Naveen
2013-02-26 15:23 ` Marcus Shawcroft
@ 2013-02-26 15:29 ` Marcus Shawcroft
1 sibling, 0 replies; 10+ messages in thread
From: Marcus Shawcroft @ 2013-02-26 15:29 UTC (permalink / raw)
To: Hurugalawadi, Naveen; +Cc: gcc-patches
On 30/01/13 05:46, Hurugalawadi, Naveen wrote:
> Hi,
>
> Please find attached the patch that implements absolute difference
> instructions for aarch64 target.
> The patch modifies the testcase vect.c and vect-fp.c to check the
> generated instructions and also their functionality.
>
> Please review the patch and let me know if there should be any
> modifications?
>
> simd_fadd,\
> + simd_fabd,\
> simd_fcmp,\
Alphabetical order please.
Cheers
/Marcus
^ permalink raw reply [flat|nested] 10+ messages in thread
* RE: [Patch, AArch64] Implement SIMD Absolute Difference Instructions
2013-02-26 15:23 ` Marcus Shawcroft
@ 2013-02-27 5:15 ` Hurugalawadi, Naveen
2013-02-27 10:02 ` Marcus Shawcroft
0 siblings, 1 reply; 10+ messages in thread
From: Hurugalawadi, Naveen @ 2013-02-27 5:15 UTC (permalink / raw)
To: Marcus Shawcroft; +Cc: gcc-patches
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Hi Marcus,
Thanks for reviewing the patch and your comments.
>> Please drop the trailing white space, here and on the following
>> patterns.
The trailing white spaces are observed only in the patch. When the
patch is applied on sources, there are no trailing white spaces.
>> GNU style, spaces around '=' and '<'.
Sorry for missing the indentation part. Spaces have been added
wherever needed.
Please review the modified patch and let me know if there should be
any further modifications?
Thanks,
Naveen
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: simd-abd.patch --]
[-- Type: text/x-patch; name="simd-abd.patch", Size: 6594 bytes --]
--- gcc/config/aarch64/aarch64-simd.md 2013-02-20 13:24:21.608042549 +0530
+++ gcc/config/aarch64/aarch64-simd.md 2013-02-27 10:26:47.367204006 +0530
@@ -44,6 +44,7 @@
; simd_dup duplicate element.
; simd_dupgp duplicate general purpose register.
; simd_ext bitwise extract from pair.
+; simd_fabd floating absolute difference and accumulate.
; simd_fadd floating point add/sub.
; simd_fcmp floating point compare.
; simd_fcvti floating point convert to integer.
@@ -147,6 +148,7 @@
simd_dup,\
simd_dupgp,\
simd_ext,\
+ simd_fabd,\
simd_fadd,\
simd_fcmp,\
simd_fcvti,\
@@ -520,6 +522,40 @@
(set_attr "simd_mode" "<MODE>")]
)
+(define_insn "abd<mode>_3"
+ [(set (match_operand:VDQ_BHSI 0 "register_operand" "=w")
+ (abs:VDQ_BHSI (minus:VDQ_BHSI
+ (match_operand:VDQ_BHSI 1 "register_operand" "w")
+ (match_operand:VDQ_BHSI 2 "register_operand" "w"))))]
+ "TARGET_SIMD"
+ "sabd\t%0.<Vtype>, %1.<Vtype>, %2.<Vtype>"
+ [(set_attr "simd_type" "simd_abd")
+ (set_attr "simd_mode" "<MODE>")]
+)
+
+(define_insn "aba<mode>_3"
+ [(set (match_operand:VDQ_BHSI 0 "register_operand" "=w")
+ (plus:VDQ_BHSI (abs:VDQ_BHSI (minus:VDQ_BHSI
+ (match_operand:VDQ_BHSI 1 "register_operand" "w")
+ (match_operand:VDQ_BHSI 2 "register_operand" "w")))
+ (match_operand:VDQ_BHSI 3 "register_operand" "0")))]
+ "TARGET_SIMD"
+ "saba\t%0.<Vtype>, %1.<Vtype>, %2.<Vtype>"
+ [(set_attr "simd_type" "simd_abd")
+ (set_attr "simd_mode" "<MODE>")]
+)
+
+(define_insn "fabd<mode>_3"
+ [(set (match_operand:VDQF 0 "register_operand" "=w")
+ (abs:VDQF (minus:VDQF
+ (match_operand:VDQF 1 "register_operand" "w")
+ (match_operand:VDQF 2 "register_operand" "w"))))]
+ "TARGET_SIMD"
+ "fabd\t%0.<Vtype>, %1.<Vtype>, %2.<Vtype>"
+ [(set_attr "simd_type" "simd_fabd")
+ (set_attr "simd_mode" "<MODE>")]
+)
+
(define_insn "and<mode>3"
[(set (match_operand:VDQ 0 "register_operand" "=w")
(and:VDQ (match_operand:VDQ 1 "register_operand" "w")
--- gcc/testsuite/gcc.target/aarch64/vect.c 2013-02-20 13:24:22.140042557 +0530
+++ gcc/testsuite/gcc.target/aarch64/vect.c 2013-02-27 10:21:27.991945664 +0530
@@ -55,6 +55,8 @@ int main (void)
int smin_vector[] = {0, -1, -2, -3, -4, -5, -6, -7, -8, -9, -10, -11, -12, -13, -14, -15};
unsigned int umax_vector[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15};
unsigned int umin_vector[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15};
+ int sabd_vector[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
+ int saba_vector[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
int reduce_smax_value = 0;
int reduce_smin_value = -15;
unsigned int reduce_umax_value = 15;
@@ -81,6 +83,8 @@ int main (void)
TEST (smin, s);
TEST (umax, u);
TEST (umin, u);
+ TEST (sabd, s);
+ TEST (saba, s);
TESTV (reduce_smax, s);
TESTV (reduce_smin, s);
TESTV (reduce_umax, u);
--- gcc/testsuite/gcc.target/aarch64/vect-compile.c 2013-02-20 13:24:22.140042557 +0530
+++ gcc/testsuite/gcc.target/aarch64/vect-compile.c 2013-02-27 10:21:27.991945664 +0530
@@ -16,5 +16,7 @@
/* { dg-final { scan-assembler "uminv" } } */
/* { dg-final { scan-assembler "smaxv" } } */
/* { dg-final { scan-assembler "sminv" } } */
+/* { dg-final { scan-assembler "sabd" } } */
+/* { dg-final { scan-assembler "saba" } } */
/* { dg-final { scan-assembler-times "addv" 2} } */
/* { dg-final { scan-assembler-times "addp" 2} } */
--- gcc/testsuite/gcc.target/aarch64/vect-fp.c 2013-02-20 13:24:22.140042557 +0530
+++ gcc/testsuite/gcc.target/aarch64/vect-fp.c 2013-02-27 10:21:27.995943664 +0530
@@ -117,6 +117,16 @@ int main (void)
9.0, 10.0, 11.0, 12.0,
13.0, 14.0, 15.0, 16.0 };
+ F32 fabd_F32_vector[] = { 1.0f, 1.0f, 1.0f, 1.0f,
+ 1.0f, 1.0f, 1.0f, 1.0f,
+ 1.0f, 1.0f, 1.0f, 1.0f,
+ 1.0f, 1.0f, 1.0f, 1.0f };
+
+ F64 fabd_F64_vector[] = { 1.0, 1.0, 1.0, 1.0,
+ 1.0, 1.0, 1.0, 1.0,
+ 1.0, 1.0, 1.0, 1.0,
+ 1.0, 1.0, 1.0, 1.0 };
+
/* Setup input vectors. */
for (i=1; i<=16; i++)
{
@@ -132,6 +142,7 @@ int main (void)
TEST (div, 3);
TEST (neg, 2);
TEST (abs, 2);
+ TEST (fabd, 3);
return 0;
}
--- gcc/testsuite/gcc.target/aarch64/vect-fp-compile.c 2013-02-20 13:24:22.140042557 +0530
+++ gcc/testsuite/gcc.target/aarch64/vect-fp-compile.c 2013-02-27 10:21:27.995943664 +0530
@@ -11,3 +11,4 @@
/* { dg-final { scan-assembler "fdiv\\tv" } } */
/* { dg-final { scan-assembler "fneg\\tv" } } */
/* { dg-final { scan-assembler "fabs\\tv" } } */
+/* { dg-final { scan-assembler "fabd\\tv" } } */
--- gcc/testsuite/gcc.target/aarch64/vect-fp.x 2013-02-20 13:24:22.140042557 +0530
+++ gcc/testsuite/gcc.target/aarch64/vect-fp.x 2013-02-27 10:25:58.231203919 +0530
@@ -7,13 +7,23 @@ typedef double *__restrict__ pRF64;
extern float fabsf (float);
extern double fabs (double);
+#define DEF3a(fname, type, op) \
+ void fname##_##type (pR##type a, \
+ pR##type b, \
+ pR##type c) \
+ { \
+ int i; \
+ for (i = 0; i < 16; i++) \
+ a[i] = op (b[i] - c[i]); \
+ }
+
#define DEF3(fname, type, op) \
void fname##_##type (pR##type a, \
pR##type b, \
pR##type c) \
{ \
int i; \
- for (i=0; i<16; i++) \
+ for (i = 0; i < 16; i++) \
a[i] = b[i] op c[i]; \
}
@@ -22,11 +32,15 @@ extern double fabs (double);
pR##type b) \
{ \
int i; \
- for (i=0; i<16; i++) \
+ for (i = 0; i < 16; i++) \
a[i] = op(b[i]); \
}
+#define DEFN3a(fname, op) \
+ DEF3a (fname, F32, op) \
+ DEF3a (fname, F64, op)
+
#define DEFN3(fname, op) \
DEF3 (fname, F32, op) \
DEF3 (fname, F64, op)
@@ -42,3 +56,5 @@ DEFN3 (div, /)
DEFN2 (neg, -)
DEF2 (abs, F32, fabsf)
DEF2 (abs, F64, fabs)
+DEF3a (fabd, F32, fabsf)
+DEF3a (fabd, F64, fabs)
--- gcc/testsuite/gcc.target/aarch64/vect.x 2013-02-20 13:24:22.140042557 +0530
+++ gcc/testsuite/gcc.target/aarch64/vect.x 2013-02-27 10:25:49.451203905 +0530
@@ -138,3 +138,18 @@ long long reduce_add_s64 (pRINT64 a)
return s;
}
+
+void sabd (pRINT a, pRINT b, pRINT c)
+{
+ int i;
+ for (i = 0; i < 16; i++)
+ c[i] = abs (a[i] - b[i]);
+}
+
+void saba (pRINT a, pRINT b, pRINT c)
+{
+ int i;
+ for (i = 0; i < 16; i++)
+ c[i] += abs (a[i] - b[i]);
+}
+
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [Patch, AArch64] Implement SIMD Absolute Difference Instructions
2013-02-27 5:15 ` Hurugalawadi, Naveen
@ 2013-02-27 10:02 ` Marcus Shawcroft
2013-02-27 10:42 ` Hurugalawadi, Naveen
0 siblings, 1 reply; 10+ messages in thread
From: Marcus Shawcroft @ 2013-02-27 10:02 UTC (permalink / raw)
To: Hurugalawadi, Naveen; +Cc: gcc-patches
On 27/02/13 05:15, Hurugalawadi, Naveen wrote:
> The trailing white spaces are observed only in the patch. When the
> patch is applied on sources, there are no trailing white spaces.
When I applied the patch to my dev tree it resulted in source with
trailing white space.
Please re-spin the patch to drop the trailing white space.
Thanks
/Marcus
^ permalink raw reply [flat|nested] 10+ messages in thread
* RE: [Patch, AArch64] Implement SIMD Absolute Difference Instructions
2013-02-27 10:02 ` Marcus Shawcroft
@ 2013-02-27 10:42 ` Hurugalawadi, Naveen
2013-02-27 10:58 ` Marcus Shawcroft
0 siblings, 1 reply; 10+ messages in thread
From: Hurugalawadi, Naveen @ 2013-02-27 10:42 UTC (permalink / raw)
To: Marcus Shawcroft; +Cc: gcc-patches
[-- Attachment #1: Type: text/plain, Size: 939 bytes --]
Hi Marcus,
I had a "TAB" inserted as the pattern was starting at the 9th column.
Hence, it showed trailing whites paces in the patch.
It has been modified according to the earlier patterns in the same file.
Please find attached the modified patch as per your suggestions.
Thanks,
Naveen
________________________________________
From: Marcus Shawcroft [marcus.shawcroft@arm.com]
Sent: Wednesday, February 27, 2013 3:32 PM
To: Hurugalawadi, Naveen
Cc: gcc-patches@gcc.gnu.org
Subject: Re: [Patch, AArch64] Implement SIMD Absolute Difference Instructions
On 27/02/13 05:15, Hurugalawadi, Naveen wrote:
> The trailing white spaces are observed only in the patch. When the
> patch is applied on sources, there are no trailing white spaces.
When I applied the patch to my dev tree it resulted in source with
trailing white space.
Please re-spin the patch to drop the trailing white space.
Thanks
/Marcus
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: simd-abd.patch --]
[-- Type: text/x-patch; name="simd-abd.patch", Size: 6615 bytes --]
--- gcc/config/aarch64/aarch64-simd.md 2013-02-20 13:24:21.608042549 +0530
+++ gcc/config/aarch64/aarch64-simd.md 2013-02-27 16:04:24.839239567 +0530
@@ -44,6 +44,7 @@
; simd_dup duplicate element.
; simd_dupgp duplicate general purpose register.
; simd_ext bitwise extract from pair.
+; simd_fabd floating absolute difference and accumulate.
; simd_fadd floating point add/sub.
; simd_fcmp floating point compare.
; simd_fcvti floating point convert to integer.
@@ -147,6 +148,7 @@
simd_dup,\
simd_dupgp,\
simd_ext,\
+ simd_fabd,\
simd_fadd,\
simd_fcmp,\
simd_fcvti,\
@@ -520,6 +522,40 @@
(set_attr "simd_mode" "<MODE>")]
)
+(define_insn "abd<mode>_3"
+ [(set (match_operand:VDQ_BHSI 0 "register_operand" "=w")
+ (abs:VDQ_BHSI (minus:VDQ_BHSI
+ (match_operand:VDQ_BHSI 1 "register_operand" "w")
+ (match_operand:VDQ_BHSI 2 "register_operand" "w"))))]
+ "TARGET_SIMD"
+ "sabd\t%0.<Vtype>, %1.<Vtype>, %2.<Vtype>"
+ [(set_attr "simd_type" "simd_abd")
+ (set_attr "simd_mode" "<MODE>")]
+)
+
+(define_insn "aba<mode>_3"
+ [(set (match_operand:VDQ_BHSI 0 "register_operand" "=w")
+ (plus:VDQ_BHSI (abs:VDQ_BHSI (minus:VDQ_BHSI
+ (match_operand:VDQ_BHSI 1 "register_operand" "w")
+ (match_operand:VDQ_BHSI 2 "register_operand" "w")))
+ (match_operand:VDQ_BHSI 3 "register_operand" "0")))]
+ "TARGET_SIMD"
+ "saba\t%0.<Vtype>, %1.<Vtype>, %2.<Vtype>"
+ [(set_attr "simd_type" "simd_abd")
+ (set_attr "simd_mode" "<MODE>")]
+)
+
+(define_insn "fabd<mode>_3"
+ [(set (match_operand:VDQF 0 "register_operand" "=w")
+ (abs:VDQF (minus:VDQF
+ (match_operand:VDQF 1 "register_operand" "w")
+ (match_operand:VDQF 2 "register_operand" "w"))))]
+ "TARGET_SIMD"
+ "fabd\t%0.<Vtype>, %1.<Vtype>, %2.<Vtype>"
+ [(set_attr "simd_type" "simd_fabd")
+ (set_attr "simd_mode" "<MODE>")]
+)
+
(define_insn "and<mode>3"
[(set (match_operand:VDQ 0 "register_operand" "=w")
(and:VDQ (match_operand:VDQ 1 "register_operand" "w")
--- gcc/testsuite/gcc.target/aarch64/vect.c 2013-02-20 13:24:22.140042557 +0530
+++ gcc/testsuite/gcc.target/aarch64/vect.c 2013-02-27 15:55:57.855238677 +0530
@@ -55,6 +55,8 @@ int main (void)
int smin_vector[] = {0, -1, -2, -3, -4, -5, -6, -7, -8, -9, -10, -11, -12, -13, -14, -15};
unsigned int umax_vector[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15};
unsigned int umin_vector[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15};
+ int sabd_vector[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
+ int saba_vector[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
int reduce_smax_value = 0;
int reduce_smin_value = -15;
unsigned int reduce_umax_value = 15;
@@ -81,6 +83,8 @@ int main (void)
TEST (smin, s);
TEST (umax, u);
TEST (umin, u);
+ TEST (sabd, s);
+ TEST (saba, s);
TESTV (reduce_smax, s);
TESTV (reduce_smin, s);
TESTV (reduce_umax, u);
--- gcc/testsuite/gcc.target/aarch64/vect-compile.c 2013-02-20 13:24:22.140042557 +0530
+++ gcc/testsuite/gcc.target/aarch64/vect-compile.c 2013-02-27 15:55:57.855238677 +0530
@@ -16,5 +16,7 @@
/* { dg-final { scan-assembler "uminv" } } */
/* { dg-final { scan-assembler "smaxv" } } */
/* { dg-final { scan-assembler "sminv" } } */
+/* { dg-final { scan-assembler "sabd" } } */
+/* { dg-final { scan-assembler "saba" } } */
/* { dg-final { scan-assembler-times "addv" 2} } */
/* { dg-final { scan-assembler-times "addp" 2} } */
--- gcc/testsuite/gcc.target/aarch64/vect-fp.c 2013-02-20 13:24:22.140042557 +0530
+++ gcc/testsuite/gcc.target/aarch64/vect-fp.c 2013-02-27 15:55:57.855238677 +0530
@@ -117,6 +117,16 @@ int main (void)
9.0, 10.0, 11.0, 12.0,
13.0, 14.0, 15.0, 16.0 };
+ F32 fabd_F32_vector[] = { 1.0f, 1.0f, 1.0f, 1.0f,
+ 1.0f, 1.0f, 1.0f, 1.0f,
+ 1.0f, 1.0f, 1.0f, 1.0f,
+ 1.0f, 1.0f, 1.0f, 1.0f };
+
+ F64 fabd_F64_vector[] = { 1.0, 1.0, 1.0, 1.0,
+ 1.0, 1.0, 1.0, 1.0,
+ 1.0, 1.0, 1.0, 1.0,
+ 1.0, 1.0, 1.0, 1.0 };
+
/* Setup input vectors. */
for (i=1; i<=16; i++)
{
@@ -132,6 +142,7 @@ int main (void)
TEST (div, 3);
TEST (neg, 2);
TEST (abs, 2);
+ TEST (fabd, 3);
return 0;
}
--- gcc/testsuite/gcc.target/aarch64/vect-fp-compile.c 2013-02-20 13:24:22.140042557 +0530
+++ gcc/testsuite/gcc.target/aarch64/vect-fp-compile.c 2013-02-27 15:55:57.855238677 +0530
@@ -11,3 +11,4 @@
/* { dg-final { scan-assembler "fdiv\\tv" } } */
/* { dg-final { scan-assembler "fneg\\tv" } } */
/* { dg-final { scan-assembler "fabs\\tv" } } */
+/* { dg-final { scan-assembler "fabd\\tv" } } */
--- gcc/testsuite/gcc.target/aarch64/vect-fp.x 2013-02-20 13:24:22.140042557 +0530
+++ gcc/testsuite/gcc.target/aarch64/vect-fp.x 2013-02-27 15:55:57.855238677 +0530
@@ -7,13 +7,23 @@ typedef double *__restrict__ pRF64;
extern float fabsf (float);
extern double fabs (double);
+#define DEF3a(fname, type, op) \
+ void fname##_##type (pR##type a, \
+ pR##type b, \
+ pR##type c) \
+ { \
+ int i; \
+ for (i = 0; i < 16; i++) \
+ a[i] = op (b[i] - c[i]); \
+ }
+
#define DEF3(fname, type, op) \
void fname##_##type (pR##type a, \
pR##type b, \
pR##type c) \
{ \
int i; \
- for (i=0; i<16; i++) \
+ for (i = 0; i < 16; i++) \
a[i] = b[i] op c[i]; \
}
@@ -22,11 +32,15 @@ extern double fabs (double);
pR##type b) \
{ \
int i; \
- for (i=0; i<16; i++) \
+ for (i = 0; i < 16; i++) \
a[i] = op(b[i]); \
}
+#define DEFN3a(fname, op) \
+ DEF3a (fname, F32, op) \
+ DEF3a (fname, F64, op)
+
#define DEFN3(fname, op) \
DEF3 (fname, F32, op) \
DEF3 (fname, F64, op)
@@ -42,3 +56,5 @@ DEFN3 (div, /)
DEFN2 (neg, -)
DEF2 (abs, F32, fabsf)
DEF2 (abs, F64, fabs)
+DEF3a (fabd, F32, fabsf)
+DEF3a (fabd, F64, fabs)
--- gcc/testsuite/gcc.target/aarch64/vect.x 2013-02-20 13:24:22.140042557 +0530
+++ gcc/testsuite/gcc.target/aarch64/vect.x 2013-02-27 15:55:57.855238677 +0530
@@ -138,3 +138,18 @@ long long reduce_add_s64 (pRINT64 a)
return s;
}
+
+void sabd (pRINT a, pRINT b, pRINT c)
+{
+ int i;
+ for (i = 0; i < 16; i++)
+ c[i] = abs (a[i] - b[i]);
+}
+
+void saba (pRINT a, pRINT b, pRINT c)
+{
+ int i;
+ for (i = 0; i < 16; i++)
+ c[i] += abs (a[i] - b[i]);
+}
+
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [Patch, AArch64] Implement SIMD Absolute Difference Instructions
2013-02-27 10:42 ` Hurugalawadi, Naveen
@ 2013-02-27 10:58 ` Marcus Shawcroft
2013-02-27 11:17 ` Hurugalawadi, Naveen
0 siblings, 1 reply; 10+ messages in thread
From: Marcus Shawcroft @ 2013-02-27 10:58 UTC (permalink / raw)
To: Hurugalawadi, Naveen; +Cc: gcc-patches
On 27/02/13 10:42, Hurugalawadi, Naveen wrote:
> Hi Marcus,
>
> I had a "TAB" inserted as the pattern was starting at the 9th column.
> Hence, it showed trailing whites paces in the patch.
The use of TAB there is fine. The issue is that you have trail white
space at the end of the line, which is still present in the latest patch.
/M
^ permalink raw reply [flat|nested] 10+ messages in thread
* RE: [Patch, AArch64] Implement SIMD Absolute Difference Instructions
2013-02-27 10:58 ` Marcus Shawcroft
@ 2013-02-27 11:17 ` Hurugalawadi, Naveen
2013-02-27 11:24 ` Marcus Shawcroft
2013-03-01 13:51 ` James Greenhalgh
0 siblings, 2 replies; 10+ messages in thread
From: Hurugalawadi, Naveen @ 2013-02-27 11:17 UTC (permalink / raw)
To: Marcus Shawcroft; +Cc: gcc-patches
[-- Attachment #1: Type: text/plain, Size: 352 bytes --]
Hi Marcus,
>> The use of TAB there is fine. The issue is that you have trail white
>> space at the end of the line, which is still present in the latest patch.
Sorry. I confused it with spaces at the start of pattern instead of
trailing space. I have modified it as per your suggestion.
Please review the modified patch.
Thanks,
Naveen
[-- Warning: decoded text below may be mangled, UTF-8 assumed --]
[-- Attachment #2: simd-abd.patch --]
[-- Type: text/x-patch; name="simd-abd.patch", Size: 6582 bytes --]
--- gcc/config/aarch64/aarch64-simd.md 2013-02-20 13:24:21.608042549 +0530
+++ gcc/config/aarch64/aarch64-simd.md 2013-02-27 16:34:34.203242741 +0530
@@ -44,6 +44,7 @@
; simd_dup duplicate element.
; simd_dupgp duplicate general purpose register.
; simd_ext bitwise extract from pair.
+; simd_fabd floating absolute difference and accumulate.
; simd_fadd floating point add/sub.
; simd_fcmp floating point compare.
; simd_fcvti floating point convert to integer.
@@ -147,6 +148,7 @@
simd_dup,\
simd_dupgp,\
simd_ext,\
+ simd_fabd,\
simd_fadd,\
simd_fcmp,\
simd_fcvti,\
@@ -520,6 +522,40 @@
(set_attr "simd_mode" "<MODE>")]
)
+(define_insn "abd<mode>_3"
+ [(set (match_operand:VDQ_BHSI 0 "register_operand" "=w")
+ (abs:VDQ_BHSI (minus:VDQ_BHSI
+ (match_operand:VDQ_BHSI 1 "register_operand" "w")
+ (match_operand:VDQ_BHSI 2 "register_operand" "w"))))]
+ "TARGET_SIMD"
+ "sabd\t%0.<Vtype>, %1.<Vtype>, %2.<Vtype>"
+ [(set_attr "simd_type" "simd_abd")
+ (set_attr "simd_mode" "<MODE>")]
+)
+
+(define_insn "aba<mode>_3"
+ [(set (match_operand:VDQ_BHSI 0 "register_operand" "=w")
+ (plus:VDQ_BHSI (abs:VDQ_BHSI (minus:VDQ_BHSI
+ (match_operand:VDQ_BHSI 1 "register_operand" "w")
+ (match_operand:VDQ_BHSI 2 "register_operand" "w")))
+ (match_operand:VDQ_BHSI 3 "register_operand" "0")))]
+ "TARGET_SIMD"
+ "saba\t%0.<Vtype>, %1.<Vtype>, %2.<Vtype>"
+ [(set_attr "simd_type" "simd_abd")
+ (set_attr "simd_mode" "<MODE>")]
+)
+
+(define_insn "fabd<mode>_3"
+ [(set (match_operand:VDQF 0 "register_operand" "=w")
+ (abs:VDQF (minus:VDQF
+ (match_operand:VDQF 1 "register_operand" "w")
+ (match_operand:VDQF 2 "register_operand" "w"))))]
+ "TARGET_SIMD"
+ "fabd\t%0.<Vtype>, %1.<Vtype>, %2.<Vtype>"
+ [(set_attr "simd_type" "simd_fabd")
+ (set_attr "simd_mode" "<MODE>")]
+)
+
(define_insn "and<mode>3"
[(set (match_operand:VDQ 0 "register_operand" "=w")
(and:VDQ (match_operand:VDQ 1 "register_operand" "w")
--- gcc/testsuite/gcc.target/aarch64/vect.c 2013-02-20 13:24:22.140042557 +0530
+++ gcc/testsuite/gcc.target/aarch64/vect.c 2013-02-27 16:34:34.203242741 +0530
@@ -55,6 +55,8 @@ int main (void)
int smin_vector[] = {0, -1, -2, -3, -4, -5, -6, -7, -8, -9, -10, -11, -12, -13, -14, -15};
unsigned int umax_vector[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15};
unsigned int umin_vector[] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15};
+ int sabd_vector[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
+ int saba_vector[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
int reduce_smax_value = 0;
int reduce_smin_value = -15;
unsigned int reduce_umax_value = 15;
@@ -81,6 +83,8 @@ int main (void)
TEST (smin, s);
TEST (umax, u);
TEST (umin, u);
+ TEST (sabd, s);
+ TEST (saba, s);
TESTV (reduce_smax, s);
TESTV (reduce_smin, s);
TESTV (reduce_umax, u);
--- gcc/testsuite/gcc.target/aarch64/vect-compile.c 2013-02-20 13:24:22.140042557 +0530
+++ gcc/testsuite/gcc.target/aarch64/vect-compile.c 2013-02-27 16:34:34.231242741 +0530
@@ -16,5 +16,7 @@
/* { dg-final { scan-assembler "uminv" } } */
/* { dg-final { scan-assembler "smaxv" } } */
/* { dg-final { scan-assembler "sminv" } } */
+/* { dg-final { scan-assembler "sabd" } } */
+/* { dg-final { scan-assembler "saba" } } */
/* { dg-final { scan-assembler-times "addv" 2} } */
/* { dg-final { scan-assembler-times "addp" 2} } */
--- gcc/testsuite/gcc.target/aarch64/vect-fp.c 2013-02-20 13:24:22.140042557 +0530
+++ gcc/testsuite/gcc.target/aarch64/vect-fp.c 2013-02-27 16:34:34.235242743 +0530
@@ -117,6 +117,16 @@ int main (void)
9.0, 10.0, 11.0, 12.0,
13.0, 14.0, 15.0, 16.0 };
+ F32 fabd_F32_vector[] = { 1.0f, 1.0f, 1.0f, 1.0f,
+ 1.0f, 1.0f, 1.0f, 1.0f,
+ 1.0f, 1.0f, 1.0f, 1.0f,
+ 1.0f, 1.0f, 1.0f, 1.0f };
+
+ F64 fabd_F64_vector[] = { 1.0, 1.0, 1.0, 1.0,
+ 1.0, 1.0, 1.0, 1.0,
+ 1.0, 1.0, 1.0, 1.0,
+ 1.0, 1.0, 1.0, 1.0 };
+
/* Setup input vectors. */
for (i=1; i<=16; i++)
{
@@ -132,6 +142,7 @@ int main (void)
TEST (div, 3);
TEST (neg, 2);
TEST (abs, 2);
+ TEST (fabd, 3);
return 0;
}
--- gcc/testsuite/gcc.target/aarch64/vect-fp-compile.c 2013-02-20 13:24:22.140042557 +0530
+++ gcc/testsuite/gcc.target/aarch64/vect-fp-compile.c 2013-02-27 16:34:34.235242743 +0530
@@ -11,3 +11,4 @@
/* { dg-final { scan-assembler "fdiv\\tv" } } */
/* { dg-final { scan-assembler "fneg\\tv" } } */
/* { dg-final { scan-assembler "fabs\\tv" } } */
+/* { dg-final { scan-assembler "fabd\\tv" } } */
--- gcc/testsuite/gcc.target/aarch64/vect-fp.x 2013-02-20 13:24:22.140042557 +0530
+++ gcc/testsuite/gcc.target/aarch64/vect-fp.x 2013-02-27 16:37:24.211243041 +0530
@@ -7,13 +7,23 @@ typedef double *__restrict__ pRF64;
extern float fabsf (float);
extern double fabs (double);
+#define DEF3a(fname, type, op) \
+ void fname##_##type (pR##type a, \
+ pR##type b, \
+ pR##type c) \
+ { \
+ int i; \
+ for (i = 0; i < 16; i++) \
+ a[i] = op (b[i] - c[i]); \
+ }
+
#define DEF3(fname, type, op) \
void fname##_##type (pR##type a, \
pR##type b, \
pR##type c) \
{ \
int i; \
- for (i=0; i<16; i++) \
+ for (i = 0; i < 16; i++) \
a[i] = b[i] op c[i]; \
}
@@ -22,11 +32,15 @@ extern double fabs (double);
pR##type b) \
{ \
int i; \
- for (i=0; i<16; i++) \
+ for (i = 0; i < 16; i++) \
a[i] = op(b[i]); \
}
+#define DEFN3a(fname, op) \
+ DEF3a (fname, F32, op) \
+ DEF3a (fname, F64, op)
+
#define DEFN3(fname, op) \
DEF3 (fname, F32, op) \
DEF3 (fname, F64, op)
@@ -42,3 +56,5 @@ DEFN3 (div, /)
DEFN2 (neg, -)
DEF2 (abs, F32, fabsf)
DEF2 (abs, F64, fabs)
+DEF3a (fabd, F32, fabsf)
+DEF3a (fabd, F64, fabs)
--- gcc/testsuite/gcc.target/aarch64/vect.x 2013-02-20 13:24:22.140042557 +0530
+++ gcc/testsuite/gcc.target/aarch64/vect.x 2013-02-27 16:34:34.235242743 +0530
@@ -138,3 +138,18 @@ long long reduce_add_s64 (pRINT64 a)
return s;
}
+
+void sabd (pRINT a, pRINT b, pRINT c)
+{
+ int i;
+ for (i = 0; i < 16; i++)
+ c[i] = abs (a[i] - b[i]);
+}
+
+void saba (pRINT a, pRINT b, pRINT c)
+{
+ int i;
+ for (i = 0; i < 16; i++)
+ c[i] += abs (a[i] - b[i]);
+}
+
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [Patch, AArch64] Implement SIMD Absolute Difference Instructions
2013-02-27 11:17 ` Hurugalawadi, Naveen
@ 2013-02-27 11:24 ` Marcus Shawcroft
2013-03-01 13:51 ` James Greenhalgh
1 sibling, 0 replies; 10+ messages in thread
From: Marcus Shawcroft @ 2013-02-27 11:24 UTC (permalink / raw)
To: Hurugalawadi, Naveen; +Cc: gcc-patches, Matthew Gretton-Dann
On 27/02/13 11:16, Hurugalawadi, Naveen wrote:
> Hi Marcus,
>
>>> The use of TAB there is fine. The issue is that you have trail white
>>> space at the end of the line, which is still present in the latest patch.
>
> Sorry. I confused it with spaces at the start of pattern instead of
> trailing space. I have modified it as per your suggestion.
> Please review the modified patch.
>
> Thanks,
> Naveen
>
Thank you. This is OK for stage-1.
/Marcus
^ permalink raw reply [flat|nested] 10+ messages in thread
* RE: [Patch, AArch64] Implement SIMD Absolute Difference Instructions
2013-02-27 11:17 ` Hurugalawadi, Naveen
2013-02-27 11:24 ` Marcus Shawcroft
@ 2013-03-01 13:51 ` James Greenhalgh
1 sibling, 0 replies; 10+ messages in thread
From: James Greenhalgh @ 2013-03-01 13:51 UTC (permalink / raw)
To: 'Hurugalawadi, Naveen', Marcus Shawcroft; +Cc: gcc-patches
> >> The use of TAB there is fine. The issue is that you have trail
> white
> >> space at the end of the line, which is still present in the latest
> patch.
>
> Sorry. I confused it with spaces at the start of pattern instead of
> trailing space. I have modified it as per your suggestion.
> Please review the modified patch.
Hi Naveen,
It looks like you didn't quite catch all of them:
> +#define DEF3a(fname, type, op) \
> + void fname##_##type (pR##type a, \
> + pR##type b, \
> + pR##type c) \
> + { \
> + int i; \
> + for (i = 0; i < 16; i++) \<!tab!>
> + a[i] = op (b[i] - c[i]); \
> + }
This one introduces a problem for the testsuite as whitespace between
a \ and the newline is an error on some compilers and a warning on GCC.
There is a script at contrib/check_GNU_style.sh which is helpful
for catching bugs like this.
Thanks,
James Greenhalgh
^ permalink raw reply [flat|nested] 10+ messages in thread
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-- links below jump to the message on this page --
2013-01-30 5:46 [Patch, AArch64] Implement SIMD Absolute Difference Instructions Hurugalawadi, Naveen
2013-02-26 15:23 ` Marcus Shawcroft
2013-02-27 5:15 ` Hurugalawadi, Naveen
2013-02-27 10:02 ` Marcus Shawcroft
2013-02-27 10:42 ` Hurugalawadi, Naveen
2013-02-27 10:58 ` Marcus Shawcroft
2013-02-27 11:17 ` Hurugalawadi, Naveen
2013-02-27 11:24 ` Marcus Shawcroft
2013-03-01 13:51 ` James Greenhalgh
2013-02-26 15:29 ` Marcus Shawcroft
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