From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 20304 invoked by alias); 16 Sep 2014 03:00:51 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 20288 invoked by uid 89); 16 Sep 2014 03:00:50 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-0.8 required=5.0 tests=AWL,BAYES_00,KAM_STOCKGEN,SPF_PASS autolearn=no version=3.3.2 X-HELO: service87.mimecast.com Received: from service87.mimecast.com (HELO service87.mimecast.com) (91.220.42.44) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 16 Sep 2014 03:00:48 +0000 Received: from cam-owa1.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.21]) by service87.mimecast.com; Tue, 16 Sep 2014 04:00:46 +0100 Received: from shawin188 ([10.1.255.212]) by cam-owa1.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Tue, 16 Sep 2014 04:00:44 +0100 From: "Tony Wang" To: Cc: "Richard Earnshaw" , "Ramana Radhakrishnan" References: In-Reply-To: Subject: RE: [PATCH 1/3,ARM,libgcc]Code size optimization for the fmul/fdiv and dmul/ddiv function in libgcc Date: Tue, 16 Sep 2014 03:00:00 -0000 Message-ID: <000001cfd15a$62a31330$27e93990$@arm.com> MIME-Version: 1.0 X-MC-Unique: 114091604004600201 Content-Type: text/plain; charset=WINDOWS-1252 Content-Transfer-Encoding: quoted-printable X-IsSubscribed: yes X-SW-Source: 2014-09/txt/msg01238.txt.bz2 Ping? > -----Original Message----- > From: Tony Wang [mailto:tony.wang@arm.com] > Sent: Thursday, September 04, 2014 10:15 AM > To: 'gcc-patches@gcc.gnu.org' > Cc: Richard Earnshaw; Ramana Radhakrishnan > Subject: RE: [PATCH 1/3,ARM,libgcc]Code size optimization for the fmul/fd= iv and dmul/ddiv function in libgcc >=20 > Ping 2? >=20 > > -----Original Message----- > > From: Tony Wang [mailto:tony.wang@arm.com] > > Sent: Thursday, August 28, 2014 2:02 PM > > To: 'gcc-patches@gcc.gnu.org' > > Cc: Richard Earnshaw; Ramana Radhakrishnan > > Subject: RE: [PATCH 1/3,ARM,libgcc]Code size optimization for the fmul/= fdiv and dmul/ddiv function in libgcc > > > > Ping? > > > > > -----Original Message----- > > > From: Tony Wang [mailto:tony.wang@arm.com] > > > Sent: Thursday, August 21, 2014 2:15 PM > > > To: 'gcc-patches@gcc.gnu.org' > > > Subject: [PATCH 1/3,ARM,libgcc]Code size optimization for the fmul/fd= iv and dmul/ddiv function in libgcc > > > > > > Hi there, > > > > > > In libgcc the file ieee754-sf.S and ieee754-df.S have some function p= airs which will be bundled into one .o file > > and > > > sharing the same .text section. For example, the fmul and fdiv, the l= ibgcc makefile will build them into one .o > > file > > > and archived into libgcc.a. So when user only call single float point= multiply functions, the fdiv function will > also > > be > > > linked, and as fmul and fdiv share the same .text section, linker opt= ion --gc-sections or -flot can't remove the > > > dead code. > > > > > > So this optimization just separates the function pair(fmul/fdiv and d= mul/ddiv) into different sections, > following > > > the naming pattern of -ffunction-sections(.text.__functionname), thro= ugh which the unused sections of > > > fdiv/ddiv can be eliminated through option --gcc-sections when users = only use fmul/dmul.The solution is to > > add > > > a conditional statement in the macro FUNC_START, which will condition= al change the section of a function > > > from .text to .text.__\name. when compiling with the L_arm_muldivsf3 = or L_arm_muldivdf3 macro. > > > > > > GCC regression test has been done on QEMU for Cortex-M3. No new regre= ssions when turn on this patch. > > > > > > The code reduction for thumb2 on cortex-m3 is: > > > 1. When user only use single float point multiply: > > > fmul+fdiv =3D> fmul will have a code size reduction of 318 bytes. > > > > > > 2. When user only use double float point multiply: > > > dmul+ddiv =3D> dmul will have a code size reduction of 474 bytes. > > > > > > Ok for trunk? > > > > > > BR, > > > Tony > > > > > > Step 1: Provide another option: sp-scetion to control whether to spli= t the section of a function pair into two > > part. > > > > > > gcc/libgcc/ChangeLog: > > > 2014-08-21 Tony Wang > > > > > > * config/arm/lib1funcs.S (FUNC_START): Add conditional section > > > redefine for macro L_arm_muldivsf3 and L_arm_muldivdf3 > > > (SYM_END, ARM_SYM_START): Add macros used to expose function > > > Symbols > > > > > > diff --git a/libgcc/config/arm/lib1funcs.S b/libgcc/config/arm/lib1fu= ncs.S > > > index b617137..0f87111 100644 > > > --- a/libgcc/config/arm/lib1funcs.S > > > +++ b/libgcc/config/arm/lib1funcs.S > > > @@ -418,8 +418,12 @@ SYM (\name): > > > #define THUMB_SYNTAX > > > #endif > > > > > > -.macro FUNC_START name > > > +.macro FUNC_START name sp_section=3D > > > + .ifc \sp_section, function_section > > > + .section .text.__\name,"ax",%progbits > > > + .else > > > .text > > > + .endif > > > .globl SYM (__\name) > > > TYPE (__\name) > > > .align 0 > > > @@ -429,14 +433,24 @@ SYM (\name): > > > SYM (__\name): > > > .endm > > > > > > +.macro ARM_SYM_START name > > > + TYPE (\name) > > > + .align 0 > > > +SYM (\name): > > > +.endm > > > + > > > +.macro SYM_END name > > > + SIZE (\name) > > > +.endm > > > + > > > /* Special function that will always be coded in ARM assembly, even = if > > > in Thumb-only compilation. */ > > > > > > #if defined(__thumb2__) > > > > > > /* For Thumb-2 we build everything in thumb mode. */ > > > -.macro ARM_FUNC_START name > > > - FUNC_START \name > > > +.macro ARM_FUNC_START name sp_section=3D > > > + FUNC_START \name \sp_section > > > .syntax unified > > > .endm > > > #define EQUIV .thumb_set > > > @@ -467,8 +481,12 @@ _L__\name: > > > #ifdef __ARM_ARCH_6M__ > > > #define EQUIV .thumb_set > > > #else > > > -.macro ARM_FUNC_START name > > > +.macro ARM_FUNC_START name sp_section=3D > > > + .ifc \sp_section, function_section > > > + .section .text.__\name,"ax",%progbits > > > + .else > > > .text > > > + .endif > > > .globl SYM (__\name) > > > TYPE (__\name) > > > .align 0