Hi all,

The ICE in the PR happens when we pass a 1x(128-bit float) vector as an
argument.
The aarch64 backend erroneously classifies it as a composite type when in
fact it
is a short vector according to AAPCS64
(section 4.1.2 from
http://infocenter.arm.com/help/topic/com.arm.doc.ihi0055b/IHI0055B_aapcs64.p
df).

The solution in this patch is to check aarch64_composite_type_p for a short
vector with
aarch64_short_vector_p rather than the other way around (check for
aarch64_short_vector_p
in aarch64_composite_type_p).

With this patch the testcase compiles fine and in the generated code the
argument is passed
in the simd registers like the ABI requires.

Bootstrapped and tested on aarch64-linux.

This bug appears on all release branches so it's not a regression.
Ok for trunk?
Do we want this in the release branches eventually?

Thanks,
Kyrill

2015-04-20  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

    PR target/65491
    * config/aarch64/aarch64.c (aarch64_short_vector_p): Move above
    aarch64_composite_type_p.  Remove check for aarch64_composite_type_p.
    (aarch64_composite_type_p): Return false if given type and mode are
    for a short vector.

2015-04-20  Kyrylo Tkachov  <kyrylo.tkachov@arm.com>

    PR target/65491
    * gcc.target/aarch64/pr65491_1.c: New test.
    * gcc.target/aarch64/aapcs64/type-def.h (vlf1_t): New typedef.
    * gcc.target/aarch64/aapcs64/func-ret-1.c: Add test for vlf1_t.