RE: [PATCH] [AArch32] Additional bics patterns.

["Kyrill Tkachov" <kyrylo.tkachov@arm.com>]

Hi Alex,

On 22/04/15 14:12, Alex Velenko wrote:
> Hi,
>
> This patch adds arm rtl patterns to generate bics instructions with shift.
>
> Done full regression run on arm-none-eabi.

A bootstrap on arm-none-linux-gnueabihf would be nice too.

>
>
> Is patch ok?
>
> gcc/config
>
> 2015-04-22  Alex Velenko  <Alex.Velenko@arm.com>
>
>   * arm/arm.md (andsi_not_shiftsi_si_scc): New pattern.
>   * (andsi_not_shiftsi_si_scc_no_reuse): New pattern.

the path to arm.md should be:
    * config/arm/arm.md

>
>  
> +(define_insn "andsi_not_shiftsi_si_scc_no_reuse"
> +  [(set (reg:CC_NOOV CC_REGNUM)
> +	(compare:CC_NOOV
> +		(and:SI (not:SI (match_operator:SI 0 "shift_operator"
> +			[(match_operand:SI 1 "s_register_operand" "r")
> +			 (match_operand:SI 2 "arm_rhs_operand" "rM")]))
> +			(match_operand:SI 3 "s_register_operand" "r"))
> +		(const_int 0)))
> +   (clobber (match_scratch:SI 4 "=r"))]
> +  "TARGET_32BIT"
> +  "bic%.%?\\t%4, %3, %1%S0"
> +  [(set_attr "predicable" "yes")
> +   (set_attr "conds" "set")
> +   (set_attr "shift" "1")
> +   (set (attr "type") (if_then_else (match_operand 2 "const_int_operand"
"")
> +		      (const_string "logic_shift_imm")
> +		      (const_string "logic_shift_reg")))]
> +)

Since this is a predicable instruction and has a 32-bit encoding
you should also set the 'predicable_short_it' attribute to 'no'
to prevent GCC from trying to put it inside an IT block when
compiling for ARMv8-A.

>
> +
> +(define_insn "andsi_not_shiftsi_si_scc"
> +  [(parallel [(set (reg:CC_NOOV CC_REGNUM)
> +	(compare:CC_NOOV
> +		(and:SI (not:SI (match_operator:SI 0 "shift_operator"
> +			[(match_operand:SI 1 "s_register_operand" "r")
> +			 (match_operand:SI 2 "arm_rhs_operand" "rM")]))
> +			(match_operand:SI 3 "s_register_operand" "r"))
> +		(const_int 0)))
> +	(set (match_operand:SI 4 "s_register_operand" "=r")
> +	     (and:SI (not:SI (match_op_dup 0
> +		     [(match_dup 1)
> +		      (match_dup 2)]))
> +		     (match_dup 3)))])]
> +  "TARGET_32BIT"
> +  "bic%.%?\\t%4, %3, %1%S0"
> +  [(set_attr "predicable" "yes")
> +   (set_attr "conds" "set")
> +   (set_attr "shift" "1")
> +   (set (attr "type") (if_then_else (match_operand 2 "const_int_operand"
"")
> +		      (const_string "logic_shift_imm")
> +		      (const_string "logic_shift_reg")))]
same comment about predicable_short_it.

Cheers,
Kyrill

>
> +)
> +
>  (define_insn "*andsi_notsi_si_compare0"
>    [(set (reg:CC_NOOV CC_REGNUM)
>  	(compare:CC_NOOV