From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 125237 invoked by alias); 22 Apr 2015 13:27:31 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 124515 invoked by uid 89); 22 Apr 2015 13:27:30 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.8 required=5.0 tests=AWL,BAYES_00,SPF_PASS autolearn=ham version=3.3.2 X-HELO: eu-smtp-delivery-143.mimecast.com Received: from eu-smtp-delivery-143.mimecast.com (HELO eu-smtp-delivery-143.mimecast.com) (207.82.80.143) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 22 Apr 2015 13:27:28 +0000 Received: from cam-owa2.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) by uk-mta-6.uk.mimecast.lan; Wed, 22 Apr 2015 14:27:25 +0100 Received: from E100706VM ([10.1.2.79]) by cam-owa2.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 22 Apr 2015 14:27:25 +0100 From: "Kyrill Tkachov" To: "Alex Velenko" , Cc: "Ramana Radhakrishnan" References: <1429708361-25668-1-git-send-email-alex.velenko@arm.com> In-Reply-To: <1429708361-25668-1-git-send-email-alex.velenko@arm.com> Subject: RE: [PATCH] [AArch32] Additional bics patterns. Date: Wed, 22 Apr 2015 13:27:00 -0000 Message-ID: <000001d07d00$10179f80$3046de80$@arm.com> MIME-Version: 1.0 X-MC-Unique: b9Nj2yxRSb2Bbqy5Z_zlkQ-1 Content-Type: text/plain; charset=WINDOWS-1252 Content-Transfer-Encoding: quoted-printable X-IsSubscribed: yes X-SW-Source: 2015-04/txt/msg01309.txt.bz2 Hi Alex, On 22/04/15 14:12, Alex Velenko wrote: > Hi, > > This patch adds arm rtl patterns to generate bics instructions with shift. > > Done full regression run on arm-none-eabi. A bootstrap on arm-none-linux-gnueabihf would be nice too. > > > Is patch ok? > > gcc/config > > 2015-04-22 Alex Velenko > > * arm/arm.md (andsi_not_shiftsi_si_scc): New pattern. > * (andsi_not_shiftsi_si_scc_no_reuse): New pattern. the path to arm.md should be: * config/arm/arm.md > >=20=20 > +(define_insn "andsi_not_shiftsi_si_scc_no_reuse" > + [(set (reg:CC_NOOV CC_REGNUM) > + (compare:CC_NOOV > + (and:SI (not:SI (match_operator:SI 0 "shift_operator" > + [(match_operand:SI 1 "s_register_operand" "r") > + (match_operand:SI 2 "arm_rhs_operand" "rM")])) > + (match_operand:SI 3 "s_register_operand" "r")) > + (const_int 0))) > + (clobber (match_scratch:SI 4 "=3Dr"))] > + "TARGET_32BIT" > + "bic%.%?\\t%4, %3, %1%S0" > + [(set_attr "predicable" "yes") > + (set_attr "conds" "set") > + (set_attr "shift" "1") > + (set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "") > + (const_string "logic_shift_imm") > + (const_string "logic_shift_reg")))] > +) Since this is a predicable instruction and has a 32-bit encoding you should also set the 'predicable_short_it' attribute to 'no' to prevent GCC from trying to put it inside an IT block when compiling for ARMv8-A. > > + > +(define_insn "andsi_not_shiftsi_si_scc" > + [(parallel [(set (reg:CC_NOOV CC_REGNUM) > + (compare:CC_NOOV > + (and:SI (not:SI (match_operator:SI 0 "shift_operator" > + [(match_operand:SI 1 "s_register_operand" "r") > + (match_operand:SI 2 "arm_rhs_operand" "rM")])) > + (match_operand:SI 3 "s_register_operand" "r")) > + (const_int 0))) > + (set (match_operand:SI 4 "s_register_operand" "=3Dr") > + (and:SI (not:SI (match_op_dup 0 > + [(match_dup 1) > + (match_dup 2)])) > + (match_dup 3)))])] > + "TARGET_32BIT" > + "bic%.%?\\t%4, %3, %1%S0" > + [(set_attr "predicable" "yes") > + (set_attr "conds" "set") > + (set_attr "shift" "1") > + (set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "") > + (const_string "logic_shift_imm") > + (const_string "logic_shift_reg")))] same comment about predicable_short_it. Cheers, Kyrill > > +) > + > (define_insn "*andsi_notsi_si_compare0" > [(set (reg:CC_NOOV CC_REGNUM) > (compare:CC_NOOV