From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 30483 invoked by alias); 13 Nov 2013 16:09:45 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 30474 invoked by uid 89); 13 Nov 2013 16:09:44 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=1.8 required=5.0 tests=AWL,BAYES_95,KAM_STOCKGEN,RDNS_NONE,SPF_PASS,URIBL_BLOCKED autolearn=no version=3.3.2 X-HELO: service87.mimecast.com Received: from Unknown (HELO service87.mimecast.com) (91.220.42.44) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 13 Nov 2013 16:09:43 +0000 Received: from cam-owa1.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.21]) by service87.mimecast.com; Wed, 13 Nov 2013 16:09:34 +0000 Received: from E103005 ([10.1.255.212]) by cam-owa1.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Wed, 13 Nov 2013 16:09:32 +0000 From: "Joey Ye" To: "Richard Earnshaw" Cc: References: <000001cedf74$bd1bf710$3753e530$@arm.com> <528207A5.9070702@arm.com> <000001cee038$2a027e80$7e077b80$@arm.com> <52834B21.5080305@arm.com> <000001cee05a$0b8dbd80$22a93880$@arm.com> <52835D38.4020309@arm.com> In-Reply-To: <52835D38.4020309@arm.com> Subject: RE: [patch] [arm] New option for PIC offset unfixed Date: Wed, 13 Nov 2013 17:23:00 -0000 Message-ID: <000101cee08a$ba5b5720$2f120560$@arm.com> MIME-Version: 1.0 X-MC-Unique: 113111316093404001 Content-Type: multipart/mixed; boundary="----=_NextPart_000_0002_01CEE0CD.C8810820" X-SW-Source: 2013-11/txt/msg01486.txt.bz2 This is a multipart message in MIME format. ------=_NextPart_000_0002_01CEE0CD.C8810820 Content-Type: text/plain; charset=WINDOWS-1252 Content-Transfer-Encoding: quoted-printable Content-length: 1033 This patch address all comments. Thanks, Joey > -----Original Message----- > From: Richard Earnshaw > Sent: Wednesday, November 13, 2013 19:07 > To: Joey Ye > Cc: gcc-patches@gcc.gnu.org > Subject: Re: [patch] [arm] New option for PIC offset unfixed >=20 > On 13/11/13 10:20, Joey Ye wrote: > >>> +@item -mpic-data-is-text-relative > >>> > > +@opindex mpic-data-is-text-relative Assume that each data > >>> > > +segments are relative to text segment at load > > time. > >> > > >>> > > +Therefore, prevent PC relative and GOTOFF style relocations to > >>> > > +reference data. > >> > > >> > I think the sense of this sentence is now backwards. I'd also try > >> > to > > avoid > >> > GOTOFF in the user part of the manual. > > How about > > "Therefore, prevent addressing data with relocation types that doesn't > > apply in such circumstance." > > > >> > >=20 > No, that's still backwards. Remember, the option is now pic-data-is-text- > relative, so the option /permits/ addressing data using PC-relative operations. >=20 > R.= ------=_NextPart_000_0002_01CEE0CD.C8810820 Content-Type: text/plain; name=pic_data_text_rel-1114.patch.txt Content-Transfer-Encoding: quoted-printable Content-Disposition: attachment; filename="pic_data_text_rel-1114.patch.txt" Content-length: 2464 diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index 7757e86..5a95399 100644 --- a/gcc/config/arm/arm.c +++ b/gcc/config/arm/arm.c @@ -2504,6 +2504,11 @@ arm_option_override (void) arm_pic_register =3D pic_register; } =20 + if (arm_pic_data_is_text_relative < 0 && TARGET_VXWORKS_RTP) + arm_pic_data_is_text_relative =3D 0; + else + arm_pic_data_is_text_relative =3D 1; + /* Enable -mfix-cortex-m3-ldrd by default for Cortex-M3 cores. */ if (fix_cm3_ldrd =3D=3D 2) { @@ -6020,7 +6025,7 @@ legitimize_pic_address (rtx orig, enum machine_mode m= ode, rtx reg) || (GET_CODE (orig) =3D=3D SYMBOL_REF && SYMBOL_REF_LOCAL_P (orig))) && NEED_GOT_RELOC - && !TARGET_VXWORKS_RTP) + && arm_pic_data_is_text_relative) insn =3D arm_pic_static_addr (orig, reg); else { @@ -21498,7 +21503,7 @@ arm_assemble_integer (rtx x, unsigned int size, int= aligned_p) { /* See legitimize_pic_address for an explanation of the TARGET_VXWORKS_RTP check. */ - if (TARGET_VXWORKS_RTP + if (!arm_pic_data_is_text_relative || (GET_CODE (x) =3D=3D SYMBOL_REF && !SYMBOL_REF_LOCAL_P (x))) fputs ("(GOT)", asm_out_file); else diff --git a/gcc/config/arm/arm.opt b/gcc/config/arm/arm.opt index 9b74038..adac749 100644 --- a/gcc/config/arm/arm.opt +++ b/gcc/config/arm/arm.opt @@ -158,6 +158,10 @@ mlong-calls Target Report Mask(LONG_CALLS) Generate call insns as indirect calls, if necessary =20 +mpic-data-is-text-relative +Target Report Var(arm_pic_data_is_text_relative) Init(-1) +Assume data segments are relative to text segment. + mpic-register=3D Target RejectNegative Joined Var(arm_pic_register_string) Specify the register to be used for PIC addressing diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi index 863e518..fbe77e6 100644 --- a/gcc/doc/invoke.texi +++ b/gcc/doc/invoke.texi @@ -12120,6 +12120,12 @@ before execution begins. Specify the register to be used for PIC addressing. The default is R10 unless stack-checking is enabled, when R9 is used. =20 +@item -mpic-data-is-text-relative +@opindex mpic-data-is-text-relative +Assume that each data segments are relative to text segment at load time. +Therefore, it permits addressing data using PC-relative operations. +This option is on by default for targets other than VxWorks RTP. + @item -mpoke-function-name @opindex mpoke-function-name Write the name of each function into the text section, directly ------=_NextPart_000_0002_01CEE0CD.C8810820--