From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 18042 invoked by alias); 24 Nov 2014 05:11:19 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 17991 invoked by uid 89); 24 Nov 2014 05:11:18 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.8 required=5.0 tests=AWL,BAYES_00,SPF_PASS autolearn=ham version=3.3.2 X-HELO: service87.mimecast.com Received: from service87.mimecast.com (HELO service87.mimecast.com) (91.220.42.44) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Mon, 24 Nov 2014 05:11:16 +0000 Received: from cam-owa1.Emea.Arm.com (217.140.96.140 [217.140.96.140]) by service87.mimecast.com; Mon, 24 Nov 2014 05:11:14 +0000 Received: from shawin003 ([10.164.2.30]) by cam-owa1.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Mon, 24 Nov 2014 05:11:12 +0000 From: "Zhenqiang Chen" To: Cc: "Marcus Shawcroft" Subject: [PATCH, AARCH64] Fix ICE in CCMP (PR64015) Date: Mon, 24 Nov 2014 08:21:00 -0000 Message-ID: <000101d007a5$0d120f30$27362d90$@arm.com> MIME-Version: 1.0 X-MC-Unique: 114112405111400201 Content-Type: text/plain; charset=WINDOWS-1252 Content-Transfer-Encoding: quoted-printable X-IsSubscribed: yes X-SW-Source: 2014-11/txt/msg02969.txt.bz2 Hi, Expand pass always uses sign-extend to represent constant value. For the case in the patch, a 8-bit unsigned value "252" is represented as "-4", which pass the ccmn check. After mode conversion, "-4" becomes "252", which leads to mismatch. The patch adds another operand check after mode conversion. No make check regression with qemu. OK for trunk? Thanks! -Zhenqiang ChangeLog: 2014-11-24 Zhenqiang Chen PR target/64015 * config/aarch64/aarch64.c (aarch64_gen_ccmp_first): Recheck operand after mode conversion. (aarch64_gen_ccmp_next): Likewise. testsuite/ChangeLog: 2014-11-24 Zhenqiang Chen * gcc.target/aarch64/pr64015.c: New test. diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c index 1809513..203d095 100644 --- a/gcc/config/aarch64/aarch64.c +++ b/gcc/config/aarch64/aarch64.c @@ -10311,7 +10311,10 @@ aarch64_gen_ccmp_first (int code, rtx op0, rtx op1) if (!aarch64_plus_operand (op1, GET_MODE (op1))) op1 =3D force_reg (mode, op1); =20 - if (!aarch64_convert_mode (&op0, &op1, unsignedp)) + if (!aarch64_convert_mode (&op0, &op1, unsignedp) + /* Some negative value might be transformed into a positive one. + So need recheck here. */ + || !aarch64_plus_operand (op1, GET_MODE (op1))) return NULL_RTX; =20 mode =3D aarch64_code_to_ccmode ((enum rtx_code) code); @@ -10344,7 +10347,10 @@ aarch64_gen_ccmp_next (rtx prev, int cmp_code, rtx op0, rtx op1, int bit_code) || !aarch64_ccmp_operand (op1, GET_MODE (op1))) return NULL_RTX; =20 - if (!aarch64_convert_mode (&op0, &op1, unsignedp)) + if (!aarch64_convert_mode (&op0, &op1, unsignedp) + /* Some negative value might be transformed into a positive one. + So need recheck here. */ + || !aarch64_ccmp_operand (op1, GET_MODE (op1))) return NULL_RTX; =20 mode =3D aarch64_code_to_ccmode ((enum rtx_code) cmp_code); diff --git a/gcc/testsuite/gcc.target/aarch64/pr64015.c b/gcc/testsuite/gcc.target/aarch64/pr64015.c new file mode 100644 index 0000000..eeed665 --- /dev/null +++ b/gcc/testsuite/gcc.target/aarch64/pr64015.c @@ -0,0 +1,7 @@ +/* { dg-do compile } */ +/* { dg-options " -O2 " } */ +int +test (unsigned short a, unsigned char b) +{ + return a > 0xfff2 && b > 252; +}