From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 39592 invoked by alias); 27 Feb 2015 14:29:43 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 39583 invoked by uid 89); 27 Feb 2015 14:29:42 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.8 required=5.0 tests=AWL,BAYES_00,SPF_PASS autolearn=ham version=3.3.2 X-HELO: service87.mimecast.com Received: from service87.mimecast.com (HELO service87.mimecast.com) (91.220.42.44) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Fri, 27 Feb 2015 14:29:41 +0000 Received: from cam-owa1.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) by service87.mimecast.com; Fri, 27 Feb 2015 14:29:38 +0000 Received: from E100706VM ([10.1.255.212]) by cam-owa1.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Fri, 27 Feb 2015 14:29:36 +0000 From: "Kyrill Tkachov" To: "Kyrylo Tkachov" , "GCC Patches" Cc: "Ramana Radhakrishnan" , "Richard Earnshaw" References: <54D0E6BF.8070804@arm.com> In-Reply-To: <54D0E6BF.8070804@arm.com> Subject: RE: [PATCH][ARM] PR target/64600 Fix another ICE with -mtune=xscale: properly sign-extend mask during constant splitting Date: Fri, 27 Feb 2015 14:30:00 -0000 Message-ID: <000201d05299$cd873ad0$6895b070$@arm.com> MIME-Version: 1.0 X-MC-Unique: 115022714293805401 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-IsSubscribed: yes X-SW-Source: 2015-02/txt/msg01706.txt.bz2 On 03/02/15 15:18, Kyrill Tkachov wrote: > Hi all, > > The ICE in this PR occurs when -mtune=3Dxscale triggers a particular path= =20 > through arm_gen_constant during expand > that creates a 0xfffff00f mask but for a 64-bit HOST_WIDE_INT doesn't=20 > sign extend it into > 0xfffffffffffff00f that signifies the required -4081. It leaves it as=20 > 0xfffff00f (4294963215) that breaks when > later combine tries to perform an SImode bitwise AND using the wide-int=20 > machinery. > > I think the correct approach here is to use trunc_int_for_mode that=20 > correctly sign-extends the constant so > that it is properly represented by a HOST_WIDE_INT for the required mode. > > Bootstrapped and tested arm-none-linux-gnueabihf with -mtune=3Dxscale in= =20 > BOOT_CFLAGS. > > The testcase triggers for -mcpu=3Dxscale and all slowmul targets because= =20 > they are the only ones that have the > constant_limit tune parameter set to anything >1 which is required to=20 > follow this particular path through > arm_split_constant. Also, the rtx costs can hide this ICE sometimes. > > Ok for trunk? > > Thanks, > Kyrill > > 2015-02-03 Kyrylo Tkachov > > PR target/64600 > * config/arm/arm.c (arm_gen_constant, AND case): Call > trunc_int_for_mode when constructing AND mask. > > 2015-02-03 Kyrylo Tkachov > > PR target/64600 > * gcc.target/arm/pr64600_1.c: New test. > arm-xscale-wide.patch > commit 52388a359dd65276bccfac499a2fd9e406fbe1a8 > Author: Kyrylo Tkachov > Date: Tue Jan 20 11:21:34 2015 +0000 > > [ARM] Fix ICE due to arm_gen_constant not sign_extending > > diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c > index db4834b..d0f3a52 100644 > --- a/gcc/config/arm/arm.c > +++ b/gcc/config/arm/arm.c > @@ -4709,19 +4709,20 @@ arm_gen_constant (enum rtx_code code, machine_mod= e mode, rtx cond, >=20=20 > if ((remainder | shift_mask) !=3D 0xffffffff) > { > + HOST_WIDE_INT new_val > + =3D trunc_int_for_mode (remainder | shift_mask, mode); Offlist, Richard mentioned that trunc_int_for_mode may pessimize codegen fo= r HImode values due to excessive setting of bits and using ARM_SIGN_EXTEND might be preferable. I've tried that and it does fix the ICE and goes through testing ok. Bootst= rap still ongoing. I didn't perform any code quality investigation. Richard, are there any par= ticular code sequences that you'd like us to investigate here? Thanks, Kyrill > > + > if (generate) > { > rtx new_src =3D subtargets ? gen_reg_rtx (mode) : target; > - insns =3D arm_gen_constant (AND, mode, cond, > - remainder | shift_mask, > + insns =3D arm_gen_constant (AND, SImode, cond, new_val, > new_src, source, subtargets, 1); > source =3D new_src; > } > else > { > rtx targ =3D subtargets ? NULL_RTX : target; > - insns =3D arm_gen_constant (AND, mode, cond, > - remainder | shift_mask, > + insns =3D arm_gen_constant (AND, mode, cond, new_val, > targ, source, subtargets, 0); > } > } > @@ -4744,12 +4745,13 @@ arm_gen_constant (enum rtx_code code, machine_mod= e mode, rtx cond, >=20=20 > if ((remainder | shift_mask) !=3D 0xffffffff) > { > + HOST_WIDE_INT new_val > + =3D trunc_int_for_mode (remainder | shift_mask, mode); > if (generate) > { > rtx new_src =3D subtargets ? gen_reg_rtx (mode) : target; >=20=20 > - insns =3D arm_gen_constant (AND, mode, cond, > - remainder | shift_mask, > + insns =3D arm_gen_constant (AND, mode, cond, new_val, > new_src, source, subtargets, 1); > source =3D new_src; > } > @@ -4757,8 +4759,7 @@ arm_gen_constant (enum rtx_code code, machine_mode = mode, rtx cond, > { > rtx targ =3D subtargets ? NULL_RTX : target; >=20=20 > - insns =3D arm_gen_constant (AND, mode, cond, > - remainder | shift_mask, > + insns =3D arm_gen_constant (AND, mode, cond, new_val, > targ, source, subtargets, 0); > } > } > diff --git a/gcc/testsuite/gcc.target/arm/pr64600_1.c b/gcc/testsuite/gcc= .target/arm/pr64600_1.c > new file mode 100644 > index 0000000..6ba3fa2 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/arm/pr64600_1.c > @@ -0,0 +1,15 @@ > +/* { dg-do compile } */ > +/* { dg-options "-O2 -mtune=3Dxscale" } */ > + > +typedef unsigned int speed_t; > +typedef unsigned int tcflag_t; > + > +struct termios { > + tcflag_t c_cflag; > +}; > + > +speed_t > +cfgetospeed (const struct termios *tp) > +{ > + return tp->c_cflag & 010017; > +}