From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 112134 invoked by alias); 3 Mar 2015 17:59:55 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 112122 invoked by uid 89); 3 Mar 2015 17:59:55 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=-1.8 required=5.0 tests=AWL,BAYES_00,SPF_PASS autolearn=ham version=3.3.2 X-HELO: service87.mimecast.com Received: from service87.mimecast.com (HELO service87.mimecast.com) (91.220.42.44) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 03 Mar 2015 17:59:53 +0000 Received: from cam-owa1.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.140]) by service87.mimecast.com; Tue, 03 Mar 2015 17:59:50 +0000 Received: from E100706VM ([10.1.255.212]) by cam-owa1.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Tue, 3 Mar 2015 17:59:48 +0000 From: "Kyrill Tkachov" To: "GCC Patches" Cc: "Ramana Radhakrishnan" , "Richard Earnshaw" References: <54D0E6BF.8070804@arm.com> <000201d05299$cd873ad0$6895b070$@arm.com> In-Reply-To: <000201d05299$cd873ad0$6895b070$@arm.com> Subject: RE: [PATCH][ARM] PR target/64600 Fix another ICE with -mtune=xscale: properly sign-extend mask during constant splitting Date: Tue, 03 Mar 2015 17:59:00 -0000 Message-ID: <000401d055db$d56f8a00$804e9e00$@arm.com> MIME-Version: 1.0 X-MC-Unique: 115030317595008101 Content-Type: multipart/mixed; boundary="----=_NextPart_000_0005_01D055DB.D571D3F0" X-IsSubscribed: yes X-SW-Source: 2015-03/txt/msg00158.txt.bz2 This is a multipart message in MIME format. ------=_NextPart_000_0005_01D055DB.D571D3F0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Content-length: 5560 > -----Original Message----- > From: Kyrylo Tkachov > Sent: 27 February 2015 14:30 > To: Kyrylo Tkachov; GCC Patches > Cc: Ramana Radhakrishnan; Richard Earnshaw > Subject: RE: [PATCH][ARM] PR target/64600 Fix another ICE with - > mtune=3Dxscale: properly sign-extend mask during constant splitting >=20 > On 03/02/15 15:18, Kyrill Tkachov wrote: > > Hi all, > > > > The ICE in this PR occurs when -mtune=3Dxscale triggers a particular > > path through arm_gen_constant during expand that creates a 0xfffff00f > > mask but for a 64-bit HOST_WIDE_INT doesn't sign extend it into > > 0xfffffffffffff00f that signifies the required -4081. It leaves it as > > 0xfffff00f (4294963215) that breaks when later combine tries to > > perform an SImode bitwise AND using the wide-int machinery. > > > > I think the correct approach here is to use trunc_int_for_mode that > > correctly sign-extends the constant so that it is properly represented > > by a HOST_WIDE_INT for the required mode. > > > > Bootstrapped and tested arm-none-linux-gnueabihf with -mtune=3Dxscale in > > BOOT_CFLAGS. > > > > The testcase triggers for -mcpu=3Dxscale and all slowmul targets because > > they are the only ones that have the constant_limit tune parameter set > > to anything >1 which is required to follow this particular path > > through arm_split_constant. Also, the rtx costs can hide this ICE > > sometimes. > > > > Ok for trunk? > > > > Thanks, > > Kyrill > > > > 2015-02-03 Kyrylo Tkachov > > > > PR target/64600 > > * config/arm/arm.c (arm_gen_constant, AND case): Call > > trunc_int_for_mode when constructing AND mask. > > > > 2015-02-03 Kyrylo Tkachov > > > > PR target/64600 > > * gcc.target/arm/pr64600_1.c: New test. > > arm-xscale-wide.patch > > commit 52388a359dd65276bccfac499a2fd9e406fbe1a8 > > Author: Kyrylo Tkachov > > Date: Tue Jan 20 11:21:34 2015 +0000 > > > > [ARM] Fix ICE due to arm_gen_constant not sign_extending > > > > diff --git a/gcc/config/arm/arm.c b/gcc/config/arm/arm.c index > > db4834b..d0f3a52 100644 > > --- a/gcc/config/arm/arm.c > > +++ b/gcc/config/arm/arm.c > > @@ -4709,19 +4709,20 @@ arm_gen_constant (enum rtx_code code, > > machine_mode mode, rtx cond, > > > > if ((remainder | shift_mask) !=3D 0xffffffff) > > { > > + HOST_WIDE_INT new_val > > + =3D trunc_int_for_mode (remainder | shift_mask, mode); >=20 > Offlist, Richard mentioned that trunc_int_for_mode may pessimize codegen > for HImode values due to excessive setting of bits and using > ARM_SIGN_EXTEND might be preferable. > I've tried that and it does fix the ICE and goes through testing ok. Boot= strap > still ongoing. > I didn't perform any code quality investigation. Richard, are there any > particular code sequences that you'd like us to investigate here? >=20 Here's the alternative version using ARM_SIGN_EXTEND if you want to have a= look. Thanks, Kyrill 2015-03-03 Kyrylo Tkachov PR target/64600 * config/arm/arm.c (arm_gen_constant, AND case): Use ARM_SIGN_EXTEND when constructing AND mask. 2015-03-03 Kyrylo Tkachov PR target/64600 * gcc.target/arm/pr64600_1.c: New test. > Thanks, > Kyrill >=20 > > > > + > > if (generate) > > { > > rtx new_src =3D subtargets ? gen_reg_rtx (mode) : target; > > - insns =3D arm_gen_constant (AND, mode, cond, > > - remainder | shift_mask, > > + insns =3D arm_gen_constant (AND, SImode, cond, new_val, > > new_src, source, subtargets, 1); > > source =3D new_src; > > } > > else > > { > > rtx targ =3D subtargets ? NULL_RTX : target; > > - insns =3D arm_gen_constant (AND, mode, cond, > > - remainder | shift_mask, > > + insns =3D arm_gen_constant (AND, mode, cond, new_val, > > targ, source, subtargets, 0); > > } > > } > > @@ -4744,12 +4745,13 @@ arm_gen_constant (enum rtx_code code, > > machine_mode mode, rtx cond, > > > > if ((remainder | shift_mask) !=3D 0xffffffff) > > { > > + HOST_WIDE_INT new_val > > + =3D trunc_int_for_mode (remainder | shift_mask, mode); > > if (generate) > > { > > rtx new_src =3D subtargets ? gen_reg_rtx (mode) : target; > > > > - insns =3D arm_gen_constant (AND, mode, cond, > > - remainder | shift_mask, > > + insns =3D arm_gen_constant (AND, mode, cond, new_val, > > new_src, source, subtargets, 1); > > source =3D new_src; > > } > > @@ -4757,8 +4759,7 @@ arm_gen_constant (enum rtx_code code, > machine_mode mode, rtx cond, > > { > > rtx targ =3D subtargets ? NULL_RTX : target; > > > > - insns =3D arm_gen_constant (AND, mode, cond, > > - remainder | shift_mask, > > + insns =3D arm_gen_constant (AND, mode, cond, new_val, > > targ, source, subtargets, 0); > > } > > } > > diff --git a/gcc/testsuite/gcc.target/arm/pr64600_1.c > > b/gcc/testsuite/gcc.target/arm/pr64600_1.c > > new file mode 100644 > > index 0000000..6ba3fa2 > > --- /dev/null > > +++ b/gcc/testsuite/gcc.target/arm/pr64600_1.c > > @@ -0,0 +1,15 @@ > > +/* { dg-do compile } */ > > +/* { dg-options "-O2 -mtune=3Dxscale" } */ > > + > > +typedef unsigned int speed_t; > > +typedef unsigned int tcflag_t; > > + > > +struct termios { > > + tcflag_t c_cflag; > > +}; > > + > > +speed_t > > +cfgetospeed (const struct termios *tp) { > > + return tp->c_cflag & 010017; > > +} >=20 ------=_NextPart_000_0005_01D055DB.D571D3F0 Content-Transfer-Encoding: base64 Content-Type: application/octet-stream; name="arm-sign-extend-2.patch" Content-Disposition: attachment; filename="arm-sign-extend-2.patch" Content-length: 3372 Y29tbWl0IGQwMDIzZjQ3MmU4MTQzOTUxYWVkZDRiMTg4MGQ2NDg2Nzg3MzMx YjEKQXV0aG9yOiBLeXJ5bG8gVGthY2hvdiA8a3lyeWxvLnRrYWNob3ZAYXJt LmNvbT4KRGF0ZTogICBNb24gSmFuIDI2IDE2OjA2OjAyIDIwMTUgKzAwMDAK CiAgICBbQVJNXSBGaXggSUNFIGR1ZSB0byBhcm1fZ2VuX2NvbnN0YW50IG5v dCBzaWduX2V4dGVuZGluZwoKZGlmZiAtLWdpdCBhL2djYy9jb25maWcvYXJt L2FybS5jIGIvZ2NjL2NvbmZpZy9hcm0vYXJtLmMKaW5kZXggMmQzYThjNC4u NWIwODJkNiAxMDA2NDQKLS0tIGEvZ2NjL2NvbmZpZy9hcm0vYXJtLmMKKysr IGIvZ2NjL2NvbmZpZy9hcm0vYXJtLmMKQEAgLTQ1NzksMTkgKzQ1NzksMjAg QEAgYXJtX2dlbl9jb25zdGFudCAoZW51bSBydHhfY29kZSBjb2RlLCBtYWNo aW5lX21vZGUgbW9kZSwgcnR4IGNvbmQsCiAKIAkgIGlmICgocmVtYWluZGVy IHwgc2hpZnRfbWFzaykgIT0gMHhmZmZmZmZmZikKIAkgICAgeworCSAgICAg IEhPU1RfV0lERV9JTlQgbmV3X3ZhbAorCSAgICAgICAgPSBBUk1fU0lHTl9F WFRFTkQgKHJlbWFpbmRlciB8IHNoaWZ0X21hc2spOworCiAJICAgICAgaWYg KGdlbmVyYXRlKQogCQl7CiAJCSAgcnR4IG5ld19zcmMgPSBzdWJ0YXJnZXRz ID8gZ2VuX3JlZ19ydHggKG1vZGUpIDogdGFyZ2V0OwotCQkgIGluc25zID0g YXJtX2dlbl9jb25zdGFudCAoQU5ELCBtb2RlLCBjb25kLAotCQkJCQkgICAg cmVtYWluZGVyIHwgc2hpZnRfbWFzaywKKwkJICBpbnNucyA9IGFybV9nZW5f Y29uc3RhbnQgKEFORCwgU0ltb2RlLCBjb25kLCBuZXdfdmFsLAogCQkJCQkg ICAgbmV3X3NyYywgc291cmNlLCBzdWJ0YXJnZXRzLCAxKTsKIAkJICBzb3Vy Y2UgPSBuZXdfc3JjOwogCQl9CiAJICAgICAgZWxzZQogCQl7CiAJCSAgcnR4 IHRhcmcgPSBzdWJ0YXJnZXRzID8gTlVMTF9SVFggOiB0YXJnZXQ7Ci0JCSAg aW5zbnMgPSBhcm1fZ2VuX2NvbnN0YW50IChBTkQsIG1vZGUsIGNvbmQsCi0J CQkJCSAgICByZW1haW5kZXIgfCBzaGlmdF9tYXNrLAorCQkgIGluc25zID0g YXJtX2dlbl9jb25zdGFudCAoQU5ELCBtb2RlLCBjb25kLCBuZXdfdmFsLAog CQkJCQkgICAgdGFyZywgc291cmNlLCBzdWJ0YXJnZXRzLCAwKTsKIAkJfQog CSAgICB9CkBAIC00NjE0LDEyICs0NjE1LDEzIEBAIGFybV9nZW5fY29uc3Rh bnQgKGVudW0gcnR4X2NvZGUgY29kZSwgbWFjaGluZV9tb2RlIG1vZGUsIHJ0 eCBjb25kLAogCiAJICBpZiAoKHJlbWFpbmRlciB8IHNoaWZ0X21hc2spICE9 IDB4ZmZmZmZmZmYpCiAJICAgIHsKKwkgICAgICBIT1NUX1dJREVfSU5UIG5l d192YWwKKwkgICAgICAgID0gQVJNX1NJR05fRVhURU5EIChyZW1haW5kZXIg fCBzaGlmdF9tYXNrKTsKIAkgICAgICBpZiAoZ2VuZXJhdGUpCiAJCXsKIAkJ ICBydHggbmV3X3NyYyA9IHN1YnRhcmdldHMgPyBnZW5fcmVnX3J0eCAobW9k ZSkgOiB0YXJnZXQ7CiAKLQkJICBpbnNucyA9IGFybV9nZW5fY29uc3RhbnQg KEFORCwgbW9kZSwgY29uZCwKLQkJCQkJICAgIHJlbWFpbmRlciB8IHNoaWZ0 X21hc2ssCisJCSAgaW5zbnMgPSBhcm1fZ2VuX2NvbnN0YW50IChBTkQsIG1v ZGUsIGNvbmQsIG5ld192YWwsCiAJCQkJCSAgICBuZXdfc3JjLCBzb3VyY2Us IHN1YnRhcmdldHMsIDEpOwogCQkgIHNvdXJjZSA9IG5ld19zcmM7CiAJCX0K QEAgLTQ2MjcsOCArNDYyOSw3IEBAIGFybV9nZW5fY29uc3RhbnQgKGVudW0g cnR4X2NvZGUgY29kZSwgbWFjaGluZV9tb2RlIG1vZGUsIHJ0eCBjb25kLAog CQl7CiAJCSAgcnR4IHRhcmcgPSBzdWJ0YXJnZXRzID8gTlVMTF9SVFggOiB0 YXJnZXQ7CiAKLQkJICBpbnNucyA9IGFybV9nZW5fY29uc3RhbnQgKEFORCwg bW9kZSwgY29uZCwKLQkJCQkJICAgIHJlbWFpbmRlciB8IHNoaWZ0X21hc2ss CisJCSAgaW5zbnMgPSBhcm1fZ2VuX2NvbnN0YW50IChBTkQsIG1vZGUsIGNv bmQsIG5ld192YWwsCiAJCQkJCSAgICB0YXJnLCBzb3VyY2UsIHN1YnRhcmdl dHMsIDApOwogCQl9CiAJICAgIH0KZGlmZiAtLWdpdCBhL2djYy90ZXN0c3Vp dGUvZ2NjLnRhcmdldC9hcm0vcHI2NDYwMF8xLmMgYi9nY2MvdGVzdHN1aXRl L2djYy50YXJnZXQvYXJtL3ByNjQ2MDBfMS5jCm5ldyBmaWxlIG1vZGUgMTAw NjQ0CmluZGV4IDAwMDAwMDAuLjZiYTNmYTIKLS0tIC9kZXYvbnVsbAorKysg Yi9nY2MvdGVzdHN1aXRlL2djYy50YXJnZXQvYXJtL3ByNjQ2MDBfMS5jCkBA IC0wLDAgKzEsMTUgQEAKKy8qIHsgZGctZG8gY29tcGlsZSB9ICovCisvKiB7 IGRnLW9wdGlvbnMgIi1PMiAtbXR1bmU9eHNjYWxlIiB9ICovCisKK3R5cGVk ZWYgdW5zaWduZWQgaW50IHNwZWVkX3Q7Cit0eXBlZGVmIHVuc2lnbmVkIGlu dCB0Y2ZsYWdfdDsKKworc3RydWN0IHRlcm1pb3MgeworIHRjZmxhZ190IGNf Y2ZsYWc7Cit9OworCitzcGVlZF90CitjZmdldG9zcGVlZCAoY29uc3Qgc3Ry dWN0IHRlcm1pb3MgKnRwKQoreworICByZXR1cm4gdHAtPmNfY2ZsYWcgJiAw MTAwMTc7Cit9Cg== ------=_NextPart_000_0005_01D055DB.D571D3F0--