[PATCH 2/4 v2][AArch64] Add support for FCCMP

[PATCH 2/4 v2][AArch64] Add support for FCCMP

[Wilco Dijkstra]

(v2 version removes 4 enums)

This patch adds support for FCCMP. This is trivial with the new CCMP
representation - remove the restriction of FP in ccmp.c and add FCCMP
patterns. Add a test to ensure FCCMP/FCCMPE are emitted as expected.

OK for commit?

ChangeLog:
2015-11-18  Wilco Dijkstra  <wdijkstr@arm.com>

	* gcc/ccmp.c (ccmp_candidate_p): Remove integer-only restriction.
	* gcc/config/aarch64/aarch64.md (fccmp<mode>): New pattern.
	(fccmpe<mode>): Likewise.
	(fcmp): Rename to fcmp and globalize pattern.
	(fcmpe): Likewise.
	* gcc/config/aarch64/aarch64.c (aarch64_gen_ccmp_first): Add FP
support.
	(aarch64_gen_ccmp_next): Add FP support.

gcc/testsuite/
	* gcc.target/aarch64/ccmp_1.c: New testcase.


---
 gcc/ccmp.c                                |  6 ---
 gcc/config/aarch64/aarch64.c              | 24 +++++++++
 gcc/config/aarch64/aarch64.md             | 34 ++++++++++++-
 gcc/testsuite/gcc.target/aarch64/ccmp_1.c | 84
+++++++++++++++++++++++++++++++
 4 files changed, 140 insertions(+), 8 deletions(-)
 create mode 100644 gcc/testsuite/gcc.target/aarch64/ccmp_1.c

diff --git a/gcc/ccmp.c b/gcc/ccmp.c
index 58ac126..3698a7d 100644
--- a/gcc/ccmp.c
+++ b/gcc/ccmp.c
@@ -112,12 +112,6 @@ ccmp_candidate_p (gimple *g)
       || gimple_bb (gs0) != gimple_bb (g))
     return false;
 
-  if (!(INTEGRAL_TYPE_P (TREE_TYPE (gimple_assign_rhs1 (gs0)))
-       || POINTER_TYPE_P (TREE_TYPE (gimple_assign_rhs1 (gs0))))
-      || !(INTEGRAL_TYPE_P (TREE_TYPE (gimple_assign_rhs1 (gs1)))
-	   || POINTER_TYPE_P (TREE_TYPE (gimple_assign_rhs1 (gs1)))))
-    return false;
-
   tcode0 = gimple_assign_rhs_code (gs0);
   tcode1 = gimple_assign_rhs_code (gs1);
   if (TREE_CODE_CLASS (tcode0) == tcc_comparison
diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
index c8bee3b..db4d190 100644
--- a/gcc/config/aarch64/aarch64.c
+++ b/gcc/config/aarch64/aarch64.c
@@ -12398,6 +12398,18 @@ aarch64_gen_ccmp_first (rtx *prep_seq, rtx
*gen_seq,
       icode = CODE_FOR_cmpdi;
       break;
 
+    case SFmode:
+      cmp_mode = SFmode;
+      cc_mode = aarch64_select_cc_mode ((rtx_code) code, op0, op1);
+      icode = cc_mode == CCFPEmode ? CODE_FOR_fcmpesf : CODE_FOR_fcmpsf;
+      break;
+
+    case DFmode:
+      cmp_mode = DFmode;
+      cc_mode = aarch64_select_cc_mode ((rtx_code) code, op0, op1);
+      icode = cc_mode == CCFPEmode ? CODE_FOR_fcmpedf : CODE_FOR_fcmpdf;
+      break;
+
     default:
       end_sequence ();
       return NULL_RTX;
@@ -12461,6 +12473,18 @@ aarch64_gen_ccmp_next (rtx *prep_seq, rtx *gen_seq,
rtx prev, int cmp_code,
       icode = CODE_FOR_ccmpdi;
       break;
 
+    case SFmode:
+      cmp_mode = SFmode;
+      cc_mode = aarch64_select_cc_mode ((rtx_code) cmp_code, op0, op1);
+      icode = cc_mode == CCFPEmode ? CODE_FOR_fccmpesf : CODE_FOR_fccmpsf;
+      break;
+
+    case DFmode:
+      cmp_mode = DFmode;
+      cc_mode = aarch64_select_cc_mode ((rtx_code) cmp_code, op0, op1);
+      icode = cc_mode == CCFPEmode ? CODE_FOR_fccmpedf : CODE_FOR_fccmpdf;
+      break;
+
     default:
       end_sequence ();
       return NULL_RTX;
diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index fab65c6..7d728b5 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -279,6 +279,36 @@
   [(set_attr "type" "alus_sreg,alus_imm,alus_imm")]
 )
 
+(define_insn "fccmp<mode>"
+  [(set (match_operand:CCFP 1 "cc_register" "")
+	(if_then_else:CCFP
+	  (match_operator 4 "aarch64_comparison_operator"
+	   [(match_operand 0 "cc_register" "")
+	    (const_int 0)])
+	  (compare:CCFP
+	    (match_operand:GPF 2 "register_operand" "w")
+	    (match_operand:GPF 3 "register_operand" "w"))
+	  (match_operand 5 "immediate_operand")))]
+  "TARGET_FLOAT"
+  "fccmp\\t%<s>2, %<s>3, %k5, %m4"
+  [(set_attr "type" "fcmp<s>")]
+)
+
+(define_insn "fccmpe<mode>"
+  [(set (match_operand:CCFPE 1 "cc_register" "")
+	 (if_then_else:CCFPE
+	  (match_operator 4 "aarch64_comparison_operator"
+	   [(match_operand 0 "cc_register" "")
+	  (const_int 0)])
+	   (compare:CCFPE
+	    (match_operand:GPF 2 "register_operand" "w")
+	    (match_operand:GPF 3 "register_operand" "w"))
+	  (match_operand 5 "immediate_operand")))]
+  "TARGET_FLOAT"
+  "fccmpe\\t%<s>2, %<s>3, %k5, %m4"
+  [(set_attr "type" "fcmp<s>")]
+)
+
 ;; Expansion of signed mod by a power of 2 using CSNEG.
 ;; For x0 % n where n is a power of 2 produce:
 ;; negs   x1, x0
@@ -2794,7 +2824,7 @@
   [(set_attr "type" "alus_sreg,alus_imm,alus_imm")]
 )
 
-(define_insn "*cmp<mode>"
+(define_insn "fcmp<mode>"
   [(set (reg:CCFP CC_REGNUM)
         (compare:CCFP (match_operand:GPF 0 "register_operand" "w,w")
 		      (match_operand:GPF 1 "aarch64_fp_compare_operand"
"Y,w")))]
@@ -2805,7 +2835,7 @@
   [(set_attr "type" "fcmp<s>")]
 )
 
-(define_insn "*cmpe<mode>"
+(define_insn "fcmpe<mode>"
   [(set (reg:CCFPE CC_REGNUM)
         (compare:CCFPE (match_operand:GPF 0 "register_operand" "w,w")
 		       (match_operand:GPF 1 "aarch64_fp_compare_operand"
"Y,w")))]
diff --git a/gcc/testsuite/gcc.target/aarch64/ccmp_1.c
b/gcc/testsuite/gcc.target/aarch64/ccmp_1.c
new file mode 100644
index 0000000..ef077e0
--- /dev/null
+++ b/gcc/testsuite/gcc.target/aarch64/ccmp_1.c
@@ -0,0 +1,84 @@
+/* { dg-do compile } */
+/* { dg-options "-O2" } */
+
+int
+f1 (int a)
+{
+  return a == 17 || a == 32;
+}
+
+int
+f2 (int a)
+{
+  return a == 33 || a == 18;
+}
+
+int
+f3 (int a, int b)
+{
+  return a == 19 && b == 34;
+}
+
+int
+f4 (int a, int b)
+{
+  return a == 35 && b == 20;
+}
+
+int
+f5 (int a)
+{
+  return a == 0 || a == 5;
+}
+
+int
+f6 (int a)
+{
+  return a == 6 || a == 0;
+}
+
+int
+f7 (int a, int b)
+{
+  return a == 0 && b == 7;
+}
+
+int
+f8 (int a, int b)
+{
+  return a == 9 && b == 0;
+}
+
+int
+f9 (float a, float b)
+{
+  return a < 0.0f && a > b;
+}
+
+int
+f10 (float a, float b)
+{
+  return a == b || b == 0.0f;
+}
+
+int
+f11 (double a, int b)
+{
+  return a < 0.0f && b == 30;
+}
+
+int
+f12 (double a, int b)
+{
+  return b == 31 || a == 0.0f;
+}
+
+int
+f13 (int a, int b)
+{
+  a += b;
+  return a == 3 || a == 0;
+}
+
+/* { dg-final { scan-assembler "fccmp\t" } } */
+/* { dg-final { scan-assembler "fccmpe\t" } } */
-- 
1.9.1

Re: [PATCH 2/4 v2][AArch64] Add support for FCCMP

[Evandro Menezes]

On 02/15/16 04:53, James Greenhalgh wrote:
> On Thu, Jan 21, 2016 at 04:55:40PM -0600, Evandro Menezes wrote:
>> Got it.
>>
>> Let me try this again:
>>
>>     Add support for the FCCMP insn types
>>
>>     2016-01-21  Evandro Menezes  <e.menezes@samsung.com>
>>
>>     gcc/
>>              * config/aarch64/aarch64.md (fccmp): Change insn type.
>>              (fccmpe): Likewise.
>>              * config/aarch64/thunderx.md (thunderx_fcmp): Add
>>     "fccmp{s,d}" types.
>>              * config/arm/cortex-a53.md (cortex_a53_fpalu): Likewise.
>>              * config/arm/cortex-a57.md (cortex_a57_fp_cmp): Likewise.
>>              * config/arm/xgene1.md (xgene1_fcmp): Likewise.
>>              * config/arm/exynos-m1.md (exynos_m1_fp_ccmp): New insn
>>     reservation.
>>              * config/arm/types.md (fccmps): Add new insn type.
>>              (fccmpd): Likewise.
>>
>>
> This is OK. Sorry to have left it waiting so long.
>
> Thanks,
> James
>
>
>>  From 14874dec3257c7b59aed4b7c610305f76bbbcf33 Mon Sep 17 00:00:00 2001
>> From: Evandro Menezes <e.menezes@samsung.com>
>> Date: Mon, 4 Jan 2016 18:44:30 -0600
>> Subject: [PATCH] Add support for the FCCMP insn types
>>
>> 2016-01-21  Evandro Menezes  <e.menezes@samsung.com>
>>
>> gcc/
>> 	* config/aarch64/aarch64.md (fccmp): Change insn type.
>> 	(fccmpe): Likewise.
>> 	* config/aarch64/thunderx.md (thunderx_fcmp): Add "fccmp{s,d}" types.
>> 	* config/arm/cortex-a53.md (cortex_a53_fpalu): Likewise.
>> 	* config/arm/cortex-a57.md (cortex_a57_fp_cmp): Likewise.
>> 	* config/arm/xgene1.md (xgene1_fcmp): Likewise.
>> 	* config/arm/exynos-m1.md (exynos_m1_fp_ccmp): New insn reservation.
>> 	* config/arm/types.md (fccmps): Add new insn type.
>> 	(fccmpd): Likewise.
>> ---
>>   gcc/config/aarch64/aarch64.md  | 4 ++--
>>   gcc/config/aarch64/thunderx.md | 2 +-
>>   gcc/config/arm/cortex-a53.md   | 4 ++--
>>   gcc/config/arm/cortex-a57.md   | 2 +-
>>   gcc/config/arm/exynos-m1.md    | 5 +++++
>>   gcc/config/arm/types.md        | 3 +++
>>   gcc/config/arm/xgene1.md       | 2 +-
>>   7 files changed, 15 insertions(+), 7 deletions(-)
>>
>> diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
>> index 2f543aa..032b342 100644
>> --- a/gcc/config/aarch64/aarch64.md
>> +++ b/gcc/config/aarch64/aarch64.md
>> @@ -301,7 +301,7 @@
>>   	  (match_operand 5 "immediate_operand")))]
>>     "TARGET_FLOAT"
>>     "fccmp\\t%<s>2, %<s>3, %k5, %m4"
>> -  [(set_attr "type" "fcmp<s>")]
>> +  [(set_attr "type" "fccmp<s>")]
>>   )
>>   
>>   (define_insn "fccmpe<mode>"
>> @@ -316,7 +316,7 @@
>>   	  (match_operand 5 "immediate_operand")))]
>>     "TARGET_FLOAT"
>>     "fccmpe\\t%<s>2, %<s>3, %k5, %m4"
>> -  [(set_attr "type" "fcmp<s>")]
>> +  [(set_attr "type" "fccmp<s>")]
>>   )
>>   
>>   ;; Expansion of signed mod by a power of 2 using CSNEG.
>> diff --git a/gcc/config/aarch64/thunderx.md b/gcc/config/aarch64/thunderx.md
>> index 922df39..058713a 100644
>> --- a/gcc/config/aarch64/thunderx.md
>> +++ b/gcc/config/aarch64/thunderx.md
>> @@ -156,7 +156,7 @@
>>   
>>   (define_insn_reservation "thunderx_fcmp" 3
>>     (and (eq_attr "tune" "thunderx")
>> -       (eq_attr "type" "fcmps,fcmpd"))
>> +       (eq_attr "type" "fcmps,fcmpd,fccmps,fccmpd"))
>>     "thunderx_pipe1")
>>   
>>   (define_insn_reservation "thunderx_fmul" 6
>> diff --git a/gcc/config/arm/cortex-a53.md b/gcc/config/arm/cortex-a53.md
>> index c1eeedb..fc60bc2 100644
>> --- a/gcc/config/arm/cortex-a53.md
>> +++ b/gcc/config/arm/cortex-a53.md
>> @@ -508,8 +508,8 @@
>>   (define_insn_reservation "cortex_a53_fpalu" 5
>>     (and (eq_attr "tune" "cortexa53")
>>   	(eq_attr "type" "ffariths, fadds, ffarithd, faddd, fmov,
>> -			f_cvt, fcmps, fcmpd, fcsel, f_rints, f_rintd,
>> -			f_minmaxs, f_minmaxd"))
>> +			f_cvt, fcmps, fcmpd, fccmps, fccmpd, fcsel,
>> +			f_rints, f_rintd, f_minmaxs, f_minmaxd"))
>>     "cortex_a53_slot_any,cortex_a53_fp_alu")
>>   
>>   (define_insn_reservation "cortex_a53_fconst" 3
>> diff --git a/gcc/config/arm/cortex-a57.md b/gcc/config/arm/cortex-a57.md
>> index 0d28951..f4c112c 100644
>> --- a/gcc/config/arm/cortex-a57.md
>> +++ b/gcc/config/arm/cortex-a57.md
>> @@ -716,7 +716,7 @@
>>   
>>   (define_insn_reservation "cortex_a57_fp_cmp" 7
>>     (and (eq_attr "tune" "cortexa57")
>> -       (eq_attr "type" "fcmps,fcmpd"))
>> +       (eq_attr "type" "fcmps,fcmpd,fccmps,fccmpd"))
>>     "ca57_cx2")
>>   
>>   (define_insn_reservation "cortex_a57_fp_arith" 4
>> diff --git a/gcc/config/arm/exynos-m1.md b/gcc/config/arm/exynos-m1.md
>> index 0448073..973c8a9 100644
>> --- a/gcc/config/arm/exynos-m1.md
>> +++ b/gcc/config/arm/exynos-m1.md
>> @@ -823,6 +823,11 @@
>>          (eq_attr "type" "fcmps, fcmpd"))
>>     "em1_nmisc")
>>   
>> +(define_insn_reservation "exynos_m1_fp_ccmp" 7
>> +  (and (eq_attr "tune" "exynosm1")
>> +       (eq_attr "type" "fccmps, fccmpd"))
>> +  "em1_st, em1_nmisc")
>> +
>>   (define_insn_reservation "exynos_m1_fp_sel" 4
>>     (and (eq_attr "tune" "exynosm1")
>>          (eq_attr "type" "fcsel"))
>> diff --git a/gcc/config/arm/types.md b/gcc/config/arm/types.md
>> index 321ff89..25f79b4 100644
>> --- a/gcc/config/arm/types.md
>> +++ b/gcc/config/arm/types.md
>> @@ -70,6 +70,7 @@
>>   ; f_rint[d,s]        double/single floating point rount to integral.
>>   ; f_store[d,s]       double/single store to memory.  Used for VFP unit.
>>   ; fadd[d,s]          double/single floating-point scalar addition.
>> +; fccmp[d,s]         From ARMv8-A: floating-point conditional compare.
>>   ; fcmp[d,s]          double/single floating-point compare.
>>   ; fconst[d,s]        double/single load immediate.
>>   ; fcsel              From ARMv8-A: Floating-point conditional select.
>> @@ -582,6 +583,8 @@
>>     f_stores,\
>>     faddd,\
>>     fadds,\
>> +  fccmpd,\
>> +  fccmps,\
>>     fcmpd,\
>>     fcmps,\
>>     fconstd,\
>> diff --git a/gcc/config/arm/xgene1.md b/gcc/config/arm/xgene1.md
>> index 8dfd8a1..b7aeac6 100644
>> --- a/gcc/config/arm/xgene1.md
>> +++ b/gcc/config/arm/xgene1.md
>> @@ -154,7 +154,7 @@
>>   
>>   (define_insn_reservation "xgene1_fcmp" 10
>>     (and (eq_attr "tune" "xgene1")
>> -       (eq_attr "type" "fcmpd,fcmps"))
>> +       (eq_attr "type" "fcmpd,fcmps,fccmpd,fccmps"))
>>     "xgene1_decode1op,xgene1_fsu+xgene1_fcmp*3")
>>   
>>   (define_insn_reservation "xgene1_fcsel" 3
>> -- 
>> 2.6.3
>>
>
>

Committed as r233432.

Thank you,

-- 
Evandro Menezes

Re: [PATCH 2/4 v2][AArch64] Add support for FCCMP

[James Greenhalgh]

On Thu, Jan 21, 2016 at 04:55:40PM -0600, Evandro Menezes wrote:
> 
> Got it.
> 
> Let me try this again:
> 
>    Add support for the FCCMP insn types
> 
>    2016-01-21  Evandro Menezes  <e.menezes@samsung.com>
> 
>    gcc/
>             * config/aarch64/aarch64.md (fccmp): Change insn type.
>             (fccmpe): Likewise.
>             * config/aarch64/thunderx.md (thunderx_fcmp): Add
>    "fccmp{s,d}" types.
>             * config/arm/cortex-a53.md (cortex_a53_fpalu): Likewise.
>             * config/arm/cortex-a57.md (cortex_a57_fp_cmp): Likewise.
>             * config/arm/xgene1.md (xgene1_fcmp): Likewise.
>             * config/arm/exynos-m1.md (exynos_m1_fp_ccmp): New insn
>    reservation.
>             * config/arm/types.md (fccmps): Add new insn type.
>             (fccmpd): Likewise.
> 
> 

This is OK. Sorry to have left it waiting so long.

Thanks,
James


> From 14874dec3257c7b59aed4b7c610305f76bbbcf33 Mon Sep 17 00:00:00 2001
> From: Evandro Menezes <e.menezes@samsung.com>
> Date: Mon, 4 Jan 2016 18:44:30 -0600
> Subject: [PATCH] Add support for the FCCMP insn types
> 
> 2016-01-21  Evandro Menezes  <e.menezes@samsung.com>
> 
> gcc/
> 	* config/aarch64/aarch64.md (fccmp): Change insn type.
> 	(fccmpe): Likewise.
> 	* config/aarch64/thunderx.md (thunderx_fcmp): Add "fccmp{s,d}" types.
> 	* config/arm/cortex-a53.md (cortex_a53_fpalu): Likewise.
> 	* config/arm/cortex-a57.md (cortex_a57_fp_cmp): Likewise.
> 	* config/arm/xgene1.md (xgene1_fcmp): Likewise.
> 	* config/arm/exynos-m1.md (exynos_m1_fp_ccmp): New insn reservation.
> 	* config/arm/types.md (fccmps): Add new insn type.
> 	(fccmpd): Likewise.
> ---
>  gcc/config/aarch64/aarch64.md  | 4 ++--
>  gcc/config/aarch64/thunderx.md | 2 +-
>  gcc/config/arm/cortex-a53.md   | 4 ++--
>  gcc/config/arm/cortex-a57.md   | 2 +-
>  gcc/config/arm/exynos-m1.md    | 5 +++++
>  gcc/config/arm/types.md        | 3 +++
>  gcc/config/arm/xgene1.md       | 2 +-
>  7 files changed, 15 insertions(+), 7 deletions(-)
> 
> diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
> index 2f543aa..032b342 100644
> --- a/gcc/config/aarch64/aarch64.md
> +++ b/gcc/config/aarch64/aarch64.md
> @@ -301,7 +301,7 @@
>  	  (match_operand 5 "immediate_operand")))]
>    "TARGET_FLOAT"
>    "fccmp\\t%<s>2, %<s>3, %k5, %m4"
> -  [(set_attr "type" "fcmp<s>")]
> +  [(set_attr "type" "fccmp<s>")]
>  )
>  
>  (define_insn "fccmpe<mode>"
> @@ -316,7 +316,7 @@
>  	  (match_operand 5 "immediate_operand")))]
>    "TARGET_FLOAT"
>    "fccmpe\\t%<s>2, %<s>3, %k5, %m4"
> -  [(set_attr "type" "fcmp<s>")]
> +  [(set_attr "type" "fccmp<s>")]
>  )
>  
>  ;; Expansion of signed mod by a power of 2 using CSNEG.
> diff --git a/gcc/config/aarch64/thunderx.md b/gcc/config/aarch64/thunderx.md
> index 922df39..058713a 100644
> --- a/gcc/config/aarch64/thunderx.md
> +++ b/gcc/config/aarch64/thunderx.md
> @@ -156,7 +156,7 @@
>  
>  (define_insn_reservation "thunderx_fcmp" 3
>    (and (eq_attr "tune" "thunderx")
> -       (eq_attr "type" "fcmps,fcmpd"))
> +       (eq_attr "type" "fcmps,fcmpd,fccmps,fccmpd"))
>    "thunderx_pipe1")
>  
>  (define_insn_reservation "thunderx_fmul" 6
> diff --git a/gcc/config/arm/cortex-a53.md b/gcc/config/arm/cortex-a53.md
> index c1eeedb..fc60bc2 100644
> --- a/gcc/config/arm/cortex-a53.md
> +++ b/gcc/config/arm/cortex-a53.md
> @@ -508,8 +508,8 @@
>  (define_insn_reservation "cortex_a53_fpalu" 5
>    (and (eq_attr "tune" "cortexa53")
>  	(eq_attr "type" "ffariths, fadds, ffarithd, faddd, fmov,
> -			f_cvt, fcmps, fcmpd, fcsel, f_rints, f_rintd,
> -			f_minmaxs, f_minmaxd"))
> +			f_cvt, fcmps, fcmpd, fccmps, fccmpd, fcsel,
> +			f_rints, f_rintd, f_minmaxs, f_minmaxd"))
>    "cortex_a53_slot_any,cortex_a53_fp_alu")
>  
>  (define_insn_reservation "cortex_a53_fconst" 3
> diff --git a/gcc/config/arm/cortex-a57.md b/gcc/config/arm/cortex-a57.md
> index 0d28951..f4c112c 100644
> --- a/gcc/config/arm/cortex-a57.md
> +++ b/gcc/config/arm/cortex-a57.md
> @@ -716,7 +716,7 @@
>  
>  (define_insn_reservation "cortex_a57_fp_cmp" 7
>    (and (eq_attr "tune" "cortexa57")
> -       (eq_attr "type" "fcmps,fcmpd"))
> +       (eq_attr "type" "fcmps,fcmpd,fccmps,fccmpd"))
>    "ca57_cx2")
>  
>  (define_insn_reservation "cortex_a57_fp_arith" 4
> diff --git a/gcc/config/arm/exynos-m1.md b/gcc/config/arm/exynos-m1.md
> index 0448073..973c8a9 100644
> --- a/gcc/config/arm/exynos-m1.md
> +++ b/gcc/config/arm/exynos-m1.md
> @@ -823,6 +823,11 @@
>         (eq_attr "type" "fcmps, fcmpd"))
>    "em1_nmisc")
>  
> +(define_insn_reservation "exynos_m1_fp_ccmp" 7
> +  (and (eq_attr "tune" "exynosm1")
> +       (eq_attr "type" "fccmps, fccmpd"))
> +  "em1_st, em1_nmisc")
> +
>  (define_insn_reservation "exynos_m1_fp_sel" 4
>    (and (eq_attr "tune" "exynosm1")
>         (eq_attr "type" "fcsel"))
> diff --git a/gcc/config/arm/types.md b/gcc/config/arm/types.md
> index 321ff89..25f79b4 100644
> --- a/gcc/config/arm/types.md
> +++ b/gcc/config/arm/types.md
> @@ -70,6 +70,7 @@
>  ; f_rint[d,s]        double/single floating point rount to integral.
>  ; f_store[d,s]       double/single store to memory.  Used for VFP unit.
>  ; fadd[d,s]          double/single floating-point scalar addition.
> +; fccmp[d,s]         From ARMv8-A: floating-point conditional compare.
>  ; fcmp[d,s]          double/single floating-point compare.
>  ; fconst[d,s]        double/single load immediate.
>  ; fcsel              From ARMv8-A: Floating-point conditional select.
> @@ -582,6 +583,8 @@
>    f_stores,\
>    faddd,\
>    fadds,\
> +  fccmpd,\
> +  fccmps,\
>    fcmpd,\
>    fcmps,\
>    fconstd,\
> diff --git a/gcc/config/arm/xgene1.md b/gcc/config/arm/xgene1.md
> index 8dfd8a1..b7aeac6 100644
> --- a/gcc/config/arm/xgene1.md
> +++ b/gcc/config/arm/xgene1.md
> @@ -154,7 +154,7 @@
>  
>  (define_insn_reservation "xgene1_fcmp" 10
>    (and (eq_attr "tune" "xgene1")
> -       (eq_attr "type" "fcmpd,fcmps"))
> +       (eq_attr "type" "fcmpd,fcmps,fccmpd,fccmps"))
>    "xgene1_decode1op,xgene1_fsu+xgene1_fcmp*3")
>  
>  (define_insn_reservation "xgene1_fcsel" 3
> -- 
> 2.6.3
> 

Re: [PATCH 2/4 v2][AArch64] Add support for FCCMP

[Evandro Menezes]

On 01/21/16 16:55, Evandro Menezes wrote:
> On 01/21/16 16:07, James Greenhalgh wrote:
>> On Thu, Jan 21, 2016 at 01:58:31PM -0600, Evandro Menezes wrote:
>>> Hi, James.
>>>
>>> On 01/21/16 03:24, James Greenhalgh wrote:
>>>> On Wed, Jan 06, 2016 at 02:44:47PM -0600, Evandro Menezes wrote:
>>>>> On 01/06/2016 06:04 AM, Wilco Dijkstra wrote:
>>>>>>> Here's what I had in mind when I inquired about distinguishing 
>>>>>>> FCMP from
>>>>>>> FCCMP.  As you can see in the patch, Exynos is the only target that
>>>>>>> cares about it, but I wonder if ThunderX or Xgene would too.
>>>>>>>
>>>>>>> What do you think?
>>>>>> The new attributes look fine (I've got a similar outstanding 
>>>>>> change), however
>>>>>> please don't add them to non-AArch64 cores. We only need it for 
>>>>>> thunderx.md,
>>>>>> cortex-a53.md, cortex-a57.md, xgene1.md and exynos-m1.md.
>>>>>          Add support for the FCCMP insn types
>>>>>
>>>>>          2016-01-04  Evandro Menezes <e.menezes@samsung.com>
>>>>>
>>>>>          gcc/
>>>>>              * config/aarch64/aarch64.md (fccmp): Change insn type.
>>>>>              (fccmpe): Likewise.
>>>>>              * config/aarch64/thunderx.md (thunderx_fcmp): Add
>>>>>     "fccmp{s,d}" types.
>>>>>              * config/arm/cortex-a53.md (cortex_a53_fpalu): Likewise.
>>>>>              * config/arm/cortex-a57.md (cortex_a57_fp_cmp): 
>>>>> Likewise.
>>>>>              * config/arm/xgene1.md (xgene1_fcmp): Likewise.
>>>>>              * config/arm/exynos-m1.md (exynos_m1_fp_ccmp): New insn
>>>>>     reservation.
>>>>>              * config/arm/types.md (fccmps): Add new insn type.
>>>>>              (fccmpd): Likewise.
>>>>>
>>>>> Got it.  Here's an updated patch.  Again, assuming that your
>>>>> original patch is in place.  Perhaps you can build on it.
>>>> If we don't have any targets which care about the fccmps/fccmpd 
>>>> split in
>>>> the code base, do we really need it? Can we just follow the example of
>>>> fcsel?
>>> The Exynos M1 does care about the difference between FCMP and FCCMP,
>>> as can be seen in the patch.
>>> More explicitly:
>>>
>>>     (define_insn_reservation "exynos_m1_fp_cmp" 4
>>>        (and (eq_attr "tune" "exynosm1")
>>>             (eq_attr "type" "fcmps, fcmpd"))
>>>        "em1_nmisc")
>>>
>>>     (define_insn_reservation "exynos_m1_fp_ccmp" 7
>>>        (and (eq_attr "tune" "exynosm1")
>>>             (eq_attr "type" "fccmps, fccmpd"))
>>>        "em1_st, em1_nmisc")
>>>
>> I think I was unclear. Your exynos-m1 model cares about splitting 
>> fcmp[s/d]
>> and fccmp, but it doesn't care about splitting fccmp in to 
>> fccmps/fccmpd. It
>> is the split to fccmps/fccmpd that I think is unneccesary at this time.
>
> Indeed.  However, it seems to me that the jury is still out about the 
> {s,d} suffix, isn't it?  Otherwise, whatever others deem better.  I 
> myself am agnostic about it.
>
>>>>> diff --git a/gcc/config/arm/types.md b/gcc/config/arm/types.md
>>>>> index 321ff89..daf7162 100644
>>>>> --- a/gcc/config/arm/types.md
>>>>> +++ b/gcc/config/arm/types.md
>>>>> @@ -70,6 +70,7 @@
>>>>>   ; f_rint[d,s]        double/single floating point rount to 
>>>>> integral.
>>>>>   ; f_store[d,s]       double/single store to memory. Used for VFP 
>>>>> unit.
>>>>>   ; fadd[d,s]          double/single floating-point scalar addition.
>>>>> +; fccmp[d,s]         double/single floating-point conditional 
>>>>> compare.
>>>> Can we follow the convention fcsel uses of calling out "From ARMv8-A:"
>>>> for this type?
>>> I'm not sure I follow.  Though I didn't refer to the ISA spec, I
>>> used the description from it for the *fccmp* type.
>> Something like:
>>
>> ; fccmp    From ARMv8-A: floating point conditional compare.
>>
>> Just to capture that this instruction is only available for cores 
>> implementing
>> ARMv8-A.
>
>
> Got it.
>
> Let me try this again:
>
>    Add support for the FCCMP insn types
>
>    2016-01-21  Evandro Menezes  <e.menezes@samsung.com>
>
>    gcc/
>             * config/aarch64/aarch64.md (fccmp): Change insn type.
>             (fccmpe): Likewise.
>             * config/aarch64/thunderx.md (thunderx_fcmp): Add
>    "fccmp{s,d}" types.
>             * config/arm/cortex-a53.md (cortex_a53_fpalu): Likewise.
>             * config/arm/cortex-a57.md (cortex_a57_fp_cmp): Likewise.
>             * config/arm/xgene1.md (xgene1_fcmp): Likewise.
>             * config/arm/exynos-m1.md (exynos_m1_fp_ccmp): New insn
>    reservation.
>             * config/arm/types.md (fccmps): Add new insn type.
>             (fccmpd): Likewise.
>

*Ping*

-- 
Evandro Menezes

Re: [PATCH 2/4 v2][AArch64] Add support for FCCMP

[Evandro Menezes]

[-- Attachment #1: Type: text/plain, Size: 4379 bytes --]

On 01/21/16 16:07, James Greenhalgh wrote:
> On Thu, Jan 21, 2016 at 01:58:31PM -0600, Evandro Menezes wrote:
>> Hi, James.
>>
>> On 01/21/16 03:24, James Greenhalgh wrote:
>>> On Wed, Jan 06, 2016 at 02:44:47PM -0600, Evandro Menezes wrote:
>>>> On 01/06/2016 06:04 AM, Wilco Dijkstra wrote:
>>>>>> Here's what I had in mind when I inquired about distinguishing FCMP from
>>>>>> FCCMP.  As you can see in the patch, Exynos is the only target that
>>>>>> cares about it, but I wonder if ThunderX or Xgene would too.
>>>>>>
>>>>>> What do you think?
>>>>> The new attributes look fine (I've got a similar outstanding change), however
>>>>> please don't add them to non-AArch64 cores. We only need it for thunderx.md,
>>>>> cortex-a53.md, cortex-a57.md, xgene1.md and exynos-m1.md.
>>>>          Add support for the FCCMP insn types
>>>>
>>>>          2016-01-04  Evandro Menezes  <e.menezes@samsung.com>
>>>>
>>>>          gcc/
>>>>              * config/aarch64/aarch64.md (fccmp): Change insn type.
>>>>              (fccmpe): Likewise.
>>>>              * config/aarch64/thunderx.md (thunderx_fcmp): Add
>>>>     "fccmp{s,d}" types.
>>>>              * config/arm/cortex-a53.md (cortex_a53_fpalu): Likewise.
>>>>              * config/arm/cortex-a57.md (cortex_a57_fp_cmp): Likewise.
>>>>              * config/arm/xgene1.md (xgene1_fcmp): Likewise.
>>>>              * config/arm/exynos-m1.md (exynos_m1_fp_ccmp): New insn
>>>>     reservation.
>>>>              * config/arm/types.md (fccmps): Add new insn type.
>>>>              (fccmpd): Likewise.
>>>>
>>>> Got it.  Here's an updated patch.  Again, assuming that your
>>>> original patch is in place.  Perhaps you can build on it.
>>> If we don't have any targets which care about the fccmps/fccmpd split in
>>> the code base, do we really need it? Can we just follow the example of
>>> fcsel?
>> The Exynos M1 does care about the difference between FCMP and FCCMP,
>> as can be seen in the patch.
>> More explicitly:
>>
>>     (define_insn_reservation "exynos_m1_fp_cmp" 4
>>        (and (eq_attr "tune" "exynosm1")
>>             (eq_attr "type" "fcmps, fcmpd"))
>>        "em1_nmisc")
>>
>>     (define_insn_reservation "exynos_m1_fp_ccmp" 7
>>        (and (eq_attr "tune" "exynosm1")
>>             (eq_attr "type" "fccmps, fccmpd"))
>>        "em1_st, em1_nmisc")
>>
> I think I was unclear. Your exynos-m1 model cares about splitting fcmp[s/d]
> and fccmp, but it doesn't care about splitting fccmp in to fccmps/fccmpd. It
> is the split to fccmps/fccmpd that I think is unneccesary at this time.

Indeed.  However, it seems to me that the jury is still out about the 
{s,d} suffix, isn't it?  Otherwise, whatever others deem better.  I 
myself am agnostic about it.

>>>> diff --git a/gcc/config/arm/types.md b/gcc/config/arm/types.md
>>>> index 321ff89..daf7162 100644
>>>> --- a/gcc/config/arm/types.md
>>>> +++ b/gcc/config/arm/types.md
>>>> @@ -70,6 +70,7 @@
>>>>   ; f_rint[d,s]        double/single floating point rount to integral.
>>>>   ; f_store[d,s]       double/single store to memory.  Used for VFP unit.
>>>>   ; fadd[d,s]          double/single floating-point scalar addition.
>>>> +; fccmp[d,s]         double/single floating-point conditional compare.
>>> Can we follow the convention fcsel uses of calling out "From ARMv8-A:"
>>> for this type?
>> I'm not sure I follow.  Though I didn't refer to the ISA spec, I
>> used the description from it for the *fccmp* type.
> Something like:
>
> ; fccmp    From ARMv8-A: floating point conditional compare.
>
> Just to capture that this instruction is only available for cores implementing
> ARMv8-A.


Got it.

Let me try this again:

    Add support for the FCCMP insn types

    2016-01-21  Evandro Menezes  <e.menezes@samsung.com>

    gcc/
             * config/aarch64/aarch64.md (fccmp): Change insn type.
             (fccmpe): Likewise.
             * config/aarch64/thunderx.md (thunderx_fcmp): Add
    "fccmp{s,d}" types.
             * config/arm/cortex-a53.md (cortex_a53_fpalu): Likewise.
             * config/arm/cortex-a57.md (cortex_a57_fp_cmp): Likewise.
             * config/arm/xgene1.md (xgene1_fcmp): Likewise.
             * config/arm/exynos-m1.md (exynos_m1_fp_ccmp): New insn
    reservation.
             * config/arm/types.md (fccmps): Add new insn type.
             (fccmpd): Likewise.


Thank you,

-- 
Evandro Menezes


[-- Attachment #2: 0001-Add-support-for-the-FCCMP-insn-types.patch --]
[-- Type: text/x-patch, Size: 4920 bytes --]

From 14874dec3257c7b59aed4b7c610305f76bbbcf33 Mon Sep 17 00:00:00 2001
From: Evandro Menezes <e.menezes@samsung.com>
Date: Mon, 4 Jan 2016 18:44:30 -0600
Subject: [PATCH] Add support for the FCCMP insn types

2016-01-21  Evandro Menezes  <e.menezes@samsung.com>

gcc/
	* config/aarch64/aarch64.md (fccmp): Change insn type.
	(fccmpe): Likewise.
	* config/aarch64/thunderx.md (thunderx_fcmp): Add "fccmp{s,d}" types.
	* config/arm/cortex-a53.md (cortex_a53_fpalu): Likewise.
	* config/arm/cortex-a57.md (cortex_a57_fp_cmp): Likewise.
	* config/arm/xgene1.md (xgene1_fcmp): Likewise.
	* config/arm/exynos-m1.md (exynos_m1_fp_ccmp): New insn reservation.
	* config/arm/types.md (fccmps): Add new insn type.
	(fccmpd): Likewise.
---
 gcc/config/aarch64/aarch64.md  | 4 ++--
 gcc/config/aarch64/thunderx.md | 2 +-
 gcc/config/arm/cortex-a53.md   | 4 ++--
 gcc/config/arm/cortex-a57.md   | 2 +-
 gcc/config/arm/exynos-m1.md    | 5 +++++
 gcc/config/arm/types.md        | 3 +++
 gcc/config/arm/xgene1.md       | 2 +-
 7 files changed, 15 insertions(+), 7 deletions(-)

diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index 2f543aa..032b342 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -301,7 +301,7 @@
 	  (match_operand 5 "immediate_operand")))]
   "TARGET_FLOAT"
   "fccmp\\t%<s>2, %<s>3, %k5, %m4"
-  [(set_attr "type" "fcmp<s>")]
+  [(set_attr "type" "fccmp<s>")]
 )
 
 (define_insn "fccmpe<mode>"
@@ -316,7 +316,7 @@
 	  (match_operand 5 "immediate_operand")))]
   "TARGET_FLOAT"
   "fccmpe\\t%<s>2, %<s>3, %k5, %m4"
-  [(set_attr "type" "fcmp<s>")]
+  [(set_attr "type" "fccmp<s>")]
 )
 
 ;; Expansion of signed mod by a power of 2 using CSNEG.
diff --git a/gcc/config/aarch64/thunderx.md b/gcc/config/aarch64/thunderx.md
index 922df39..058713a 100644
--- a/gcc/config/aarch64/thunderx.md
+++ b/gcc/config/aarch64/thunderx.md
@@ -156,7 +156,7 @@
 
 (define_insn_reservation "thunderx_fcmp" 3
   (and (eq_attr "tune" "thunderx")
-       (eq_attr "type" "fcmps,fcmpd"))
+       (eq_attr "type" "fcmps,fcmpd,fccmps,fccmpd"))
   "thunderx_pipe1")
 
 (define_insn_reservation "thunderx_fmul" 6
diff --git a/gcc/config/arm/cortex-a53.md b/gcc/config/arm/cortex-a53.md
index c1eeedb..fc60bc2 100644
--- a/gcc/config/arm/cortex-a53.md
+++ b/gcc/config/arm/cortex-a53.md
@@ -508,8 +508,8 @@
 (define_insn_reservation "cortex_a53_fpalu" 5
   (and (eq_attr "tune" "cortexa53")
 	(eq_attr "type" "ffariths, fadds, ffarithd, faddd, fmov,
-			f_cvt, fcmps, fcmpd, fcsel, f_rints, f_rintd,
-			f_minmaxs, f_minmaxd"))
+			f_cvt, fcmps, fcmpd, fccmps, fccmpd, fcsel,
+			f_rints, f_rintd, f_minmaxs, f_minmaxd"))
   "cortex_a53_slot_any,cortex_a53_fp_alu")
 
 (define_insn_reservation "cortex_a53_fconst" 3
diff --git a/gcc/config/arm/cortex-a57.md b/gcc/config/arm/cortex-a57.md
index 0d28951..f4c112c 100644
--- a/gcc/config/arm/cortex-a57.md
+++ b/gcc/config/arm/cortex-a57.md
@@ -716,7 +716,7 @@
 
 (define_insn_reservation "cortex_a57_fp_cmp" 7
   (and (eq_attr "tune" "cortexa57")
-       (eq_attr "type" "fcmps,fcmpd"))
+       (eq_attr "type" "fcmps,fcmpd,fccmps,fccmpd"))
   "ca57_cx2")
 
 (define_insn_reservation "cortex_a57_fp_arith" 4
diff --git a/gcc/config/arm/exynos-m1.md b/gcc/config/arm/exynos-m1.md
index 0448073..973c8a9 100644
--- a/gcc/config/arm/exynos-m1.md
+++ b/gcc/config/arm/exynos-m1.md
@@ -823,6 +823,11 @@
        (eq_attr "type" "fcmps, fcmpd"))
   "em1_nmisc")
 
+(define_insn_reservation "exynos_m1_fp_ccmp" 7
+  (and (eq_attr "tune" "exynosm1")
+       (eq_attr "type" "fccmps, fccmpd"))
+  "em1_st, em1_nmisc")
+
 (define_insn_reservation "exynos_m1_fp_sel" 4
   (and (eq_attr "tune" "exynosm1")
        (eq_attr "type" "fcsel"))
diff --git a/gcc/config/arm/types.md b/gcc/config/arm/types.md
index 321ff89..25f79b4 100644
--- a/gcc/config/arm/types.md
+++ b/gcc/config/arm/types.md
@@ -70,6 +70,7 @@
 ; f_rint[d,s]        double/single floating point rount to integral.
 ; f_store[d,s]       double/single store to memory.  Used for VFP unit.
 ; fadd[d,s]          double/single floating-point scalar addition.
+; fccmp[d,s]         From ARMv8-A: floating-point conditional compare.
 ; fcmp[d,s]          double/single floating-point compare.
 ; fconst[d,s]        double/single load immediate.
 ; fcsel              From ARMv8-A: Floating-point conditional select.
@@ -582,6 +583,8 @@
   f_stores,\
   faddd,\
   fadds,\
+  fccmpd,\
+  fccmps,\
   fcmpd,\
   fcmps,\
   fconstd,\
diff --git a/gcc/config/arm/xgene1.md b/gcc/config/arm/xgene1.md
index 8dfd8a1..b7aeac6 100644
--- a/gcc/config/arm/xgene1.md
+++ b/gcc/config/arm/xgene1.md
@@ -154,7 +154,7 @@
 
 (define_insn_reservation "xgene1_fcmp" 10
   (and (eq_attr "tune" "xgene1")
-       (eq_attr "type" "fcmpd,fcmps"))
+       (eq_attr "type" "fcmpd,fcmps,fccmpd,fccmps"))
   "xgene1_decode1op,xgene1_fsu+xgene1_fcmp*3")
 
 (define_insn_reservation "xgene1_fcsel" 3
-- 
2.6.3

Re: [PATCH 2/4 v2][AArch64] Add support for FCCMP

[James Greenhalgh]

On Thu, Jan 21, 2016 at 01:58:31PM -0600, Evandro Menezes wrote:
> Hi, James.
> 
> On 01/21/16 03:24, James Greenhalgh wrote:
> >On Wed, Jan 06, 2016 at 02:44:47PM -0600, Evandro Menezes wrote:
> >>On 01/06/2016 06:04 AM, Wilco Dijkstra wrote:
> >>>>Here's what I had in mind when I inquired about distinguishing FCMP from
> >>>>FCCMP.  As you can see in the patch, Exynos is the only target that
> >>>>cares about it, but I wonder if ThunderX or Xgene would too.
> >>>>
> >>>>What do you think?
> >>>The new attributes look fine (I've got a similar outstanding change), however
> >>>please don't add them to non-AArch64 cores. We only need it for thunderx.md,
> >>>cortex-a53.md, cortex-a57.md, xgene1.md and exynos-m1.md.
> >>         Add support for the FCCMP insn types
> >>
> >>         2016-01-04  Evandro Menezes  <e.menezes@samsung.com>
> >>
> >>         gcc/
> >>             * config/aarch64/aarch64.md (fccmp): Change insn type.
> >>             (fccmpe): Likewise.
> >>             * config/aarch64/thunderx.md (thunderx_fcmp): Add
> >>    "fccmp{s,d}" types.
> >>             * config/arm/cortex-a53.md (cortex_a53_fpalu): Likewise.
> >>             * config/arm/cortex-a57.md (cortex_a57_fp_cmp): Likewise.
> >>             * config/arm/xgene1.md (xgene1_fcmp): Likewise.
> >>             * config/arm/exynos-m1.md (exynos_m1_fp_ccmp): New insn
> >>    reservation.
> >>             * config/arm/types.md (fccmps): Add new insn type.
> >>             (fccmpd): Likewise.
> >>
> >>Got it.  Here's an updated patch.  Again, assuming that your
> >>original patch is in place.  Perhaps you can build on it.
> >If we don't have any targets which care about the fccmps/fccmpd split in
> >the code base, do we really need it? Can we just follow the example of
> >fcsel?
> 
> The Exynos M1 does care about the difference between FCMP and FCCMP,
> as can be seen in the patch.

> More explicitly:
> 
>    (define_insn_reservation "exynos_m1_fp_cmp" 4
>       (and (eq_attr "tune" "exynosm1")
>            (eq_attr "type" "fcmps, fcmpd"))
>       "em1_nmisc")
> 
>    (define_insn_reservation "exynos_m1_fp_ccmp" 7
>       (and (eq_attr "tune" "exynosm1")
>            (eq_attr "type" "fccmps, fccmpd"))
>       "em1_st, em1_nmisc")
> 

I think I was unclear. Your exynos-m1 model cares about splitting fcmp[s/d]
and fccmp, but it doesn't care about splitting fccmp in to fccmps/fccmpd. It
is the split to fccmps/fccmpd that I think is unneccesary at this time.

> >>diff --git a/gcc/config/arm/types.md b/gcc/config/arm/types.md
> >>index 321ff89..daf7162 100644
> >>--- a/gcc/config/arm/types.md
> >>+++ b/gcc/config/arm/types.md
> >>@@ -70,6 +70,7 @@
> >>  ; f_rint[d,s]        double/single floating point rount to integral.
> >>  ; f_store[d,s]       double/single store to memory.  Used for VFP unit.
> >>  ; fadd[d,s]          double/single floating-point scalar addition.
> >>+; fccmp[d,s]         double/single floating-point conditional compare.
> >Can we follow the convention fcsel uses of calling out "From ARMv8-A:"
> >for this type?
> >
> 
> I'm not sure I follow.  Though I didn't refer to the ISA spec, I
> used the description from it for the *fccmp* type.
> 
> Please, advise.

Something like:

; fccmp    From ARMv8-A: floating point conditional compare.

Just to capture that this instruction is only available for cores implementing
ARMv8-A.

Thanks,
James

Re: [PATCH 2/4 v2][AArch64] Add support for FCCMP

[Evandro Menezes]

On 01/21/16 13:58, Evandro Menezes wrote:
> Hi, James.
>
> On 01/21/16 03:24, James Greenhalgh wrote:
>> On Wed, Jan 06, 2016 at 02:44:47PM -0600, Evandro Menezes wrote:
>>> On 01/06/2016 06:04 AM, Wilco Dijkstra wrote:
>>>>> Here's what I had in mind when I inquired about distinguishing 
>>>>> FCMP from
>>>>> FCCMP.  As you can see in the patch, Exynos is the only target that
>>>>> cares about it, but I wonder if ThunderX or Xgene would too.
>>>>>
>>>>> What do you think?
>>>> The new attributes look fine (I've got a similar outstanding 
>>>> change), however
>>>> please don't add them to non-AArch64 cores. We only need it for 
>>>> thunderx.md,
>>>> cortex-a53.md, cortex-a57.md, xgene1.md and exynos-m1.md.
>>>          Add support for the FCCMP insn types
>>>
>>>          2016-01-04  Evandro Menezes <e.menezes@samsung.com>
>>>
>>>          gcc/
>>>              * config/aarch64/aarch64.md (fccmp): Change insn type.
>>>              (fccmpe): Likewise.
>>>              * config/aarch64/thunderx.md (thunderx_fcmp): Add
>>>     "fccmp{s,d}" types.
>>>              * config/arm/cortex-a53.md (cortex_a53_fpalu): Likewise.
>>>              * config/arm/cortex-a57.md (cortex_a57_fp_cmp): Likewise.
>>>              * config/arm/xgene1.md (xgene1_fcmp): Likewise.
>>>              * config/arm/exynos-m1.md (exynos_m1_fp_ccmp): New insn
>>>     reservation.
>>>              * config/arm/types.md (fccmps): Add new insn type.
>>>              (fccmpd): Likewise.
>>>
>>> Got it.  Here's an updated patch.  Again, assuming that your
>>> original patch is in place.  Perhaps you can build on it.
>> If we don't have any targets which care about the fccmps/fccmpd split in
>> the code base, do we really need it? Can we just follow the example of
>> fcsel?
>
> The Exynos M1 does care about the difference between FCMP and FCCMP, 
> as can be seen in the patch.
>
>

More explicitly:

    (define_insn_reservation "exynos_m1_fp_cmp" 4
       (and (eq_attr "tune" "exynosm1")
            (eq_attr "type" "fcmps, fcmpd"))
       "em1_nmisc")

    (define_insn_reservation "exynos_m1_fp_ccmp" 7
       (and (eq_attr "tune" "exynosm1")
            (eq_attr "type" "fccmps, fccmpd"))
       "em1_st, em1_nmisc")


Thank you,

-- 
Evandro Menezes

Re: [PATCH 2/4 v2][AArch64] Add support for FCCMP

[Evandro Menezes]

Hi, James.

On 01/21/16 03:24, James Greenhalgh wrote:
> On Wed, Jan 06, 2016 at 02:44:47PM -0600, Evandro Menezes wrote:
>> On 01/06/2016 06:04 AM, Wilco Dijkstra wrote:
>>>> Here's what I had in mind when I inquired about distinguishing FCMP from
>>>> FCCMP.  As you can see in the patch, Exynos is the only target that
>>>> cares about it, but I wonder if ThunderX or Xgene would too.
>>>>
>>>> What do you think?
>>> The new attributes look fine (I've got a similar outstanding change), however
>>> please don't add them to non-AArch64 cores. We only need it for thunderx.md,
>>> cortex-a53.md, cortex-a57.md, xgene1.md and exynos-m1.md.
>>          Add support for the FCCMP insn types
>>
>>          2016-01-04  Evandro Menezes  <e.menezes@samsung.com>
>>
>>          gcc/
>>              * config/aarch64/aarch64.md (fccmp): Change insn type.
>>              (fccmpe): Likewise.
>>              * config/aarch64/thunderx.md (thunderx_fcmp): Add
>>     "fccmp{s,d}" types.
>>              * config/arm/cortex-a53.md (cortex_a53_fpalu): Likewise.
>>              * config/arm/cortex-a57.md (cortex_a57_fp_cmp): Likewise.
>>              * config/arm/xgene1.md (xgene1_fcmp): Likewise.
>>              * config/arm/exynos-m1.md (exynos_m1_fp_ccmp): New insn
>>     reservation.
>>              * config/arm/types.md (fccmps): Add new insn type.
>>              (fccmpd): Likewise.
>>
>> Got it.  Here's an updated patch.  Again, assuming that your
>> original patch is in place.  Perhaps you can build on it.
> If we don't have any targets which care about the fccmps/fccmpd split in
> the code base, do we really need it? Can we just follow the example of
> fcsel?

The Exynos M1 does care about the difference between FCMP and FCCMP, as 
can be seen in the patch.

>> diff --git a/gcc/config/arm/types.md b/gcc/config/arm/types.md
>> index 321ff89..daf7162 100644
>> --- a/gcc/config/arm/types.md
>> +++ b/gcc/config/arm/types.md
>> @@ -70,6 +70,7 @@
>>   ; f_rint[d,s]        double/single floating point rount to integral.
>>   ; f_store[d,s]       double/single store to memory.  Used for VFP unit.
>>   ; fadd[d,s]          double/single floating-point scalar addition.
>> +; fccmp[d,s]         double/single floating-point conditional compare.
> Can we follow the convention fcsel uses of calling out "From ARMv8-A:"
> for this type?
>

I'm not sure I follow.  Though I didn't refer to the ISA spec, I used 
the description from it for the *fccmp* type.

Please, advise.

-- 
Evandro Menezes

Re: [PATCH 2/4 v2][AArch64] Add support for FCCMP

[James Greenhalgh]

On Thu, Jan 21, 2016 at 11:13:29AM +0000, Wilco Dijkstra wrote:
> James Greenhalgh <james.greenhalgh@arm.com> wrote:
> > If we don't have any targets which care about the fccmps/fccmpd split in
> > the code base, do we really need it? Can we just follow the example of
> > fcsel?
> 
> If we do that then we should also change fcmps/d to fcmp to keep the f(c)cmp
> attributes orthogonal. However it seems better to have all FP operations use
> {s|d} postfix as the convention (rather than assume that all current and future
> microarchitectures will treat float and double identically on all operations),
> so fcsel should ideally be fixed.

Adding values to this type attributes is a pretty lightweight change, and
each new type attribute has a small cost in compiler build-time and scheduler
performance. Given this, I don't see any need to design for the future, and
I don't see why we'd want to add more of them than we need to.

The fcmps/fcmpd split is used in cortex-a15-neon.md and cortex-r4f.md so
doesn't make a good comparison.

If we support a target in future which would benefit from different
modeling for fccmps and fccmpd we can split the value then.

Thanks,
James

Re: [PATCH 2/4 v2][AArch64] Add support for FCCMP

[Wilco Dijkstra]

James Greenhalgh <james.greenhalgh@arm.com> wrote:
> If we don't have any targets which care about the fccmps/fccmpd split in
> the code base, do we really need it? Can we just follow the example of
> fcsel?

If we do that then we should also change fcmps/d to fcmp to keep the f(c)cmp
attributes orthogonal. However it seems better to have all FP operations use
{s|d} postfix as the convention (rather than assume that all current and future
microarchitectures will treat float and double identically on all operations),
so fcsel should ideally be fixed.

Wilco

Re: [PATCH 2/4 v2][AArch64] Add support for FCCMP

[James Greenhalgh]

On Wed, Jan 06, 2016 at 02:44:47PM -0600, Evandro Menezes wrote:
> Hi, Wilco.
> 
> On 01/06/2016 06:04 AM, Wilco Dijkstra wrote:
> >>Here's what I had in mind when I inquired about distinguishing FCMP from
> >>FCCMP.  As you can see in the patch, Exynos is the only target that
> >>cares about it, but I wonder if ThunderX or Xgene would too.
> >>
> >>What do you think?
> >The new attributes look fine (I've got a similar outstanding change), however
> >please don't add them to non-AArch64 cores. We only need it for thunderx.md,
> >cortex-a53.md, cortex-a57.md, xgene1.md and exynos-m1.md.
> 
>         Add support for the FCCMP insn types
> 
>         2016-01-04  Evandro Menezes  <e.menezes@samsung.com>
> 
>         gcc/
>             * config/aarch64/aarch64.md (fccmp): Change insn type.
>             (fccmpe): Likewise.
>             * config/aarch64/thunderx.md (thunderx_fcmp): Add
>    "fccmp{s,d}" types.
>             * config/arm/cortex-a53.md (cortex_a53_fpalu): Likewise.
>             * config/arm/cortex-a57.md (cortex_a57_fp_cmp): Likewise.
>             * config/arm/xgene1.md (xgene1_fcmp): Likewise.
>             * config/arm/exynos-m1.md (exynos_m1_fp_ccmp): New insn
>    reservation.
>             * config/arm/types.md (fccmps): Add new insn type.
>             (fccmpd): Likewise.
> 
> Got it.  Here's an updated patch.  Again, assuming that your
> original patch is in place.  Perhaps you can build on it.

If we don't have any targets which care about the fccmps/fccmpd split in
the code base, do we really need it? Can we just follow the example of
fcsel?

> diff --git a/gcc/config/arm/types.md b/gcc/config/arm/types.md
> index 321ff89..daf7162 100644
> --- a/gcc/config/arm/types.md
> +++ b/gcc/config/arm/types.md
> @@ -70,6 +70,7 @@
>  ; f_rint[d,s]        double/single floating point rount to integral.
>  ; f_store[d,s]       double/single store to memory.  Used for VFP unit.
>  ; fadd[d,s]          double/single floating-point scalar addition.
> +; fccmp[d,s]         double/single floating-point conditional compare.

Can we follow the convention fcsel uses of calling out "From ARMv8-A:"
for this type?

Thanks,
James

Re: [PATCH 2/4 v2][AArch64] Add support for FCCMP

[Evandro Menezes]

On 01/06/16 14:44, Evandro Menezes wrote:
> Hi, Wilco.
>
> On 01/06/2016 06:04 AM, Wilco Dijkstra wrote:
>>> Here's what I had in mind when I inquired about distinguishing FCMP 
>>> from
>>> FCCMP.  As you can see in the patch, Exynos is the only target that
>>> cares about it, but I wonder if ThunderX or Xgene would too.
>>>
>>> What do you think?
>> The new attributes look fine (I've got a similar outstanding change), 
>> however
>> please don't add them to non-AArch64 cores. We only need it for 
>> thunderx.md,
>> cortex-a53.md, cortex-a57.md, xgene1.md and exynos-m1.md.
>
>         Add support for the FCCMP insn types
>
>         2016-01-04  Evandro Menezes  <e.menezes@samsung.com>
>
>         gcc/
>             * config/aarch64/aarch64.md (fccmp): Change insn type.
>             (fccmpe): Likewise.
>             * config/aarch64/thunderx.md (thunderx_fcmp): Add
>    "fccmp{s,d}" types.
>             * config/arm/cortex-a53.md (cortex_a53_fpalu): Likewise.
>             * config/arm/cortex-a57.md (cortex_a57_fp_cmp): Likewise.
>             * config/arm/xgene1.md (xgene1_fcmp): Likewise.
>             * config/arm/exynos-m1.md (exynos_m1_fp_ccmp): New insn
>    reservation.
>             * config/arm/types.md (fccmps): Add new insn type.
>             (fccmpd): Likewise.
>
> Got it.  Here's an updated patch.  Again, assuming that your original 
> patch is in place.  Perhaps you can build on it.
>
> Thank you,
>

Ping.

-- 
Evandro Menezes

Re: [PATCH 2/4 v2][AArch64] Add support for FCCMP

[Evandro Menezes]

[-- Attachment #1: Type: text/plain, Size: 1366 bytes --]

Hi, Wilco.

On 01/06/2016 06:04 AM, Wilco Dijkstra wrote:
>> Here's what I had in mind when I inquired about distinguishing FCMP from
>> FCCMP.  As you can see in the patch, Exynos is the only target that
>> cares about it, but I wonder if ThunderX or Xgene would too.
>>
>> What do you think?
> The new attributes look fine (I've got a similar outstanding change), however
> please don't add them to non-AArch64 cores. We only need it for thunderx.md,
> cortex-a53.md, cortex-a57.md, xgene1.md and exynos-m1.md.

         Add support for the FCCMP insn types

         2016-01-04  Evandro Menezes  <e.menezes@samsung.com>

         gcc/
             * config/aarch64/aarch64.md (fccmp): Change insn type.
             (fccmpe): Likewise.
             * config/aarch64/thunderx.md (thunderx_fcmp): Add
    "fccmp{s,d}" types.
             * config/arm/cortex-a53.md (cortex_a53_fpalu): Likewise.
             * config/arm/cortex-a57.md (cortex_a57_fp_cmp): Likewise.
             * config/arm/xgene1.md (xgene1_fcmp): Likewise.
             * config/arm/exynos-m1.md (exynos_m1_fp_ccmp): New insn
    reservation.
             * config/arm/types.md (fccmps): Add new insn type.
             (fccmpd): Likewise.

Got it.  Here's an updated patch.  Again, assuming that your original 
patch is in place.  Perhaps you can build on it.

Thank you,

-- 
Evandro Menezes


[-- Attachment #2: 0001-Add-support-for-the-FCCMP-insn-types.patch --]
[-- Type: text/x-patch, Size: 4920 bytes --]

From b5b603880eb265536eb927499c8df3ca6c42e718 Mon Sep 17 00:00:00 2001
From: Evandro Menezes <e.menezes@samsung.com>
Date: Mon, 4 Jan 2016 18:44:30 -0600
Subject: [PATCH] Add support for the FCCMP insn types

2016-01-04  Evandro Menezes  <e.menezes@samsung.com>

gcc/
	* config/aarch64/aarch64.md (fccmp): Change insn type.
	(fccmpe): Likewise.
	* config/aarch64/thunderx.md (thunderx_fcmp): Add "fccmp{s,d}" types.
	* config/arm/cortex-a53.md (cortex_a53_fpalu): Likewise.
	* config/arm/cortex-a57.md (cortex_a57_fp_cmp): Likewise.
	* config/arm/xgene1.md (xgene1_fcmp): Likewise.
	* config/arm/exynos-m1.md (exynos_m1_fp_ccmp): New insn reservation.
	* config/arm/types.md (fccmps): Add new insn type.
	(fccmpd): Likewise.
---
 gcc/config/aarch64/aarch64.md  | 4 ++--
 gcc/config/aarch64/thunderx.md | 2 +-
 gcc/config/arm/cortex-a53.md   | 4 ++--
 gcc/config/arm/cortex-a57.md   | 2 +-
 gcc/config/arm/exynos-m1.md    | 5 +++++
 gcc/config/arm/types.md        | 3 +++
 gcc/config/arm/xgene1.md       | 2 +-
 7 files changed, 15 insertions(+), 7 deletions(-)

diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index 8b737bc..9a7ebf4 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -335,7 +335,7 @@
 	  (match_operand 5 "immediate_operand")))]
   "TARGET_FLOAT"
   "fccmp\\t%<s>2, %<s>3, %k5, %m4"
-  [(set_attr "type" "fcmp<s>")]
+  [(set_attr "type" "fccmp<s>")]
 )
 
 (define_insn "fccmpe<mode>"
@@ -350,7 +350,7 @@
 	  (match_operand 5 "immediate_operand")))]
   "TARGET_FLOAT"
   "fccmpe\\t%<s>2, %<s>3, %k5, %m4"
-  [(set_attr "type" "fcmp<s>")]
+  [(set_attr "type" "fccmp<s>")]
 )
 
 ;; Expansion of signed mod by a power of 2 using CSNEG.
diff --git a/gcc/config/aarch64/thunderx.md b/gcc/config/aarch64/thunderx.md
index 922df39..058713a 100644
--- a/gcc/config/aarch64/thunderx.md
+++ b/gcc/config/aarch64/thunderx.md
@@ -156,7 +156,7 @@
 
 (define_insn_reservation "thunderx_fcmp" 3
   (and (eq_attr "tune" "thunderx")
-       (eq_attr "type" "fcmps,fcmpd"))
+       (eq_attr "type" "fcmps,fcmpd,fccmps,fccmpd"))
   "thunderx_pipe1")
 
 (define_insn_reservation "thunderx_fmul" 6
diff --git a/gcc/config/arm/cortex-a53.md b/gcc/config/arm/cortex-a53.md
index c1eeedb..fc60bc2 100644
--- a/gcc/config/arm/cortex-a53.md
+++ b/gcc/config/arm/cortex-a53.md
@@ -508,8 +508,8 @@
 (define_insn_reservation "cortex_a53_fpalu" 5
   (and (eq_attr "tune" "cortexa53")
 	(eq_attr "type" "ffariths, fadds, ffarithd, faddd, fmov,
-			f_cvt, fcmps, fcmpd, fcsel, f_rints, f_rintd,
-			f_minmaxs, f_minmaxd"))
+			f_cvt, fcmps, fcmpd, fccmps, fccmpd, fcsel,
+			f_rints, f_rintd, f_minmaxs, f_minmaxd"))
   "cortex_a53_slot_any,cortex_a53_fp_alu")
 
 (define_insn_reservation "cortex_a53_fconst" 3
diff --git a/gcc/config/arm/cortex-a57.md b/gcc/config/arm/cortex-a57.md
index 0d28951..f4c112c 100644
--- a/gcc/config/arm/cortex-a57.md
+++ b/gcc/config/arm/cortex-a57.md
@@ -716,7 +716,7 @@
 
 (define_insn_reservation "cortex_a57_fp_cmp" 7
   (and (eq_attr "tune" "cortexa57")
-       (eq_attr "type" "fcmps,fcmpd"))
+       (eq_attr "type" "fcmps,fcmpd,fccmps,fccmpd"))
   "ca57_cx2")
 
 (define_insn_reservation "cortex_a57_fp_arith" 4
diff --git a/gcc/config/arm/exynos-m1.md b/gcc/config/arm/exynos-m1.md
index 0448073..973c8a9 100644
--- a/gcc/config/arm/exynos-m1.md
+++ b/gcc/config/arm/exynos-m1.md
@@ -823,6 +823,11 @@
        (eq_attr "type" "fcmps, fcmpd"))
   "em1_nmisc")
 
+(define_insn_reservation "exynos_m1_fp_ccmp" 7
+  (and (eq_attr "tune" "exynosm1")
+       (eq_attr "type" "fccmps, fccmpd"))
+  "em1_st, em1_nmisc")
+
 (define_insn_reservation "exynos_m1_fp_sel" 4
   (and (eq_attr "tune" "exynosm1")
        (eq_attr "type" "fcsel"))
diff --git a/gcc/config/arm/types.md b/gcc/config/arm/types.md
index 321ff89..daf7162 100644
--- a/gcc/config/arm/types.md
+++ b/gcc/config/arm/types.md
@@ -70,6 +70,7 @@
 ; f_rint[d,s]        double/single floating point rount to integral.
 ; f_store[d,s]       double/single store to memory.  Used for VFP unit.
 ; fadd[d,s]          double/single floating-point scalar addition.
+; fccmp[d,s]         double/single floating-point conditional compare.
 ; fcmp[d,s]          double/single floating-point compare.
 ; fconst[d,s]        double/single load immediate.
 ; fcsel              From ARMv8-A: Floating-point conditional select.
@@ -582,6 +583,8 @@
   f_stores,\
   faddd,\
   fadds,\
+  fccmpd,\
+  fccmps,\
   fcmpd,\
   fcmps,\
   fconstd,\
diff --git a/gcc/config/arm/xgene1.md b/gcc/config/arm/xgene1.md
index 8dfd8a1..b7aeac6 100644
--- a/gcc/config/arm/xgene1.md
+++ b/gcc/config/arm/xgene1.md
@@ -154,7 +154,7 @@
 
 (define_insn_reservation "xgene1_fcmp" 10
   (and (eq_attr "tune" "xgene1")
-       (eq_attr "type" "fcmpd,fcmps"))
+       (eq_attr "type" "fcmpd,fcmps,fccmpd,fccmps"))
   "xgene1_decode1op,xgene1_fsu+xgene1_fcmp*3")
 
 (define_insn_reservation "xgene1_fcsel" 3
-- 
1.9.1

Re: [PATCH 2/4 v2][AArch64] Add support for FCCMP

[Wilco Dijkstra]

Hi Evandro,

> Here's what I had in mind when I inquired about distinguishing FCMP from
> FCCMP.  As you can see in the patch, Exynos is the only target that
> cares about it, but I wonder if ThunderX or Xgene would too.
> 
> What do you think?

The new attributes look fine (I've got a similar outstanding change), however
please don't add them to non-AArch64 cores. We only need it for thunderx.md,
cortex-a53.md, cortex-a57.md, xgene1.md and exynos-m1.md.

Wilco

Re: [PATCH 2/4 v2][AArch64] Add support for FCCMP

[Andrew Pinski]

On Tue, Jan 5, 2016 at 2:00 PM, Evandro Menezes <e.menezes@samsung.com> wrote:
> Hi, Wilco.
>
> On 12/15/2015 04:32 AM, Wilco Dijkstra wrote:
>>>
>>> -----Original Message-----
>>> From: Wilco Dijkstra [mailto:Wilco.Dijkstra@arm.com]
>>> Sent: 17 November 2015 18:36
>>> To: gcc-patches@gcc.gnu.org
>>> Subject: [PATCH 2/4 v2][AArch64] Add support for FCCMP
>>>
>>> (v2 version removes 4 enums)
>>>
>>> This patch adds support for FCCMP. This is trivial with the new CCMP
>>> representation - remove the restriction of FP in ccmp.c and add
>>> FCCMP patterns. Add a test to ensure FCCMP/FCCMPE are emitted as
>>> expected.
>>>
>>> OK for commit?
>>>
>>> ChangeLog:
>>> 2015-11-18  Wilco Dijkstra  <wdijkstr@arm.com>
>>>
>>>         * gcc/ccmp.c (ccmp_candidate_p): Remove integer-only restriction.
>>>         * gcc/config/aarch64/aarch64.md (fccmp<mode>): New pattern.
>>>         (fccmpe<mode>): Likewise.
>>>         (fcmp): Rename to fcmp and globalize pattern.
>>>         (fcmpe): Likewise.
>>>         * gcc/config/aarch64/aarch64.c (aarch64_gen_ccmp_first): Add FP
>>> support.
>>>         (aarch64_gen_ccmp_next): Add FP support.
>>>
>>> gcc/testsuite/
>>>         * gcc.target/aarch64/ccmp_1.c: New testcase.
>
>
>         Add support for the FCCMP insn types
>
>         2016-01-04  Evandro Menezes  <e.menezes@samsung.com>
>
>         gcc/
>             * config/aarch64/aarch64.md (fccmp): Change insn type.
>             (fccmpe): Likewise.
>             * config/aarch64/thunderx.md (thunderx_fcmp): Add
>    "fccmp{s,d}" types.
>             * config/arm/types.md (fccmps): Add new insn type.
>             (fccmpd): Likewise.
>             * config/arm/arm1020e.md (v10_ffarith): Add "fccmp{s,d}" types.
>             * config/arm/cortex-a17-neon.md (cortex_a17_vfp_cmp): Likewise.
>             * config/arm/cortex-a5.md (cortex_a5_fpalu): Likewise.
>             * config/arm/cortex-a53.md (cortex_a53_fpalu): Likewise.
>             * config/arm/cortex-a57.md (cortex_a57_fp_cmp): Likewise.
>             * config/arm/cortex-a7.md (cortex_a7_fpalu): Likewise.
>             * config/arm/cortex-a8-neon.md (cortex_a8_vfp_farith):
>    Likewise.
>             * config/arm/cortex-a9.md (cortex_a9_fcmp): Likewise.
>             * config/arm/cortex-m7.md (cortex_m7_fpalu): Likewise.
>             * config/arm/marvell-pj4.md (pj4_vfp_cpy): Likewise.
>             * config/arm/vfp11.md (vfp_ffarith): Likewise.
>             * config/arm/xgene1.md (xgene1_fcmp): Likewise.
>             * config/arm/cortex-a15-neon.md (cortex_a15_vfp_cmps): Add
>    "fccmps"
>             type.
>             (cortex_a15_vfp_cmpd): Add "fccmpd" type.
>             * config/arm/cortex-m4-fpu.md (cortex_m4_fcmps): Add
>    "fccmps" type.
>             * config/arm/cortex-r4f.md (cortex_r4_ffariths): Likewise.
>             (cortex_r4_fcmpd): Add "fccmpd" type.
>             * config/arm/exynos-m1.md (exynos_m1_fp_ccmp): New insn
>    reservation.
>
> Here's what I had in mind when I inquired about distinguishing FCMP from
> FCCMP.  As you can see in the patch, Exynos is the only target that cares
> about it, but I wonder if ThunderX or Xgene would too.

For ThunderX, FCCMP and FCMP have both the same latency and executed
on the same pipeline so ThunderX does not care about the difference
between those two.

Thanks,
Andrew

>
> What do you think?
>
> Thank you,
>
> --
> Evandro Menezes
>

Re: [PATCH 2/4 v2][AArch64] Add support for FCCMP

[Evandro Menezes]

[-- Attachment #1: Type: text/plain, Size: 2994 bytes --]

Hi, Wilco.

On 12/15/2015 04:32 AM, Wilco Dijkstra wrote:
>> -----Original Message-----
>> From: Wilco Dijkstra [mailto:Wilco.Dijkstra@arm.com]
>> Sent: 17 November 2015 18:36
>> To: gcc-patches@gcc.gnu.org
>> Subject: [PATCH 2/4 v2][AArch64] Add support for FCCMP
>>
>> (v2 version removes 4 enums)
>>
>> This patch adds support for FCCMP. This is trivial with the new CCMP representation - remove the restriction of FP in ccmp.c and add
>> FCCMP patterns. Add a test to ensure FCCMP/FCCMPE are emitted as expected.
>>
>> OK for commit?
>>
>> ChangeLog:
>> 2015-11-18  Wilco Dijkstra  <wdijkstr@arm.com>
>>
>> 	* gcc/ccmp.c (ccmp_candidate_p): Remove integer-only restriction.
>> 	* gcc/config/aarch64/aarch64.md (fccmp<mode>): New pattern.
>> 	(fccmpe<mode>): Likewise.
>> 	(fcmp): Rename to fcmp and globalize pattern.
>> 	(fcmpe): Likewise.
>> 	* gcc/config/aarch64/aarch64.c (aarch64_gen_ccmp_first): Add FP support.
>> 	(aarch64_gen_ccmp_next): Add FP support.
>>
>> gcc/testsuite/
>> 	* gcc.target/aarch64/ccmp_1.c: New testcase.

         Add support for the FCCMP insn types

         2016-01-04  Evandro Menezes  <e.menezes@samsung.com>

         gcc/
             * config/aarch64/aarch64.md (fccmp): Change insn type.
             (fccmpe): Likewise.
             * config/aarch64/thunderx.md (thunderx_fcmp): Add
    "fccmp{s,d}" types.
             * config/arm/types.md (fccmps): Add new insn type.
             (fccmpd): Likewise.
             * config/arm/arm1020e.md (v10_ffarith): Add "fccmp{s,d}" types.
             * config/arm/cortex-a17-neon.md (cortex_a17_vfp_cmp): Likewise.
             * config/arm/cortex-a5.md (cortex_a5_fpalu): Likewise.
             * config/arm/cortex-a53.md (cortex_a53_fpalu): Likewise.
             * config/arm/cortex-a57.md (cortex_a57_fp_cmp): Likewise.
             * config/arm/cortex-a7.md (cortex_a7_fpalu): Likewise.
             * config/arm/cortex-a8-neon.md (cortex_a8_vfp_farith):
    Likewise.
             * config/arm/cortex-a9.md (cortex_a9_fcmp): Likewise.
             * config/arm/cortex-m7.md (cortex_m7_fpalu): Likewise.
             * config/arm/marvell-pj4.md (pj4_vfp_cpy): Likewise.
             * config/arm/vfp11.md (vfp_ffarith): Likewise.
             * config/arm/xgene1.md (xgene1_fcmp): Likewise.
             * config/arm/cortex-a15-neon.md (cortex_a15_vfp_cmps): Add
    "fccmps"
             type.
             (cortex_a15_vfp_cmpd): Add "fccmpd" type.
             * config/arm/cortex-m4-fpu.md (cortex_m4_fcmps): Add
    "fccmps" type.
             * config/arm/cortex-r4f.md (cortex_r4_ffariths): Likewise.
             (cortex_r4_fcmpd): Add "fccmpd" type.
             * config/arm/exynos-m1.md (exynos_m1_fp_ccmp): New insn
    reservation.

Here's what I had in mind when I inquired about distinguishing FCMP from 
FCCMP.  As you can see in the patch, Exynos is the only target that 
cares about it, but I wonder if ThunderX or Xgene would too.

What do you think?

Thank you,

-- 
Evandro Menezes


[-- Attachment #2: 0001-Add-support-for-the-FCCMP-insn-types.patch --]
[-- Type: text/x-patch, Size: 12992 bytes --]

From d96ede48a0adb46cec1f98acfe967fce22dcc406 Mon Sep 17 00:00:00 2001
From: Evandro Menezes <e.menezes@samsung.com>
Date: Mon, 4 Jan 2016 18:44:30 -0600
Subject: [PATCH] Add support for the FCCMP insn types

2016-01-04  Evandro Menezes  <e.menezes@samsung.com>

gcc/
	* config/aarch64/aarch64.md (fccmp): Change insn type.
	(fccmpe): Likewise.
	* config/aarch64/thunderx.md (thunderx_fcmp): Add "fccmp{s,d}" types.
	* config/arm/types.md (fccmps): Add new insn type.
	(fccmpd): Likewise.
	* config/arm/arm1020e.md (v10_ffarith): Add "fccmp{s,d}" types.
	* config/arm/cortex-a17-neon.md (cortex_a17_vfp_cmp): Likewise.
	* config/arm/cortex-a5.md (cortex_a5_fpalu): Likewise.
	* config/arm/cortex-a53.md (cortex_a53_fpalu): Likewise.
	* config/arm/cortex-a57.md (cortex_a57_fp_cmp): Likewise.
	* config/arm/cortex-a7.md (cortex_a7_fpalu): Likewise.
	* config/arm/cortex-a8-neon.md (cortex_a8_vfp_farith): Likewise.
	* config/arm/cortex-a9.md (cortex_a9_fcmp): Likewise.
	* config/arm/cortex-m7.md (cortex_m7_fpalu): Likewise.
	* config/arm/marvell-pj4.md (pj4_vfp_cpy): Likewise.
	* config/arm/vfp11.md (vfp_ffarith): Likewise.
	* config/arm/xgene1.md (xgene1_fcmp): Likewise.
	* config/arm/cortex-a15-neon.md (cortex_a15_vfp_cmps): Add "fccmps"
	type.
	(cortex_a15_vfp_cmpd): Add "fccmpd" type.
	* config/arm/cortex-m4-fpu.md (cortex_m4_fcmps): Add "fccmps" type.
	* config/arm/cortex-r4f.md (cortex_r4_ffariths): Likewise.
	(cortex_r4_fcmpd): Add "fccmpd" type.
	* config/arm/exynos-m1.md (exynos_m1_fp_ccmp): New insn reservation.
---
 gcc/config/aarch64/aarch64.md     | 4 ++--
 gcc/config/aarch64/thunderx.md    | 2 +-
 gcc/config/arm/arm1020e.md        | 2 +-
 gcc/config/arm/cortex-a15-neon.md | 4 ++--
 gcc/config/arm/cortex-a17-neon.md | 2 +-
 gcc/config/arm/cortex-a5.md       | 2 +-
 gcc/config/arm/cortex-a53.md      | 3 ++-
 gcc/config/arm/cortex-a57.md      | 2 +-
 gcc/config/arm/cortex-a7.md       | 3 ++-
 gcc/config/arm/cortex-a8-neon.md  | 3 ++-
 gcc/config/arm/cortex-a9.md       | 2 +-
 gcc/config/arm/cortex-m4-fpu.md   | 2 +-
 gcc/config/arm/cortex-m7.md       | 3 ++-
 gcc/config/arm/cortex-r4f.md      | 4 ++--
 gcc/config/arm/exynos-m1.md       | 5 +++++
 gcc/config/arm/marvell-pj4.md     | 2 +-
 gcc/config/arm/types.md           | 3 +++
 gcc/config/arm/vfp11.md           | 2 +-
 gcc/config/arm/xgene1.md          | 2 +-
 19 files changed, 32 insertions(+), 20 deletions(-)

diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
index 8b737bc..9a7ebf4 100644
--- a/gcc/config/aarch64/aarch64.md
+++ b/gcc/config/aarch64/aarch64.md
@@ -335,7 +335,7 @@
 	  (match_operand 5 "immediate_operand")))]
   "TARGET_FLOAT"
   "fccmp\\t%<s>2, %<s>3, %k5, %m4"
-  [(set_attr "type" "fcmp<s>")]
+  [(set_attr "type" "fccmp<s>")]
 )
 
 (define_insn "fccmpe<mode>"
@@ -350,7 +350,7 @@
 	  (match_operand 5 "immediate_operand")))]
   "TARGET_FLOAT"
   "fccmpe\\t%<s>2, %<s>3, %k5, %m4"
-  [(set_attr "type" "fcmp<s>")]
+  [(set_attr "type" "fccmp<s>")]
 )
 
 ;; Expansion of signed mod by a power of 2 using CSNEG.
diff --git a/gcc/config/aarch64/thunderx.md b/gcc/config/aarch64/thunderx.md
index 922df39..058713a 100644
--- a/gcc/config/aarch64/thunderx.md
+++ b/gcc/config/aarch64/thunderx.md
@@ -156,7 +156,7 @@
 
 (define_insn_reservation "thunderx_fcmp" 3
   (and (eq_attr "tune" "thunderx")
-       (eq_attr "type" "fcmps,fcmpd"))
+       (eq_attr "type" "fcmps,fcmpd,fccmps,fccmpd"))
   "thunderx_pipe1")
 
 (define_insn_reservation "thunderx_fmul" 6
diff --git a/gcc/config/arm/arm1020e.md b/gcc/config/arm/arm1020e.md
index 7cdab57..73532a1 100644
--- a/gcc/config/arm/arm1020e.md
+++ b/gcc/config/arm/arm1020e.md
@@ -279,7 +279,7 @@
 ;; first execute state.  We model this by using 1020a_e in the first cycle.
 (define_insn_reservation "v10_ffarith" 5
  (and (eq_attr "vfp10" "yes")
-      (eq_attr "type" "fmov,ffariths,ffarithd,fcmps,fcmpd"))
+      (eq_attr "type" "fmov,ffariths,ffarithd,fcmps,fcmpd,fccmps,fccmpd"))
  "1020a_e+v10_fmac")
 
 (define_insn_reservation "v10_farith" 5
diff --git a/gcc/config/arm/cortex-a15-neon.md b/gcc/config/arm/cortex-a15-neon.md
index 082ccd7..3f9ea75 100644
--- a/gcc/config/arm/cortex-a15-neon.md
+++ b/gcc/config/arm/cortex-a15-neon.md
@@ -637,12 +637,12 @@
 
 (define_insn_reservation "cortex_a15_vfp_cmpd" 8
   (and (eq_attr "tune" "cortexa15")
-       (eq_attr "type" "fcmpd"))
+       (eq_attr "type" "fcmpd,fccmpd"))
   "ca15_issue2,ca15_cx_perm,ca15_cx_vfp")
 
 (define_insn_reservation "cortex_a15_vfp_cmps" 8
   (and (eq_attr "tune" "cortexa15")
-       (eq_attr "type" "fcmps"))
+       (eq_attr "type" "fcmps,fccmps"))
   "ca15_issue2,ca15_cx_perm,ca15_cx_vfp")
 
 (define_insn_reservation "cortex_a15_vfp_arithd" 7
diff --git a/gcc/config/arm/cortex-a17-neon.md b/gcc/config/arm/cortex-a17-neon.md
index 1385560..140fafa 100644
--- a/gcc/config/arm/cortex-a17-neon.md
+++ b/gcc/config/arm/cortex-a17-neon.md
@@ -565,7 +565,7 @@
 
 (define_insn_reservation "cortex_a17_vfp_cmp" 4
   (and (eq_attr "tune" "cortexa17")
-       (eq_attr "type" "fcmps,fcmpd"))
+       (eq_attr "type" "fcmps,fcmpd,fccmps,fccmpd"))
   "ca17_asimd1+ca17_fpadd1")
 
 (define_insn_reservation "cortex_a17_vfp_arithd" 4
diff --git a/gcc/config/arm/cortex-a5.md b/gcc/config/arm/cortex-a5.md
index 65c12a5..b4c7283 100644
--- a/gcc/config/arm/cortex-a5.md
+++ b/gcc/config/arm/cortex-a5.md
@@ -170,7 +170,7 @@
   (and (eq_attr "tune" "cortexa5")
        (eq_attr "type" "ffariths, fadds, ffarithd, faddd, fmov, fmuls,\
                         f_cvt,f_cvtf2i,f_cvti2f,\
-			fcmps, fcmpd"))
+			fcmps, fcmpd, fccmps, fccmpd"))
   "cortex_a5_ex1+cortex_a5_fpadd_pipe")
 
 ;; For fconsts and fconstd, 8-bit immediate data is passed directly from
diff --git a/gcc/config/arm/cortex-a53.md b/gcc/config/arm/cortex-a53.md
index c1eeedb..aa76c97 100644
--- a/gcc/config/arm/cortex-a53.md
+++ b/gcc/config/arm/cortex-a53.md
@@ -508,7 +508,8 @@
 (define_insn_reservation "cortex_a53_fpalu" 5
   (and (eq_attr "tune" "cortexa53")
 	(eq_attr "type" "ffariths, fadds, ffarithd, faddd, fmov,
-			f_cvt, fcmps, fcmpd, fcsel, f_rints, f_rintd,
+			f_cvt, fcmps, fcmpd, fccmps, fccmpd, fcsel,
+			f_rints, f_rintd,
 			f_minmaxs, f_minmaxd"))
   "cortex_a53_slot_any,cortex_a53_fp_alu")
 
diff --git a/gcc/config/arm/cortex-a57.md b/gcc/config/arm/cortex-a57.md
index 0d28951..f4c112c 100644
--- a/gcc/config/arm/cortex-a57.md
+++ b/gcc/config/arm/cortex-a57.md
@@ -716,7 +716,7 @@
 
 (define_insn_reservation "cortex_a57_fp_cmp" 7
   (and (eq_attr "tune" "cortexa57")
-       (eq_attr "type" "fcmps,fcmpd"))
+       (eq_attr "type" "fcmps,fcmpd,fccmps,fccmpd"))
   "ca57_cx2")
 
 (define_insn_reservation "cortex_a57_fp_arith" 4
diff --git a/gcc/config/arm/cortex-a7.md b/gcc/config/arm/cortex-a7.md
index a7ee466..a2eea0e 100644
--- a/gcc/config/arm/cortex-a7.md
+++ b/gcc/config/arm/cortex-a7.md
@@ -244,7 +244,8 @@
 (define_insn_reservation "cortex_a7_fpalu" 4
   (and (eq_attr "tune" "cortexa7")
        (eq_attr "type" "ffariths, fadds, ffarithd, faddd, fmov,\
-                        f_cvt, f_cvtf2i, f_cvti2f, fcmps, fcmpd"))
+                        f_cvt, f_cvtf2i, f_cvti2f,\
+                        fcmps, fcmpd, fccmps, fccmpd"))
   "cortex_a7_ex1+cortex_a7_fpadd_pipe")
 
 ;; For fconsts and fconstd, 8-bit immediate data is passed directly from
diff --git a/gcc/config/arm/cortex-a8-neon.md b/gcc/config/arm/cortex-a8-neon.md
index 45f861f..aff2605 100644
--- a/gcc/config/arm/cortex-a8-neon.md
+++ b/gcc/config/arm/cortex-a8-neon.md
@@ -387,7 +387,8 @@
 ;; take four cycles, we pick that latency.
 (define_insn_reservation "cortex_a8_vfp_farith" 4
   (and (eq_attr "tune" "cortexa8")
-       (eq_attr "type" "fmov,ffariths,ffarithd,fconsts,fconstd,fcmps,fcmpd"))
+       (eq_attr "type" "fmov,ffariths,ffarithd,fconsts,fconstd,\
+			fcmps,fcmpd,fccmps,fccmpd"))
   "cortex_a8_vfp,cortex_a8_vfplite*3")
 
 (define_insn_reservation "cortex_a8_vfp_cvt" 7
diff --git a/gcc/config/arm/cortex-a9.md b/gcc/config/arm/cortex-a9.md
index 7905816..df2afa6 100644
--- a/gcc/config/arm/cortex-a9.md
+++ b/gcc/config/arm/cortex-a9.md
@@ -238,7 +238,7 @@ cortex_a9_store3_4, cortex_a9_store1_2,  cortex_a9_load3_4")
 
 (define_insn_reservation "cortex_a9_fcmp" 1
   (and (eq_attr "tune" "cortexa9")
-      (eq_attr "type" "fcmps, fcmpd"))
+      (eq_attr "type" "fcmps, fcmpd, fccmps, fccmpd"))
  "ca9_issue_vfp_neon + ca9fp_add1")
 
 ;; Scheduling for the Multiply and MAC instructions.
diff --git a/gcc/config/arm/cortex-m4-fpu.md b/gcc/config/arm/cortex-m4-fpu.md
index db02568..3e1c867 100644
--- a/gcc/config/arm/cortex-m4-fpu.md
+++ b/gcc/config/arm/cortex-m4-fpu.md
@@ -67,7 +67,7 @@
 
 (define_insn_reservation "cortex_m4_fcmps" 1
   (and (eq_attr "tune" "cortexm4")
-       (eq_attr "type" "fcmps"))
+       (eq_attr "type" "fcmps,fccmps"))
   "cortex_m4_ex_v")
 
 (define_insn_reservation "cortex_m4_f_flag" 1
diff --git a/gcc/config/arm/cortex-m7.md b/gcc/config/arm/cortex-m7.md
index 71d04f0..09a0e37 100644
--- a/gcc/config/arm/cortex-m7.md
+++ b/gcc/config/arm/cortex-m7.md
@@ -126,7 +126,8 @@
 (define_insn_reservation "cortex_m7_fpalu" 3
   (and (eq_attr "tune" "cortexm7")
        (eq_attr "type" "ffariths,ffarithd,fadds,faddd,fmov,fconsts,\
-                        fconstd,fcmpd,f_cvt,f_cvtf2i,f_cvti2f, fcmps,\
+                        fconstd,f_cvt,f_cvtf2i,f_cvti2f,\
+                        fcmps,fcmpd,fccmps,fccmpd,\
                         fmuls,f_flag"))
   "cm7_i0|cm7_i1,cm7_fpu")
 
diff --git a/gcc/config/arm/cortex-r4f.md b/gcc/config/arm/cortex-r4f.md
index a34feb7..45d5116 100644
--- a/gcc/config/arm/cortex-r4f.md
+++ b/gcc/config/arm/cortex-r4f.md
@@ -53,7 +53,7 @@
 
 (define_insn_reservation "cortex_r4_ffariths" 2
  (and (eq_attr "tune_cortexr4" "yes")
-      (eq_attr "type" "ffariths,fconsts,fcmps"))
+      (eq_attr "type" "ffariths,fconsts,fcmps,fccmps"))
  "cortex_r4_issue_ab+cortex_r4_issue_c+cortex_r4_v1")
 
 (define_insn_reservation "cortex_r4_fariths" 3
@@ -141,7 +141,7 @@
 
 (define_insn_reservation "cortex_r4_fcmpd" 2
  (and (eq_attr "tune_cortexr4" "yes")
-      (eq_attr "type" "fcmpd"))
+      (eq_attr "type" "fcmpd,fccmpd"))
  "cortex_r4_single_issue*2")
 
 (define_insn_reservation "cortex_r4_f_cvt" 8
diff --git a/gcc/config/arm/exynos-m1.md b/gcc/config/arm/exynos-m1.md
index 0448073..973c8a9 100644
--- a/gcc/config/arm/exynos-m1.md
+++ b/gcc/config/arm/exynos-m1.md
@@ -823,6 +823,11 @@
        (eq_attr "type" "fcmps, fcmpd"))
   "em1_nmisc")
 
+(define_insn_reservation "exynos_m1_fp_ccmp" 7
+  (and (eq_attr "tune" "exynosm1")
+       (eq_attr "type" "fccmps, fccmpd"))
+  "em1_st, em1_nmisc")
+
 (define_insn_reservation "exynos_m1_fp_sel" 4
   (and (eq_attr "tune" "exynosm1")
        (eq_attr "type" "fcsel"))
diff --git a/gcc/config/arm/marvell-pj4.md b/gcc/config/arm/marvell-pj4.md
index c1bc99e..5c49853 100644
--- a/gcc/config/arm/marvell-pj4.md
+++ b/gcc/config/arm/marvell-pj4.md
@@ -209,7 +209,7 @@
 (define_insn_reservation "pj4_vfp_cpy"  4
   (and (eq_attr "tune" "marvell_pj4")
        (eq_attr "type" "fmov,ffariths,ffarithd,fconsts,fconstd,\
-                        fcmps,fcmpd,f_cvt,f_cvtf2i,f_cvti2f"))
+                        fcmps,fcmpd,fccmps,fccmpd,f_cvt,f_cvtf2i,f_cvti2f"))
 "pj4_is,nothing*2,vissue,vfast,nothing*2")
 
 ;; Enlarge latency, and wish that more nondependent insns are
diff --git a/gcc/config/arm/types.md b/gcc/config/arm/types.md
index 321ff89..daf7162 100644
--- a/gcc/config/arm/types.md
+++ b/gcc/config/arm/types.md
@@ -70,6 +70,7 @@
 ; f_rint[d,s]        double/single floating point rount to integral.
 ; f_store[d,s]       double/single store to memory.  Used for VFP unit.
 ; fadd[d,s]          double/single floating-point scalar addition.
+; fccmp[d,s]         double/single floating-point conditional compare.
 ; fcmp[d,s]          double/single floating-point compare.
 ; fconst[d,s]        double/single load immediate.
 ; fcsel              From ARMv8-A: Floating-point conditional select.
@@ -582,6 +583,8 @@
   f_stores,\
   faddd,\
   fadds,\
+  fccmpd,\
+  fccmps,\
   fcmpd,\
   fcmps,\
   fconstd,\
diff --git a/gcc/config/arm/vfp11.md b/gcc/config/arm/vfp11.md
index 9fac4ce..1390fa1 100644
--- a/gcc/config/arm/vfp11.md
+++ b/gcc/config/arm/vfp11.md
@@ -51,7 +51,7 @@
 
 (define_insn_reservation "vfp_ffarith" 4
  (and (eq_attr "generic_vfp" "yes")
-      (eq_attr "type" "fmov,ffariths,ffarithd,fcmps,fcmpd"))
+      (eq_attr "type" "fmov,ffariths,ffarithd,fcmps,fcmpd,fccmps,fccmpd,"))
  "fmac")
 
 (define_insn_reservation "vfp_farith" 8
diff --git a/gcc/config/arm/xgene1.md b/gcc/config/arm/xgene1.md
index 8dfd8a1..b7aeac6 100644
--- a/gcc/config/arm/xgene1.md
+++ b/gcc/config/arm/xgene1.md
@@ -154,7 +154,7 @@
 
 (define_insn_reservation "xgene1_fcmp" 10
   (and (eq_attr "tune" "xgene1")
-       (eq_attr "type" "fcmpd,fcmps"))
+       (eq_attr "type" "fcmpd,fcmps,fccmpd,fccmps"))
   "xgene1_decode1op,xgene1_fsu+xgene1_fcmp*3")
 
 (define_insn_reservation "xgene1_fcsel" 3
-- 
1.9.1

Re: [PATCH 2/4 v2][AArch64] Add support for FCCMP

[Bernd Schmidt]

On 12/15/2015 06:20 PM, Wilco Dijkstra wrote:
> Adding Bernd - would you mind reviewing the ccmp.c change please?

Oh sorry, didn't realize there was one in here as well. Looks ok.


Bernd

RE: [PATCH 2/4 v2][AArch64] Add support for FCCMP

[Wilco Dijkstra]

Adding Bernd - would you mind reviewing the ccmp.c change please?

> -----Original Message-----
> From: James Greenhalgh [mailto:james.greenhalgh@arm.com]
> Sent: 15 December 2015 16:42
> To: Wilco Dijkstra
> Cc: gcc-patches@gcc.gnu.org
> Subject: Re: [PATCH 2/4 v2][AArch64] Add support for FCCMP
> 
> On Tue, Dec 15, 2015 at 10:32:50AM +0000, Wilco Dijkstra wrote:
> > ping
> >
> > > -----Original Message-----
> > > From: Wilco Dijkstra [mailto:Wilco.Dijkstra@arm.com]
> > > Sent: 17 November 2015 18:36
> > > To: gcc-patches@gcc.gnu.org
> > > Subject: [PATCH 2/4 v2][AArch64] Add support for FCCMP
> > >
> > > (v2 version removes 4 enums)
> > >
> > > This patch adds support for FCCMP. This is trivial with the new CCMP representation - remove the restriction of FP in ccmp.c and
> add
> > > FCCMP patterns. Add a test to ensure FCCMP/FCCMPE are emitted as expected.
> > >
> > > OK for commit?
> 
> The AArch64 code-generation parts of this are OK, though please wait for
> an OK on the ccmp.c changes before committing, and please revisit the
> testcase.
> 
> Sorry that this took a long time to get to.

No problem.

> > > ChangeLog:
> > > 2015-11-18  Wilco Dijkstra  <wdijkstr@arm.com>
> > >
> > > 	* gcc/ccmp.c (ccmp_candidate_p): Remove integer-only restriction.
> 
> Drop the gcc/ from the paths here and below.
> 
> > > 	* gcc/config/aarch64/aarch64.md (fccmp<mode>): New pattern.
> > > 	(fccmpe<mode>): Likewise.
> > > 	(fcmp): Rename to fcmp and globalize pattern.
> > > 	(fcmpe): Likewise.
> > > 	* gcc/config/aarch64/aarch64.c (aarch64_gen_ccmp_first): Add FP support.
> > > 	(aarch64_gen_ccmp_next): Add FP support.
> > >
> > > gcc/testsuite/
> > > 	* gcc.target/aarch64/ccmp_1.c: New testcase.
> 
> This testcase doesn't look very helpful to me. You only end up checking if
> *any* of the tests compile to fccmp/fccmpe rather than *all* the tests. Should
> this use a scan-assembler-times directive to count the number of times a
> particular instruction appears?

There are no costs involved so there is no guarantee which CCMPs we will see
generated. After patch 3 and 4, the order is better defined and the testcase is
updated to reflect what we expect to be generated.

The alternative would be to not add the testcase here, but in part 4. However in
internal review it was requested to add it to this part of the patch...

Wilco

> > > ---
> > >  gcc/ccmp.c                                |  6 ---
> > >  gcc/config/aarch64/aarch64.c              | 24 +++++++++
> > >  gcc/config/aarch64/aarch64.md             | 34 ++++++++++++-
> > >  gcc/testsuite/gcc.target/aarch64/ccmp_1.c | 84 +++++++++++++++++++++++++++++++
> > >  4 files changed, 140 insertions(+), 8 deletions(-)
> > >  create mode 100644 gcc/testsuite/gcc.target/aarch64/ccmp_1.c
> > >
> > > diff --git a/gcc/ccmp.c b/gcc/ccmp.c
> > > index 58ac126..3698a7d 100644
> > > --- a/gcc/ccmp.c
> > > +++ b/gcc/ccmp.c
> > > @@ -112,12 +112,6 @@ ccmp_candidate_p (gimple *g)
> > >        || gimple_bb (gs0) != gimple_bb (g))
> > >      return false;
> > >
> > > -  if (!(INTEGRAL_TYPE_P (TREE_TYPE (gimple_assign_rhs1 (gs0)))
> > > -       || POINTER_TYPE_P (TREE_TYPE (gimple_assign_rhs1 (gs0))))
> > > -      || !(INTEGRAL_TYPE_P (TREE_TYPE (gimple_assign_rhs1 (gs1)))
> > > -	   || POINTER_TYPE_P (TREE_TYPE (gimple_assign_rhs1 (gs1)))))
> > > -    return false;
> > > -
> > >    tcode0 = gimple_assign_rhs_code (gs0);
> > >    tcode1 = gimple_assign_rhs_code (gs1);
> > >    if (TREE_CODE_CLASS (tcode0) == tcc_comparison
> > > diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
> > > index c8bee3b..db4d190 100644
> > > --- a/gcc/config/aarch64/aarch64.c
> > > +++ b/gcc/config/aarch64/aarch64.c
> > > @@ -12398,6 +12398,18 @@ aarch64_gen_ccmp_first (rtx *prep_seq, rtx *gen_seq,
> > >        icode = CODE_FOR_cmpdi;
> > >        break;
> > >
> > > +    case SFmode:
> > > +      cmp_mode = SFmode;
> > > +      cc_mode = aarch64_select_cc_mode ((rtx_code) code, op0, op1);
> > > +      icode = cc_mode == CCFPEmode ? CODE_FOR_fcmpesf : CODE_FOR_fcmpsf;
> > > +      break;
> > > +
> > > +    case DFmode:
> > > +      cmp_mode = DFmode;
> > > +      cc_mode = aarch64_select_cc_mode ((rtx_code) code, op0, op1);
> > > +      icode = cc_mode == CCFPEmode ? CODE_FOR_fcmpedf : CODE_FOR_fcmpdf;
> > > +      break;
> > > +
> > >      default:
> > >        end_sequence ();
> > >        return NULL_RTX;
> > > @@ -12461,6 +12473,18 @@ aarch64_gen_ccmp_next (rtx *prep_seq, rtx *gen_seq, rtx prev, int cmp_code,
> > >        icode = CODE_FOR_ccmpdi;
> > >        break;
> > >
> > > +    case SFmode:
> > > +      cmp_mode = SFmode;
> > > +      cc_mode = aarch64_select_cc_mode ((rtx_code) cmp_code, op0, op1);
> > > +      icode = cc_mode == CCFPEmode ? CODE_FOR_fccmpesf : CODE_FOR_fccmpsf;
> > > +      break;
> > > +
> > > +    case DFmode:
> > > +      cmp_mode = DFmode;
> > > +      cc_mode = aarch64_select_cc_mode ((rtx_code) cmp_code, op0, op1);
> > > +      icode = cc_mode == CCFPEmode ? CODE_FOR_fccmpedf : CODE_FOR_fccmpdf;
> > > +      break;
> > > +
> > >      default:
> > >        end_sequence ();
> > >        return NULL_RTX;
> > > diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
> > > index fab65c6..7d728b5 100644
> > > --- a/gcc/config/aarch64/aarch64.md
> > > +++ b/gcc/config/aarch64/aarch64.md
> > > @@ -279,6 +279,36 @@
> > >    [(set_attr "type" "alus_sreg,alus_imm,alus_imm")]
> > >  )
> > >
> > > +(define_insn "fccmp<mode>"
> > > +  [(set (match_operand:CCFP 1 "cc_register" "")
> > > +	(if_then_else:CCFP
> > > +	  (match_operator 4 "aarch64_comparison_operator"
> > > +	   [(match_operand 0 "cc_register" "")
> > > +	    (const_int 0)])
> > > +	  (compare:CCFP
> > > +	    (match_operand:GPF 2 "register_operand" "w")
> > > +	    (match_operand:GPF 3 "register_operand" "w"))
> > > +	  (match_operand 5 "immediate_operand")))]
> > > +  "TARGET_FLOAT"
> > > +  "fccmp\\t%<s>2, %<s>3, %k5, %m4"
> > > +  [(set_attr "type" "fcmp<s>")]
> > > +)
> > > +
> > > +(define_insn "fccmpe<mode>"
> > > +  [(set (match_operand:CCFPE 1 "cc_register" "")
> > > +	 (if_then_else:CCFPE
> > > +	  (match_operator 4 "aarch64_comparison_operator"
> > > +	   [(match_operand 0 "cc_register" "")
> > > +	  (const_int 0)])
> > > +	   (compare:CCFPE
> > > +	    (match_operand:GPF 2 "register_operand" "w")
> > > +	    (match_operand:GPF 3 "register_operand" "w"))
> > > +	  (match_operand 5 "immediate_operand")))]
> > > +  "TARGET_FLOAT"
> > > +  "fccmpe\\t%<s>2, %<s>3, %k5, %m4"
> > > +  [(set_attr "type" "fcmp<s>")]
> > > +)
> > > +
> > >  ;; Expansion of signed mod by a power of 2 using CSNEG.
> > >  ;; For x0 % n where n is a power of 2 produce:
> > >  ;; negs   x1, x0
> > > @@ -2794,7 +2824,7 @@
> > >    [(set_attr "type" "alus_sreg,alus_imm,alus_imm")]
> > >  )
> > >
> > > -(define_insn "*cmp<mode>"
> > > +(define_insn "fcmp<mode>"
> > >    [(set (reg:CCFP CC_REGNUM)
> > >          (compare:CCFP (match_operand:GPF 0 "register_operand" "w,w")
> > >  		      (match_operand:GPF 1 "aarch64_fp_compare_operand" "Y,w")))]
> > > @@ -2805,7 +2835,7 @@
> > >    [(set_attr "type" "fcmp<s>")]
> > >  )
> > >
> > > -(define_insn "*cmpe<mode>"
> > > +(define_insn "fcmpe<mode>"
> > >    [(set (reg:CCFPE CC_REGNUM)
> > >          (compare:CCFPE (match_operand:GPF 0 "register_operand" "w,w")
> > >  		       (match_operand:GPF 1 "aarch64_fp_compare_operand" "Y,w")))]
> > > diff --git a/gcc/testsuite/gcc.target/aarch64/ccmp_1.c b/gcc/testsuite/gcc.target/aarch64/ccmp_1.c
> > > new file mode 100644
> > > index 0000000..ef077e0
> > > --- /dev/null
> > > +++ b/gcc/testsuite/gcc.target/aarch64/ccmp_1.c
> > > @@ -0,0 +1,84 @@
> > > +/* { dg-do compile } */
> > > +/* { dg-options "-O2" } */
> > > +
> > > +int
> > > +f1 (int a)
> > > +{
> > > +  return a == 17 || a == 32;
> > > +}
> > > +
> > > +int
> > > +f2 (int a)
> > > +{
> > > +  return a == 33 || a == 18;
> > > +}
> > > +
> > > +int
> > > +f3 (int a, int b)
> > > +{
> > > +  return a == 19 && b == 34;
> > > +}
> > > +
> > > +int
> > > +f4 (int a, int b)
> > > +{
> > > +  return a == 35 && b == 20;
> > > +}
> > > +
> > > +int
> > > +f5 (int a)
> > > +{
> > > +  return a == 0 || a == 5;
> > > +}
> > > +
> > > +int
> > > +f6 (int a)
> > > +{
> > > +  return a == 6 || a == 0;
> > > +}
> > > +
> > > +int
> > > +f7 (int a, int b)
> > > +{
> > > +  return a == 0 && b == 7;
> > > +}
> > > +
> > > +int
> > > +f8 (int a, int b)
> > > +{
> > > +  return a == 9 && b == 0;
> > > +}
> > > +
> > > +int
> > > +f9 (float a, float b)
> > > +{
> > > +  return a < 0.0f && a > b;
> > > +}
> > > +
> > > +int
> > > +f10 (float a, float b)
> > > +{
> > > +  return a == b || b == 0.0f;
> > > +}
> > > +
> > > +int
> > > +f11 (double a, int b)
> > > +{
> > > +  return a < 0.0f && b == 30;
> > > +}
> > > +
> > > +int
> > > +f12 (double a, int b)
> > > +{
> > > +  return b == 31 || a == 0.0f;
> > > +}
> > > +
> > > +int
> > > +f13 (int a, int b)
> > > +{
> > > +  a += b;
> > > +  return a == 3 || a == 0;
> > > +}
> > > +
> > > +/* { dg-final { scan-assembler "fccmp\t" } } */
> > > +/* { dg-final { scan-assembler "fccmpe\t" } } */
> > > --
> > > 1.9.1
> >

Re: [PATCH 2/4 v2][AArch64] Add support for FCCMP

[James Greenhalgh]

On Tue, Dec 15, 2015 at 10:32:50AM +0000, Wilco Dijkstra wrote:
> ping
> 
> > -----Original Message-----
> > From: Wilco Dijkstra [mailto:Wilco.Dijkstra@arm.com]
> > Sent: 17 November 2015 18:36
> > To: gcc-patches@gcc.gnu.org
> > Subject: [PATCH 2/4 v2][AArch64] Add support for FCCMP
> > 
> > (v2 version removes 4 enums)
> > 
> > This patch adds support for FCCMP. This is trivial with the new CCMP representation - remove the restriction of FP in ccmp.c and add
> > FCCMP patterns. Add a test to ensure FCCMP/FCCMPE are emitted as expected.
> > 
> > OK for commit?

The AArch64 code-generation parts of this are OK, though please wait for
an OK on the ccmp.c changes before committing, and please revisit the
testcase.

Sorry that this took a long time to get to.

> > 
> > ChangeLog:
> > 2015-11-18  Wilco Dijkstra  <wdijkstr@arm.com>
> > 
> > 	* gcc/ccmp.c (ccmp_candidate_p): Remove integer-only restriction.

Drop the gcc/ from the paths here and below.

> > 	* gcc/config/aarch64/aarch64.md (fccmp<mode>): New pattern.
> > 	(fccmpe<mode>): Likewise.
> > 	(fcmp): Rename to fcmp and globalize pattern.
> > 	(fcmpe): Likewise.
> > 	* gcc/config/aarch64/aarch64.c (aarch64_gen_ccmp_first): Add FP support.
> > 	(aarch64_gen_ccmp_next): Add FP support.
> > 
> > gcc/testsuite/
> > 	* gcc.target/aarch64/ccmp_1.c: New testcase.

This testcase doesn't look very helpful to me. You only end up checking if
*any* of the tests compile to fccmp/fccmpe rather than *all* the tests. Should
this use a scan-assembler-times directive to count the number of times a
particular instruction appears?

Thanks,
James

> > ---
> >  gcc/ccmp.c                                |  6 ---
> >  gcc/config/aarch64/aarch64.c              | 24 +++++++++
> >  gcc/config/aarch64/aarch64.md             | 34 ++++++++++++-
> >  gcc/testsuite/gcc.target/aarch64/ccmp_1.c | 84 +++++++++++++++++++++++++++++++
> >  4 files changed, 140 insertions(+), 8 deletions(-)
> >  create mode 100644 gcc/testsuite/gcc.target/aarch64/ccmp_1.c
> > 
> > diff --git a/gcc/ccmp.c b/gcc/ccmp.c
> > index 58ac126..3698a7d 100644
> > --- a/gcc/ccmp.c
> > +++ b/gcc/ccmp.c
> > @@ -112,12 +112,6 @@ ccmp_candidate_p (gimple *g)
> >        || gimple_bb (gs0) != gimple_bb (g))
> >      return false;
> > 
> > -  if (!(INTEGRAL_TYPE_P (TREE_TYPE (gimple_assign_rhs1 (gs0)))
> > -       || POINTER_TYPE_P (TREE_TYPE (gimple_assign_rhs1 (gs0))))
> > -      || !(INTEGRAL_TYPE_P (TREE_TYPE (gimple_assign_rhs1 (gs1)))
> > -	   || POINTER_TYPE_P (TREE_TYPE (gimple_assign_rhs1 (gs1)))))
> > -    return false;
> > -
> >    tcode0 = gimple_assign_rhs_code (gs0);
> >    tcode1 = gimple_assign_rhs_code (gs1);
> >    if (TREE_CODE_CLASS (tcode0) == tcc_comparison
> > diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
> > index c8bee3b..db4d190 100644
> > --- a/gcc/config/aarch64/aarch64.c
> > +++ b/gcc/config/aarch64/aarch64.c
> > @@ -12398,6 +12398,18 @@ aarch64_gen_ccmp_first (rtx *prep_seq, rtx *gen_seq,
> >        icode = CODE_FOR_cmpdi;
> >        break;
> > 
> > +    case SFmode:
> > +      cmp_mode = SFmode;
> > +      cc_mode = aarch64_select_cc_mode ((rtx_code) code, op0, op1);
> > +      icode = cc_mode == CCFPEmode ? CODE_FOR_fcmpesf : CODE_FOR_fcmpsf;
> > +      break;
> > +
> > +    case DFmode:
> > +      cmp_mode = DFmode;
> > +      cc_mode = aarch64_select_cc_mode ((rtx_code) code, op0, op1);
> > +      icode = cc_mode == CCFPEmode ? CODE_FOR_fcmpedf : CODE_FOR_fcmpdf;
> > +      break;
> > +
> >      default:
> >        end_sequence ();
> >        return NULL_RTX;
> > @@ -12461,6 +12473,18 @@ aarch64_gen_ccmp_next (rtx *prep_seq, rtx *gen_seq, rtx prev, int cmp_code,
> >        icode = CODE_FOR_ccmpdi;
> >        break;
> > 
> > +    case SFmode:
> > +      cmp_mode = SFmode;
> > +      cc_mode = aarch64_select_cc_mode ((rtx_code) cmp_code, op0, op1);
> > +      icode = cc_mode == CCFPEmode ? CODE_FOR_fccmpesf : CODE_FOR_fccmpsf;
> > +      break;
> > +
> > +    case DFmode:
> > +      cmp_mode = DFmode;
> > +      cc_mode = aarch64_select_cc_mode ((rtx_code) cmp_code, op0, op1);
> > +      icode = cc_mode == CCFPEmode ? CODE_FOR_fccmpedf : CODE_FOR_fccmpdf;
> > +      break;
> > +
> >      default:
> >        end_sequence ();
> >        return NULL_RTX;
> > diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
> > index fab65c6..7d728b5 100644
> > --- a/gcc/config/aarch64/aarch64.md
> > +++ b/gcc/config/aarch64/aarch64.md
> > @@ -279,6 +279,36 @@
> >    [(set_attr "type" "alus_sreg,alus_imm,alus_imm")]
> >  )
> > 
> > +(define_insn "fccmp<mode>"
> > +  [(set (match_operand:CCFP 1 "cc_register" "")
> > +	(if_then_else:CCFP
> > +	  (match_operator 4 "aarch64_comparison_operator"
> > +	   [(match_operand 0 "cc_register" "")
> > +	    (const_int 0)])
> > +	  (compare:CCFP
> > +	    (match_operand:GPF 2 "register_operand" "w")
> > +	    (match_operand:GPF 3 "register_operand" "w"))
> > +	  (match_operand 5 "immediate_operand")))]
> > +  "TARGET_FLOAT"
> > +  "fccmp\\t%<s>2, %<s>3, %k5, %m4"
> > +  [(set_attr "type" "fcmp<s>")]
> > +)
> > +
> > +(define_insn "fccmpe<mode>"
> > +  [(set (match_operand:CCFPE 1 "cc_register" "")
> > +	 (if_then_else:CCFPE
> > +	  (match_operator 4 "aarch64_comparison_operator"
> > +	   [(match_operand 0 "cc_register" "")
> > +	  (const_int 0)])
> > +	   (compare:CCFPE
> > +	    (match_operand:GPF 2 "register_operand" "w")
> > +	    (match_operand:GPF 3 "register_operand" "w"))
> > +	  (match_operand 5 "immediate_operand")))]
> > +  "TARGET_FLOAT"
> > +  "fccmpe\\t%<s>2, %<s>3, %k5, %m4"
> > +  [(set_attr "type" "fcmp<s>")]
> > +)
> > +
> >  ;; Expansion of signed mod by a power of 2 using CSNEG.
> >  ;; For x0 % n where n is a power of 2 produce:
> >  ;; negs   x1, x0
> > @@ -2794,7 +2824,7 @@
> >    [(set_attr "type" "alus_sreg,alus_imm,alus_imm")]
> >  )
> > 
> > -(define_insn "*cmp<mode>"
> > +(define_insn "fcmp<mode>"
> >    [(set (reg:CCFP CC_REGNUM)
> >          (compare:CCFP (match_operand:GPF 0 "register_operand" "w,w")
> >  		      (match_operand:GPF 1 "aarch64_fp_compare_operand" "Y,w")))]
> > @@ -2805,7 +2835,7 @@
> >    [(set_attr "type" "fcmp<s>")]
> >  )
> > 
> > -(define_insn "*cmpe<mode>"
> > +(define_insn "fcmpe<mode>"
> >    [(set (reg:CCFPE CC_REGNUM)
> >          (compare:CCFPE (match_operand:GPF 0 "register_operand" "w,w")
> >  		       (match_operand:GPF 1 "aarch64_fp_compare_operand" "Y,w")))]
> > diff --git a/gcc/testsuite/gcc.target/aarch64/ccmp_1.c b/gcc/testsuite/gcc.target/aarch64/ccmp_1.c
> > new file mode 100644
> > index 0000000..ef077e0
> > --- /dev/null
> > +++ b/gcc/testsuite/gcc.target/aarch64/ccmp_1.c
> > @@ -0,0 +1,84 @@
> > +/* { dg-do compile } */
> > +/* { dg-options "-O2" } */
> > +
> > +int
> > +f1 (int a)
> > +{
> > +  return a == 17 || a == 32;
> > +}
> > +
> > +int
> > +f2 (int a)
> > +{
> > +  return a == 33 || a == 18;
> > +}
> > +
> > +int
> > +f3 (int a, int b)
> > +{
> > +  return a == 19 && b == 34;
> > +}
> > +
> > +int
> > +f4 (int a, int b)
> > +{
> > +  return a == 35 && b == 20;
> > +}
> > +
> > +int
> > +f5 (int a)
> > +{
> > +  return a == 0 || a == 5;
> > +}
> > +
> > +int
> > +f6 (int a)
> > +{
> > +  return a == 6 || a == 0;
> > +}
> > +
> > +int
> > +f7 (int a, int b)
> > +{
> > +  return a == 0 && b == 7;
> > +}
> > +
> > +int
> > +f8 (int a, int b)
> > +{
> > +  return a == 9 && b == 0;
> > +}
> > +
> > +int
> > +f9 (float a, float b)
> > +{
> > +  return a < 0.0f && a > b;
> > +}
> > +
> > +int
> > +f10 (float a, float b)
> > +{
> > +  return a == b || b == 0.0f;
> > +}
> > +
> > +int
> > +f11 (double a, int b)
> > +{
> > +  return a < 0.0f && b == 30;
> > +}
> > +
> > +int
> > +f12 (double a, int b)
> > +{
> > +  return b == 31 || a == 0.0f;
> > +}
> > +
> > +int
> > +f13 (int a, int b)
> > +{
> > +  a += b;
> > +  return a == 3 || a == 0;
> > +}
> > +
> > +/* { dg-final { scan-assembler "fccmp\t" } } */
> > +/* { dg-final { scan-assembler "fccmpe\t" } } */
> > --
> > 1.9.1
> 

RE: [PATCH 2/4 v2][AArch64] Add support for FCCMP

[Wilco Dijkstra]

ping

> -----Original Message-----
> From: Wilco Dijkstra [mailto:Wilco.Dijkstra@arm.com]
> Sent: 17 November 2015 18:36
> To: gcc-patches@gcc.gnu.org
> Subject: [PATCH 2/4 v2][AArch64] Add support for FCCMP
> 
> (v2 version removes 4 enums)
> 
> This patch adds support for FCCMP. This is trivial with the new CCMP representation - remove the restriction of FP in ccmp.c and add
> FCCMP patterns. Add a test to ensure FCCMP/FCCMPE are emitted as expected.
> 
> OK for commit?
> 
> ChangeLog:
> 2015-11-18  Wilco Dijkstra  <wdijkstr@arm.com>
> 
> 	* gcc/ccmp.c (ccmp_candidate_p): Remove integer-only restriction.
> 	* gcc/config/aarch64/aarch64.md (fccmp<mode>): New pattern.
> 	(fccmpe<mode>): Likewise.
> 	(fcmp): Rename to fcmp and globalize pattern.
> 	(fcmpe): Likewise.
> 	* gcc/config/aarch64/aarch64.c (aarch64_gen_ccmp_first): Add FP support.
> 	(aarch64_gen_ccmp_next): Add FP support.
> 
> gcc/testsuite/
> 	* gcc.target/aarch64/ccmp_1.c: New testcase.
> 
> 
> ---
>  gcc/ccmp.c                                |  6 ---
>  gcc/config/aarch64/aarch64.c              | 24 +++++++++
>  gcc/config/aarch64/aarch64.md             | 34 ++++++++++++-
>  gcc/testsuite/gcc.target/aarch64/ccmp_1.c | 84 +++++++++++++++++++++++++++++++
>  4 files changed, 140 insertions(+), 8 deletions(-)
>  create mode 100644 gcc/testsuite/gcc.target/aarch64/ccmp_1.c
> 
> diff --git a/gcc/ccmp.c b/gcc/ccmp.c
> index 58ac126..3698a7d 100644
> --- a/gcc/ccmp.c
> +++ b/gcc/ccmp.c
> @@ -112,12 +112,6 @@ ccmp_candidate_p (gimple *g)
>        || gimple_bb (gs0) != gimple_bb (g))
>      return false;
> 
> -  if (!(INTEGRAL_TYPE_P (TREE_TYPE (gimple_assign_rhs1 (gs0)))
> -       || POINTER_TYPE_P (TREE_TYPE (gimple_assign_rhs1 (gs0))))
> -      || !(INTEGRAL_TYPE_P (TREE_TYPE (gimple_assign_rhs1 (gs1)))
> -	   || POINTER_TYPE_P (TREE_TYPE (gimple_assign_rhs1 (gs1)))))
> -    return false;
> -
>    tcode0 = gimple_assign_rhs_code (gs0);
>    tcode1 = gimple_assign_rhs_code (gs1);
>    if (TREE_CODE_CLASS (tcode0) == tcc_comparison
> diff --git a/gcc/config/aarch64/aarch64.c b/gcc/config/aarch64/aarch64.c
> index c8bee3b..db4d190 100644
> --- a/gcc/config/aarch64/aarch64.c
> +++ b/gcc/config/aarch64/aarch64.c
> @@ -12398,6 +12398,18 @@ aarch64_gen_ccmp_first (rtx *prep_seq, rtx *gen_seq,
>        icode = CODE_FOR_cmpdi;
>        break;
> 
> +    case SFmode:
> +      cmp_mode = SFmode;
> +      cc_mode = aarch64_select_cc_mode ((rtx_code) code, op0, op1);
> +      icode = cc_mode == CCFPEmode ? CODE_FOR_fcmpesf : CODE_FOR_fcmpsf;
> +      break;
> +
> +    case DFmode:
> +      cmp_mode = DFmode;
> +      cc_mode = aarch64_select_cc_mode ((rtx_code) code, op0, op1);
> +      icode = cc_mode == CCFPEmode ? CODE_FOR_fcmpedf : CODE_FOR_fcmpdf;
> +      break;
> +
>      default:
>        end_sequence ();
>        return NULL_RTX;
> @@ -12461,6 +12473,18 @@ aarch64_gen_ccmp_next (rtx *prep_seq, rtx *gen_seq, rtx prev, int cmp_code,
>        icode = CODE_FOR_ccmpdi;
>        break;
> 
> +    case SFmode:
> +      cmp_mode = SFmode;
> +      cc_mode = aarch64_select_cc_mode ((rtx_code) cmp_code, op0, op1);
> +      icode = cc_mode == CCFPEmode ? CODE_FOR_fccmpesf : CODE_FOR_fccmpsf;
> +      break;
> +
> +    case DFmode:
> +      cmp_mode = DFmode;
> +      cc_mode = aarch64_select_cc_mode ((rtx_code) cmp_code, op0, op1);
> +      icode = cc_mode == CCFPEmode ? CODE_FOR_fccmpedf : CODE_FOR_fccmpdf;
> +      break;
> +
>      default:
>        end_sequence ();
>        return NULL_RTX;
> diff --git a/gcc/config/aarch64/aarch64.md b/gcc/config/aarch64/aarch64.md
> index fab65c6..7d728b5 100644
> --- a/gcc/config/aarch64/aarch64.md
> +++ b/gcc/config/aarch64/aarch64.md
> @@ -279,6 +279,36 @@
>    [(set_attr "type" "alus_sreg,alus_imm,alus_imm")]
>  )
> 
> +(define_insn "fccmp<mode>"
> +  [(set (match_operand:CCFP 1 "cc_register" "")
> +	(if_then_else:CCFP
> +	  (match_operator 4 "aarch64_comparison_operator"
> +	   [(match_operand 0 "cc_register" "")
> +	    (const_int 0)])
> +	  (compare:CCFP
> +	    (match_operand:GPF 2 "register_operand" "w")
> +	    (match_operand:GPF 3 "register_operand" "w"))
> +	  (match_operand 5 "immediate_operand")))]
> +  "TARGET_FLOAT"
> +  "fccmp\\t%<s>2, %<s>3, %k5, %m4"
> +  [(set_attr "type" "fcmp<s>")]
> +)
> +
> +(define_insn "fccmpe<mode>"
> +  [(set (match_operand:CCFPE 1 "cc_register" "")
> +	 (if_then_else:CCFPE
> +	  (match_operator 4 "aarch64_comparison_operator"
> +	   [(match_operand 0 "cc_register" "")
> +	  (const_int 0)])
> +	   (compare:CCFPE
> +	    (match_operand:GPF 2 "register_operand" "w")
> +	    (match_operand:GPF 3 "register_operand" "w"))
> +	  (match_operand 5 "immediate_operand")))]
> +  "TARGET_FLOAT"
> +  "fccmpe\\t%<s>2, %<s>3, %k5, %m4"
> +  [(set_attr "type" "fcmp<s>")]
> +)
> +
>  ;; Expansion of signed mod by a power of 2 using CSNEG.
>  ;; For x0 % n where n is a power of 2 produce:
>  ;; negs   x1, x0
> @@ -2794,7 +2824,7 @@
>    [(set_attr "type" "alus_sreg,alus_imm,alus_imm")]
>  )
> 
> -(define_insn "*cmp<mode>"
> +(define_insn "fcmp<mode>"
>    [(set (reg:CCFP CC_REGNUM)
>          (compare:CCFP (match_operand:GPF 0 "register_operand" "w,w")
>  		      (match_operand:GPF 1 "aarch64_fp_compare_operand" "Y,w")))]
> @@ -2805,7 +2835,7 @@
>    [(set_attr "type" "fcmp<s>")]
>  )
> 
> -(define_insn "*cmpe<mode>"
> +(define_insn "fcmpe<mode>"
>    [(set (reg:CCFPE CC_REGNUM)
>          (compare:CCFPE (match_operand:GPF 0 "register_operand" "w,w")
>  		       (match_operand:GPF 1 "aarch64_fp_compare_operand" "Y,w")))]
> diff --git a/gcc/testsuite/gcc.target/aarch64/ccmp_1.c b/gcc/testsuite/gcc.target/aarch64/ccmp_1.c
> new file mode 100644
> index 0000000..ef077e0
> --- /dev/null
> +++ b/gcc/testsuite/gcc.target/aarch64/ccmp_1.c
> @@ -0,0 +1,84 @@
> +/* { dg-do compile } */
> +/* { dg-options "-O2" } */
> +
> +int
> +f1 (int a)
> +{
> +  return a == 17 || a == 32;
> +}
> +
> +int
> +f2 (int a)
> +{
> +  return a == 33 || a == 18;
> +}
> +
> +int
> +f3 (int a, int b)
> +{
> +  return a == 19 && b == 34;
> +}
> +
> +int
> +f4 (int a, int b)
> +{
> +  return a == 35 && b == 20;
> +}
> +
> +int
> +f5 (int a)
> +{
> +  return a == 0 || a == 5;
> +}
> +
> +int
> +f6 (int a)
> +{
> +  return a == 6 || a == 0;
> +}
> +
> +int
> +f7 (int a, int b)
> +{
> +  return a == 0 && b == 7;
> +}
> +
> +int
> +f8 (int a, int b)
> +{
> +  return a == 9 && b == 0;
> +}
> +
> +int
> +f9 (float a, float b)
> +{
> +  return a < 0.0f && a > b;
> +}
> +
> +int
> +f10 (float a, float b)
> +{
> +  return a == b || b == 0.0f;
> +}
> +
> +int
> +f11 (double a, int b)
> +{
> +  return a < 0.0f && b == 30;
> +}
> +
> +int
> +f12 (double a, int b)
> +{
> +  return b == 31 || a == 0.0f;
> +}
> +
> +int
> +f13 (int a, int b)
> +{
> +  a += b;
> +  return a == 3 || a == 0;
> +}
> +
> +/* { dg-final { scan-assembler "fccmp\t" } } */
> +/* { dg-final { scan-assembler "fccmpe\t" } } */
> --
> 1.9.1