From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 128164 invoked by alias); 16 Dec 2015 12:04:38 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 128035 invoked by uid 89); 16 Dec 2015 12:04:38 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=0.9 required=5.0 tests=AWL,BAYES_50,KAM_LAZY_DOMAIN_SECURITY,KAM_LOTSOFHASH,T_RP_MATCHES_RCVD autolearn=no version=3.3.2 X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 16 Dec 2015 12:04:35 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id BB555600; Wed, 16 Dec 2015 04:04:09 -0800 (PST) Received: from SHAWIN202 (unknown [10.164.12.31]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 82F803F308; Wed, 16 Dec 2015 04:04:31 -0800 (PST) From: "Thomas Preud'homme" To: "'Ramana Radhakrishnan'" , "Richard Earnshaw" , "Kyrylo Tkachov" , "gcc-patches" Cc: "Jasmin J." Subject: [PATCH, ARM, 3/3] Add multilib support for bare-metal ARM architectures Date: Wed, 16 Dec 2015 12:04:00 -0000 Message-ID: <000601d137f9$ec63c180$c52b4480$@foss.arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-SW-Source: 2015-12/txt/msg01586.txt.bz2 Hi Ramana, As suggested in your initial answer to this thread, we updated the multilib= patch provided in ARM's embedded branch to be up-to-date with regards to s= upported CPUs in GCC. As to the need to modify Makefile.in and configure.ac= , this is because the patch aims to let control to the user as to what mult= ilib should be built. To this effect, it takes a list of architecture at co= nfigure time and that list needs to be passed down to t-baremetal Makefile = to set the multilib variables appropriately. ChangeLog entry is as follows: *** gcc/ChangeLog *** 2015-12-15 Thomas Preud'homme * Makefile.in (with_multilib_list): New variables substituted by configure. * config.gcc: Handle bare-metal multilibs in --with-multilib-list option. * config/arm/t-baremetal: New file. * configure.ac (with_multilib_list): New AC_SUBST. * configure: Regenerate. * doc/install.texi (--with-multilib-list): Update description for arm*-*-* targets to mention bare-metal multilibs. diff --git a/gcc/Makefile.in b/gcc/Makefile.in index 1f698798aa2df3f44d6b3a478bb4bf48e9fa7372..18b790afa114aa7580be0662d3a= c9ffbc94e919d 100644 --- a/gcc/Makefile.in +++ b/gcc/Makefile.in @@ -546,6 +546,7 @@ lang_opt_files=3D@lang_opt_files@ $(srcdir)/c-family/c.= opt $(srcdir)/common.opt lang_specs_files=3D@lang_specs_files@ lang_tree_files=3D@lang_tree_files@ target_cpu_default=3D@target_cpu_default@ +with_multilib_list=3D@with_multilib_list@ OBJC_BOEHM_GC=3D@objc_boehm_gc@ extra_modes_file=3D@extra_modes_file@ extra_opt_files=3D@extra_opt_files@ diff --git a/gcc/config.gcc b/gcc/config.gcc index af948b5e203f6b4f53dfca38e9d02d060d00c97b..d8098ed3cefacd00cb10590db1e= c86d48e9fcdbc 100644 --- a/gcc/config.gcc +++ b/gcc/config.gcc @@ -3787,15 +3787,25 @@ case "${target}" in default) ;; *) - echo "Error: --with-multilib-list=3D${with_multilib_list} not supporte= d." 1>&2 - exit 1 + for arm_multilib in ${arm_multilibs}; do + case ${arm_multilib} in + armv6-m | armv7-m | armv7e-m | armv7-r | armv8-m.base | armv8-m.main) + tmake_profile_file=3D"arm/t-baremetal" + ;; + *) + echo "Error: --with-multilib-list=3D${with_multilib_list} not suppor= ted." 1>&2 + exit 1 + ;; + esac + done ;; esac =20 if test "x${tmake_profile_file}" !=3D x ; then - # arm/t-aprofile is only designed to work - # without any with-cpu, with-arch, with-mode, - # with-fpu or with-float options. + # arm/t-aprofile and arm/t-baremetal are only + # designed to work without any with-cpu, + # with-arch, with-mode, with-fpu or with-float + # options. if test "x$with_arch" !=3D x \ || test "x$with_cpu" !=3D x \ || test "x$with_float" !=3D x \ diff --git a/gcc/config/arm/t-baremetal b/gcc/config/arm/t-baremetal new file mode 100644 index 0000000000000000000000000000000000000000..ffd29815e6ec22c747e77747ed9= b69e0ae21b63a --- /dev/null +++ b/gcc/config/arm/t-baremetal @@ -0,0 +1,130 @@ +# A set of predefined MULTILIB which can be used for different ARM targets. +# Via the configure option --with-multilib-list, user can customize the +# final MULTILIB implementation. + +comma :=3D , + +with_multilib_list :=3D $(subst $(comma), ,$(with_multilib_list)))) + +MULTILIB_OPTIONS =3D mthumb/marm +MULTILIB_DIRNAMES =3D thumb arm +MULTILIB_OPTIONS +=3D march=3Darmv6s-m/march=3Darmv7-m/march=3Darmv7e-m/m= arch=3Darmv7/march=3Darmv8-m.base/march=3Darmv8-m.main +MULTILIB_DIRNAMES +=3D armv6-m armv7-m armv7e-m armv7-ar armv8-m.base armv= 8-m.main +MULTILIB_OPTIONS +=3D mfloat-abi=3Dsoftfp/mfloat-abi=3Dhard +MULTILIB_DIRNAMES +=3D softfp fpu +MULTILIB_OPTIONS +=3D mfpu=3Dfpv5-sp-d16/mfpu=3Dfpv5-d16/mfpu=3Dfpv4-sp-d= 16/mfpu=3Dvfpv3-d16 +MULTILIB_DIRNAMES +=3D fpv5-sp-d16 fpv5-d16 fpv4-sp-d16 vfpv3-d16 + +MULTILIB_MATCHES =3D march?armv6s-m=3Dmcpu?cortex-m0 +MULTILIB_MATCHES +=3D march?armv6s-m=3Dmcpu?cortex-m0.small-multiply +MULTILIB_MATCHES +=3D march?armv6s-m=3Dmcpu?cortex-m0plus +MULTILIB_MATCHES +=3D march?armv6s-m=3Dmcpu?cortex-m0plus.small-multiply +MULTILIB_MATCHES +=3D march?armv6s-m=3Dmcpu?cortex-m1 +MULTILIB_MATCHES +=3D march?armv6s-m=3Dmcpu?cortex-m1.small-multiply +MULTILIB_MATCHES +=3D march?armv6s-m=3Dmarch?armv6-m +MULTILIB_MATCHES +=3D march?armv7-m=3Dmcpu?cortex-m3 +MULTILIB_MATCHES +=3D march?armv7e-m=3Dmcpu?cortex-m4 +MULTILIB_MATCHES +=3D march?armv7e-m=3Dmcpu?cortex-m7 +MULTILIB_MATCHES +=3D march?armv7e-m=3Dmcpu?marvell-pj4 +MULTILIB_MATCHES +=3D march?armv7=3Dmarch?armv7-r +MULTILIB_MATCHES +=3D march?armv7=3Dmarch?armv7-a +MULTILIB_MATCHES +=3D march?armv7=3Dmarch?armv8-a +MULTILIB_MATCHES +=3D march?armv7=3Dmcpu?cortex-r4 +MULTILIB_MATCHES +=3D march?armv7=3Dmcpu?cortex-r4f +MULTILIB_MATCHES +=3D march?armv7=3Dmcpu?cortex-r5 +MULTILIB_MATCHES +=3D march?armv7=3Dmcpu?cortex-r7 +MULTILIB_MATCHES +=3D march?armv7=3Dmcpu?generic-armv7-a +MULTILIB_MATCHES +=3D march?armv7=3Dmcpu?cortex-a5 +MULTILIB_MATCHES +=3D march?armv7=3Dmcpu?cortex-a7 +MULTILIB_MATCHES +=3D march?armv7=3Dmcpu?cortex-a8 +MULTILIB_MATCHES +=3D march?armv7=3Dmcpu?cortex-a9 +MULTILIB_MATCHES +=3D march?armv7=3Dmcpu?cortex-a12 +MULTILIB_MATCHES +=3D march?armv7=3Dmcpu?cortex-a15 +MULTILIB_MATCHES +=3D march?armv7=3Dmcpu?cortex-a17 +MULTILIB_MATCHES +=3D march?armv7=3Dmcpu?cortex-a15.cortex-a7 +MULTILIB_MATCHES +=3D march?armv7=3Dmcpu?cortex-a17.cortex-a7 +MULTILIB_MATCHES +=3D march?armv7=3Dmcpu?cortex-a53 +MULTILIB_MATCHES +=3D march?armv7=3Dmcpu?cortex-a57 +MULTILIB_MATCHES +=3D march?armv7=3Dmcpu?cortex-a72 +MULTILIB_MATCHES +=3D march?armv7=3Dmcpu?exynos-m1 +MULTILIB_MATCHES +=3D march?armv7=3Dmcpu?xgene1 +MULTILIB_MATCHES +=3D march?armv7=3Dmcpu?cortex-a57.cortex-a53 +MULTILIB_MATCHES +=3D march?armv7=3Dmcpu?cortex-a72.cortex-a53 +MULTILIB_MATCHES +=3D mfpu?vfpv3-d16=3Dmfpu?vfpv3 +MULTILIB_MATCHES +=3D mfpu?vfpv3-d16=3Dmfpu?vfpv3-fp16 +MULTILIB_MATCHES +=3D mfpu?vfpv3-d16=3Dmfpu?vfpv3-d16-fp16 +MULTILIB_MATCHES +=3D mfpu?vfpv3-d16=3Dmfpu?vfpv3xd +MULTILIB_MATCHES +=3D mfpu?vfpv3-d16=3Dmfpu?vfpv3xd-fp16 +MULTILIB_MATCHES +=3D mfpu?vfpv3-d16=3Dmfpu?vfpv4 +MULTILIB_MATCHES +=3D mfpu?vfpv3-d16=3Dmfpu?vfpv4-d16 +MULTILIB_MATCHES +=3D mfpu?vfpv3-d16=3Dmfpu?neon +MULTILIB_MATCHES +=3D mfpu?vfpv3-d16=3Dmfpu?neon-fp16 +MULTILIB_MATCHES +=3D mfpu?vfpv3-d16=3Dmfpu?neon-vfpv4 + +MULTILIB_EXCEPTIONS =3D +MULTILIB_REUSE =3D + +MULTILIB_REQUIRED =3D mthumb +MULTILIB_REQUIRED +=3D marm +MULTILIB_REQUIRED +=3D mfloat-abi=3Dhard + +MULTILIB_OSDIRNAMES =3D mthumb=3D!thumb +MULTILIB_OSDIRNAMES +=3D marm=3D!arm +MULTILIB_OSDIRNAMES +=3D mfloat-abi.hard=3D!fpu + +ifneq (,$(findstring armv6-m,$(with_multilib_list))) +MULTILIB_REQUIRED +=3D mthumb/march=3Darmv6s-m +MULTILIB_OSDIRNAMES +=3D mthumb/march.armv6s-m=3D!armv6-m +endif + +ifneq (,$(findstring armv8-m.base,$(with_multilib_list))) +MULTILIB_REQUIRED +=3D mthumb/march=3Darmv8-m.base +MULTILIB_OSDIRNAMES +=3D mthumb/march.armv8-m.base=3D!armv8-m.base +endif + +ifneq (,$(findstring armv7-m,$(with_multilib_list))) +MULTILIB_REQUIRED +=3D mthumb/march=3Darmv7-m +MULTILIB_OSDIRNAMES +=3D mthumb/march.armv7-m=3D!armv7-m +endif + +ifneq (,$(findstring armv7e-m,$(with_multilib_list))) +MULTILIB_REQUIRED +=3D mthumb/march=3Darmv7e-m +MULTILIB_REQUIRED +=3D mthumb/march=3Darmv7e-m/mfloat-abi=3Dsoftfp/mfpu= =3Dfpv4-sp-d16 +MULTILIB_REQUIRED +=3D mthumb/march=3Darmv7e-m/mfloat-abi=3Dhard/mfpu=3D= fpv4-sp-d16 +MULTILIB_REQUIRED +=3D mthumb/march=3Darmv7e-m/mfloat-abi=3Dsoftfp/mfpu= =3Dfpv5-d16 +MULTILIB_REQUIRED +=3D mthumb/march=3Darmv7e-m/mfloat-abi=3Dhard/mfpu=3D= fpv5-d16 +MULTILIB_REQUIRED +=3D mthumb/march=3Darmv7e-m/mfloat-abi=3Dsoftfp/mfpu= =3Dfpv5-sp-d16 +MULTILIB_REQUIRED +=3D mthumb/march=3Darmv7e-m/mfloat-abi=3Dhard/mfpu=3D= fpv5-sp-d16 +MULTILIB_OSDIRNAMES +=3D mthumb/march.armv7e-m=3D!armv7e-m +MULTILIB_OSDIRNAMES +=3D mthumb/march.armv7e-m/mfloat-abi.hard/mfpu.fpv4-s= p-d16=3D!armv7e-m/fpu +MULTILIB_OSDIRNAMES +=3D mthumb/march.armv7e-m/mfloat-abi.softfp/mfpu.fpv4= -sp-d16=3D!armv7e-m/softfp +MULTILIB_OSDIRNAMES +=3D mthumb/march.armv7e-m/mfloat-abi.hard/mfpu.fpv5-d= 16=3D!armv7e-m/fpu/fpv5-d16 +MULTILIB_OSDIRNAMES +=3D mthumb/march.armv7e-m/mfloat-abi.softfp/mfpu.fpv5= -d16=3D!armv7e-m/softfp/fpv5-d16 +MULTILIB_OSDIRNAMES +=3D mthumb/march.armv7e-m/mfloat-abi.hard/mfpu.fpv5-s= p-d16=3D!armv7e-m/fpu/fpv5-sp-d16 +MULTILIB_OSDIRNAMES +=3D mthumb/march.armv7e-m/mfloat-abi.softfp/mfpu.fpv5= -sp-d16=3D!armv7e-m/softfp/fpv5-sp-d16 +endif + +ifneq (,$(findstring armv8-m.main,$(with_multilib_list))) +MULTILIB_REQUIRED +=3D mthumb/march=3Darmv8-m.main +MULTILIB_REQUIRED +=3D mthumb/march=3Darmv8-m.main/mfloat-abi=3Dsoftfp/m= fpu=3Dfpv5-d16 +MULTILIB_REQUIRED +=3D mthumb/march=3Darmv8-m.main/mfloat-abi=3Dhard/mfp= u=3Dfpv5-d16 +MULTILIB_REQUIRED +=3D mthumb/march=3Darmv8-m.main/mfloat-abi=3Dsoftfp/m= fpu=3Dfpv5-sp-d16 +MULTILIB_REQUIRED +=3D mthumb/march=3Darmv8-m.main/mfloat-abi=3Dhard/mfp= u=3Dfpv5-sp-d16 +MULTILIB_OSDIRNAMES +=3D mthumb/march.armv8-m.main=3D!armv8-m.main +MULTILIB_OSDIRNAMES +=3D mthumb/march.armv8-m.main/mfloat-abi.hard/mfpu.fp= v5-d16=3D!armv8-m.main/fpu/fpv5-d16 +MULTILIB_OSDIRNAMES +=3D mthumb/march.armv8-m.main/mfloat-abi.softfp/mfpu.= fpv5-d16=3D!armv8-m.main/softfp/fpv5-d16 +MULTILIB_OSDIRNAMES +=3D mthumb/march.armv8-m.main/mfloat-abi.hard/mfpu.fp= v5-sp-d16=3D!armv8-m.main/fpu/fpv5-sp-d16 +MULTILIB_OSDIRNAMES +=3D mthumb/march.armv8-m.main/mfloat-abi.softfp/mfpu.= fpv5-sp-d16=3D!armv8-m.main/softfp/fpv5-sp-d16 +endif + +ifneq (,$(filter armv7 armv7-r armv7-a,$(with_multilib_list))) +MULTILIB_REQUIRED +=3D mthumb/march=3Darmv7 +MULTILIB_REQUIRED +=3D mthumb/march=3Darmv7/mfloat-abi=3Dsoftfp/mfpu=3Dv= fpv3-d16 +MULTILIB_REQUIRED +=3D mthumb/march=3Darmv7/mfloat-abi=3Dhard/mfpu=3Dvfp= v3-d16 +MULTILIB_OSDIRNAMES +=3D mthumb/march.armv7=3D!armv7-ar/thumb +MULTILIB_OSDIRNAMES +=3D mthumb/march.armv7/mfloat-abi.hard/mfpu.vfpv3-d16= =3D!armv7-ar/thumb/fpu +MULTILIB_OSDIRNAMES +=3D mthumb/march.armv7/mfloat-abi.softfp/mfpu.vfpv3-d= 16=3D!armv7-ar/thumb/softfp +MULTILIB_REUSE +=3D mthumb/march.armv7=3Dmarm/march.armv7 +MULTILIB_REUSE +=3D mthumb/march.armv7/mfloat-abi.softfp/mfpu.vfpv3-d= 16=3Dmarm/march.armv7/mfloat-abi.softfp/mfpu.vfpv3-d16 +MULTILIB_REUSE +=3D mthumb/march.armv7/mfloat-abi.hard/mfpu.vfpv3-d16= =3Dmarm/march.armv7/mfloat-abi.hard/mfpu.vfpv3-d16 +endif diff --git a/gcc/configure b/gcc/configure index 23f92c3ceeb4c2e171f0cf7f83346b7575e134c0..e55125cfb6e6a79e2ed3c274e05= d9d420a220d62 100755 --- a/gcc/configure +++ b/gcc/configure @@ -767,6 +767,7 @@ LN LN_S AWK SET_MAKE +with_multilib_list accel_dir_suffix real_target_noncanonical enable_as_accelerator @@ -7730,6 +7731,7 @@ else fi =20 =20 + # ------------------------- # Checks for other programs # ------------------------- diff --git a/gcc/configure.ac b/gcc/configure.ac index a2caf298d3302a2be3bfebd192101a94df7d1b65..408f772578cd5ef65310a26f6d6= 5c3a82f3533a8 100644 --- a/gcc/configure.ac +++ b/gcc/configure.ac @@ -960,6 +960,7 @@ AC_ARG_WITH(multilib-list, [AS_HELP_STRING([--with-multilib-list], [select multilibs (AArch64, SH and= x86-64 only)])], :, with_multilib_list=3Ddefault) +AC_SUBST(with_multilib_list) =20 # ------------------------- # Checks for other programs diff --git a/gcc/doc/install.texi b/gcc/doc/install.texi index 50d6133794874c6b5ec7e2b2c947c991fadbb3a4..c6d65b177696bbf897dc0dcc7dc= 25ea3777ac6fa 100644 --- a/gcc/doc/install.texi +++ b/gcc/doc/install.texi @@ -1106,14 +1106,23 @@ Currently only implemented for arm*-*-*, sh*-*-* an= d x86-64-*-linux*. =20 @table @code @item arm*-*-* -@var{list} is either @code{default} or @code{aprofile}. Specifying -@code{default} is equivalent to omitting this option while specifying -@code{aprofile} builds multilibs for each combination of ISA (@code{-marm}= or -@code{-mthumb}), architecture (@code{-march=3Darmv7-a}, @code{-march=3Darm= v7ve}, -or @code{-march=3Darmv8-a}), FPU available (none, @code{-mfpu=3Dvfpv3-d16}, -@code{neon}, @code{vfpv4-d16}, @code{neon-vfpv4} or @code{neon-fp-armv8} -depending on architecture) and floating-point ABI (@code{-mfloat-abi=3Dsof= tfp} -or @code{-mfloat-abi=3Dhard}). +@var{list} is one of: + +@itemize @bullet + @item @code{default} + @item @code{aprofile} + @item any combination of @code{armv6-m}, @code{armv7-m}, @code{armv7e-m}, + @code{armv7-r}, @code{armv8-m.base} and @code{armv8-m.main} +@end itemize + +Specifying @code{default} is equivalent to omitting this option while +specifying @code{aprofile} builds multilibs for each combination of ISA +(@code{-marm} or @code{-mthumb}), architecture (@code{-march=3Darmv7-a}, +@code{-march=3Darmv7ve}, or @code{-march=3Darmv8-a}), FPU available (none, +@code{-mfpu=3Dvfpv3-d16}, @code{neon}, @code{vfpv4-d16}, @code{neon-vfpv4}= or +@code{neon-fp-armv8} depending on architecture) and floating-point ABI +(@code{-mfloat-abi=3Dsoftfp} or @code{-mfloat-abi=3Dhard}). The last opti= on +specifies a list of bare-metal multilibs that must be built. =20 @item sh*-*-* @var{list} is a comma separated list of CPU names. These must be of the Is this ok for trunk? Best regards, Thomas > -----Original Message----- > From: gcc-patches-owner@gcc.gnu.org [mailto:gcc-patches- > owner@gcc.gnu.org] On Behalf Of Ramana Radhakrishnan > Sent: Wednesday, November 04, 2015 3:47 PM > To: Jasmin J. > Cc: gcc-patches > Subject: Re: [PATCH] Add support for ARM embedded multilibs >=20 > On Wed, Nov 4, 2015 at 12:29 AM, Jasmin J. wrote: >=20 > > >=20 > Thank you for your patch - In this case before you make any more > changes to this patch - comparing your patch and Terry's patch here > https://gcc.gnu.org/ml/gcc-patches/2014-05/msg00729.html shows no > real > differences, I would like to ask if you have a copyright assignment > on file with the FSF - Please also read > https://gcc.gnu.org/contribute.html for more context on this. >=20 > How was your patch tested - see for example how I added t-aprofile to > the backend and the kind of testing it underwent - I would prefer > something like that to be done for all the cpus listed in t-rmprofile > (https://gcc.gnu.org/ml/gcc-patches/2013-10/msg00659.html). >=20 > > Ported from svn://gcc.gnu.org/svn/gcc/branches/ARM/embedded- > 4_9-branch > > > > * config.gcc (--with-multilib-list): Accept arm embedded cores. > > * configure.ac (with_multilib_list): Export for being used in arm > > embedded multilib fragment. >=20 > This is already being used in config.gcc - why do you need this > additional hunk ? >=20 > > * configure: Regenerated. > > * Makefile.in (with_multilib_list): Import for being used in > > multilib fragment. >=20 > Again why ? >=20 > > * config/arm/t-rmprofile: New multilib fragment for arm embedded > > cores. >=20 > New file is sufficient here in the Changelog entry. >=20 >=20 > The t-rmprofile file will need updating to newer values for -mcpu and > march as well as comments up top to explain what multilibs are being > built . >=20 > Ramana