* [AARCH64-4.7] Fix constraint and attribute for logical immediate instructions
@ 2012-10-17 14:30 Sofiane Naci
0 siblings, 0 replies; only message in thread
From: Sofiane Naci @ 2012-10-17 14:30 UTC (permalink / raw)
To: gcc-patches
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Hi,
I've just committed the attached patch on ARM/AArch64-4.7 branch.
It fixes a constraint and a scheduling attribute for the<optab><mode>3
pattern.
Thanks
Sofiane
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Index: gcc/ChangeLog.aarch64
===================================================================
--- gcc/ChangeLog.aarch64 (revision 192534)
+++ gcc/ChangeLog.aarch64 (working copy)
@@ -1,3 +1,9 @@
+2012-10-17 Sofiane Naci <sofiane.naci@arm.com>
+
+ * config/aarch64/aarch64.md (<optab><mode>3): Update constraint
+ for operand 0.
+ Update scheduling attribute for the second alternative.
+
2012-10-16 Tejas Belagod <tejas.belagod@arm.com>
* config/aarch64/arm_neon.h (vmla_lane_f32, vmla_lane_s16,
Index: gcc/config/aarch64/aarch64.md
===================================================================
--- gcc/config/aarch64/aarch64.md (revision 192534)
+++ gcc/config/aarch64/aarch64.md (working copy)
@@ -1995,12 +1995,12 @@
;; -------------------------------------------------------------------
(define_insn "<optab><mode>3"
- [(set (match_operand:GPI 0 "register_operand" "=r,r")
+ [(set (match_operand:GPI 0 "register_operand" "=r,rk")
(LOGICAL:GPI (match_operand:GPI 1 "register_operand" "%r,r")
(match_operand:GPI 2 "aarch64_logical_operand" "r,<lconst>")))]
""
"<logical>\\t%<w>0, %<w>1, %<w>2"
- [(set_attr "v8type" "logic")
+ [(set_attr "v8type" "logic,logic_imm")
(set_attr "mode" "<MODE>")])
(define_insn "*<LOGICAL:optab>_<SHIFT:optab><mode>3"
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2012-10-17 14:30 [AARCH64-4.7] Fix constraint and attribute for logical immediate instructions Sofiane Naci
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