From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 56370 invoked by alias); 12 Jan 2016 09:25:23 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 56358 invoked by uid 89); 12 Jan 2016 09:25:22 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=2.6 required=5.0 tests=BAYES_50,KAM_ASCII_DIVIDERS,KAM_LAZY_DOMAIN_SECURITY,RP_MATCHES_RCVD autolearn=no version=3.3.2 spammy=U*owner, 587, 3057, 305,7 X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Tue, 12 Jan 2016 09:25:21 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id DAAF54AE for ; Tue, 12 Jan 2016 01:24:44 -0800 (PST) Received: from SHAWIN202 (unknown [10.164.6.62]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 46B4D3F246 for ; Tue, 12 Jan 2016 01:25:19 -0800 (PST) From: "Thomas Preud'homme" To: Subject: RE: [PATCH, libgcc/ARM 1/6] Fix Thumb-1 only == ARMv6-M & Thumb-2 only == ARMv7-M assumptions Date: Tue, 12 Jan 2016 09:25:00 -0000 Message-ID: <001301d14d1b$27cc4810$7764d830$@foss.arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-IsSubscribed: yes X-SW-Source: 2016-01/txt/msg00677.txt.bz2 > From: gcc-patches-owner@gcc.gnu.org [mailto:gcc-patches- > owner@gcc.gnu.org] On Behalf Of Thomas Preud'homme > Sent: Thursday, December 17, 2015 1:58 PM >=20 > Hi, >=20 > We decided to apply the following patch to the ARM embedded 5 branch. > This is *not* intended for trunk for now. We will send a separate email > for trunk. And now a rebased patch on top of trunk. >=20 > This patch is part of a patch series to add support for ARMv8-M[1] to GCC. > This specific patch fixes some assumptions related to M profile > architectures. Currently GCC (mostly libgcc) contains several assumptions > that the only ARM architecture with Thumb-1 only instructions is ARMv6- > M and the only one with Thumb-2 only instructions is ARMv7-M. ARMv8- > M [1] make this wrong since ARMv8-M baseline is also (mostly) Thumb-1 > only and ARMv8-M mainline is also Thumb-2 only. This patch replace > checks for __ARM_ARCH_*__ for checks against > __ARM_ARCH_ISA_THUMB and __ARM_ARCH_ISA_ARM instead. For > instance, Thumb-1 only can be checked with > #if !defined(__ARM_ARCH_ISA_ARM) && (__ARM_ARCH_ISA_THUMB > =3D=3D 1). It also fixes the guard for DIV code to not apply to ARMv8-M > Baseline since it uses Thumb-2 instructions. >=20 > [1] For a quick overview of ARMv8-M please refer to the initial cover > letter. >=20 > ChangeLog entries are as follow: >=20 >=20 *** gcc/ChangeLog *** 2015-11-13 Thomas Preud'homme * config/arm/elf.h: Use __ARM_ARCH_ISA_THUMB and __ARM_ARCH_ISA_ARM= to decide whether to prevent some libgcc routines being included for s= ome multilibs rather than __ARM_ARCH_6M__ and add comment to indicate t= he link between this condition and the one in libgcc/config/arm/lib1func.S. * config/arm/arm.h (TARGET_ARM_V6M): Add check to TARGET_ARM_ARCH. (TARGET_ARM_V7M): Likewise. *** gcc/testsuite/ChangeLog *** 2015-11-10 Thomas Preud'homme * lib/target-supports.exp (check_effective_target_arm_cortex_m): Use __ARM_ARCH_ISA_ARM to test for Cortex-M devices. *** libgcc/ChangeLog *** 2015-12-17 Thomas Preud'homme * config/arm/bpabi-v6m.S: Fix header comment to mention Thumb-1 rat= her than ARMv6-M. * config/arm/lib1funcs.S (__prefer_thumb__): Define among other cas= es for all Thumb-1 only targets. (__only_thumb1__): Define for all Thumb-1 only targets. (THUMB_LDIV0): Test for __only_thumb1__ rather than __ARM_ARCH_6M__. (EQUIV): Likewise. (ARM_FUNC_ALIAS): Likewise. (umodsi3): Add check to __only_thumb1__ to guard the idiv version. (modsi3): Likewise. (HAVE_ARM_CLZ): Remove block defining it. (clzsi2): Test for __only_thumb1__ rather than __ARM_ARCH_6M__ and check __ARM_FEATURE_CLZ instead of HAVE_ARM_CLZ. (clzdi2): Likewise. (ctzsi2): Likewise. (L_interwork_call_via_rX): Test for __ARM_ARCH_ISA_ARM rather than __ARM_ARCH_6M__ in guard for checking whether it is defined. (final includes): Test for __only_thumb1__ rather than __ARM_ARCH_6M__ and add comment to indicate the connection between this condition and the one in gcc/config/arm/elf.h. * config/arm/libunwind.S: Test for __ARM_ARCH_ISA_THUMB and __ARM_ARCH_ISA_ARM rather than __ARM_ARCH_6M__. * config/arm/t-softfp: Likewise. diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index fd999dd..0d23f39 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -2182,8 +2182,10 @@ extern int making_const_table; #define TARGET_ARM_ARCH \ (arm_base_arch) \ =20 -#define TARGET_ARM_V6M (!arm_arch_notm && !arm_arch_thumb2) -#define TARGET_ARM_V7M (!arm_arch_notm && arm_arch_thumb2) +#define TARGET_ARM_V6M (TARGET_ARM_ARCH =3D=3D BASE_ARCH_6M && !arm_arch_n= otm \ + && !arm_arch_thumb2) +#define TARGET_ARM_V7M (TARGET_ARM_ARCH =3D=3D BASE_ARCH_7M && !arm_arch_n= otm \ + && arm_arch_thumb2) =20 /* The highest Thumb instruction set version supported by the chip. */ #define TARGET_ARM_ARCH_ISA_THUMB \ diff --git a/gcc/config/arm/elf.h b/gcc/config/arm/elf.h index 3795728..579a580 100644 --- a/gcc/config/arm/elf.h +++ b/gcc/config/arm/elf.h @@ -148,8 +148,9 @@ while (0) =20 /* Horrible hack: We want to prevent some libgcc routines being included - for some multilibs. */ -#ifndef __ARM_ARCH_6M__ + for some multilibs. The condition should match the one in + libgcc/config/arm/lib1funcs.S. */ +#if __ARM_ARCH_ISA_ARM || __ARM_ARCH_ISA_THUMB !=3D 1 #undef L_fixdfsi #undef L_fixunsdfsi #undef L_truncdfsf2 diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/targ= et-supports.exp index 4e349e9..3f96826 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -3221,10 +3221,8 @@ proc check_effective_target_arm_cortex_m { } { return 0 } return [check_no_compiler_messages arm_cortex_m assembly { - #if !defined(__ARM_ARCH_7M__) \ - && !defined (__ARM_ARCH_7EM__) \ - && !defined (__ARM_ARCH_6M__) - #error !__ARM_ARCH_7M__ && !__ARM_ARCH_7EM__ && !__ARM_ARCH_6M__ + #if defined(__ARM_ARCH_ISA_ARM) + #error __ARM_ARCH_ISA_ARM is defined #endif int i; } "-mthumb"] diff --git a/libgcc/config/arm/bpabi-v6m.S b/libgcc/config/arm/bpabi-v6m.S index a1e1640..9ae0bb8 100644 --- a/libgcc/config/arm/bpabi-v6m.S +++ b/libgcc/config/arm/bpabi-v6m.S @@ -1,4 +1,4 @@ -/* Miscellaneous BPABI functions. ARMv6M implementation +/* Miscellaneous BPABI functions. Thumb-1 only implementation =20 Copyright (C) 2006-2015 Free Software Foundation, Inc. Contributed by CodeSourcery. diff --git a/libgcc/config/arm/lib1funcs.S b/libgcc/config/arm/lib1funcs.S index 252efcb..95a1f80 100644 --- a/libgcc/config/arm/lib1funcs.S +++ b/libgcc/config/arm/lib1funcs.S @@ -124,7 +124,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively= . If not, see && !defined(__thumb2__) \ && (!defined(__THUMB_INTERWORK__) \ || defined (__OPTIMIZE_SIZE__) \ - || defined(__ARM_ARCH_6M__))) + || !__ARM_ARCH_ISA_ARM)) # define __prefer_thumb__ #endif =20 @@ -305,7 +305,7 @@ LSYM(Lend_fde): =20 #ifdef __ARM_EABI__ .macro THUMB_LDIV0 name signed -#if defined(__ARM_ARCH_6M__) +#if !__ARM_ARCH_ISA_ARM && __ARM_ARCH_ISA_THUMB =3D=3D 1 .ifc \signed, unsigned cmp r0, #0 beq 1f @@ -478,7 +478,7 @@ _L__\name: =20 #else /* !(__INTERWORKING_STUBS__ || __thumb2__) */ =20 -#ifdef __ARM_ARCH_6M__ +#if !__ARM_ARCH_ISA_ARM && __ARM_ARCH_ISA_THUMB =3D=3D 1 #define EQUIV .thumb_set #else .macro ARM_FUNC_START name sp_section=3D @@ -510,7 +510,7 @@ SYM (__\name): #endif .endm =20 -#ifndef __ARM_ARCH_6M__ +#if __ARM_ARCH_ISA_ARM || __ARM_ARCH_ISA_THUMB !=3D 1 .macro ARM_FUNC_ALIAS new old .globl SYM (__\new) EQUIV SYM (__\new), SYM (__\old) @@ -1054,7 +1054,7 @@ ARM_FUNC_START aeabi_uidivmod /* -----------------------------------------------------------------------= - */ #ifdef L_umodsi3 =20 -#ifdef __ARM_ARCH_EXT_IDIV__ +#if defined(__ARM_ARCH_EXT_IDIV__) && __ARM_ARCH_ISA_THUMB !=3D 1 =20 ARM_FUNC_START umodsi3 =20 @@ -1240,7 +1240,7 @@ ARM_FUNC_START aeabi_idivmod /* -----------------------------------------------------------------------= - */ #ifdef L_modsi3 =20 -#if defined(__ARM_ARCH_EXT_IDIV__) +#if defined(__ARM_ARCH_EXT_IDIV__) && __ARM_ARCH_ISA_THUMB !=3D 1 =20 ARM_FUNC_START modsi3 =20 @@ -1508,14 +1508,8 @@ LSYM(Lover12): =20 #endif /* __symbian__ */ =20 -#if ((__ARM_ARCH__ > 5) && !defined(__ARM_ARCH_6M__)) \ - || defined(__ARM_ARCH_5E__) || defined(__ARM_ARCH_5TE__) \ - || defined(__ARM_ARCH_5TEJ__) -#define HAVE_ARM_CLZ 1 -#endif - #ifdef L_clzsi2 -#if defined(__ARM_ARCH_6M__) +#if !__ARM_ARCH_ISA_ARM && __ARM_ARCH_ISA_THUMB =3D=3D 1 FUNC_START clzsi2 mov r1, #28 mov r3, #1 @@ -1544,7 +1538,7 @@ FUNC_START clzsi2 FUNC_END clzsi2 #else ARM_FUNC_START clzsi2 -# if defined(HAVE_ARM_CLZ) +# if defined(__ARM_FEATURE_CLZ) clz r0, r0 RET # else @@ -1568,15 +1562,15 @@ ARM_FUNC_START clzsi2 .align 2 1: .byte 4, 3, 2, 2, 1, 1, 1, 1, 0, 0, 0, 0, 0, 0, 0, 0 -# endif /* !HAVE_ARM_CLZ */ +# endif /* !__ARM_FEATURE_CLZ */ FUNC_END clzsi2 #endif #endif /* L_clzsi2 */ =20 #ifdef L_clzdi2 -#if !defined(HAVE_ARM_CLZ) +#if !defined(__ARM_FEATURE_CLZ) =20 -# if defined(__ARM_ARCH_6M__) +# if !__ARM_ARCH_ISA_ARM && __ARM_ARCH_ISA_THUMB =3D=3D 1 FUNC_START clzdi2 push {r4, lr} # else @@ -1601,14 +1595,14 @@ ARM_FUNC_START clzdi2 bl __clzsi2 # endif 2: -# if defined(__ARM_ARCH_6M__) +# if !__ARM_ARCH_ISA_ARM && __ARM_ARCH_ISA_THUMB =3D=3D 1 pop {r4, pc} # else RETLDM r4 # endif FUNC_END clzdi2 =20 -#else /* HAVE_ARM_CLZ */ +#else /* __ARM_FEATURE_CLZ */ =20 ARM_FUNC_START clzdi2 cmp xxh, #0 @@ -1623,7 +1617,7 @@ ARM_FUNC_START clzdi2 #endif /* L_clzdi2 */ =20 #ifdef L_ctzsi2 -#if defined(__ARM_ARCH_6M__) +#if !__ARM_ARCH_ISA_ARM && __ARM_ARCH_ISA_THUMB =3D=3D 1 FUNC_START ctzsi2 neg r1, r0 and r0, r0, r1 @@ -1656,7 +1650,7 @@ FUNC_START ctzsi2 ARM_FUNC_START ctzsi2 rsb r1, r0, #0 and r0, r0, r1 -# if defined(HAVE_ARM_CLZ) +# if defined(__ARM_FEATURE_CLZ) clz r0, r0 rsb r0, r0, #31 RET @@ -1681,7 +1675,7 @@ ARM_FUNC_START ctzsi2 .align 2 1: .byte 27, 28, 29, 29, 30, 30, 30, 30, 31, 31, 31, 31, 31, 31, 31, 31 -# endif /* !HAVE_ARM_CLZ */ +# endif /* !__ARM_FEATURE_CLZ */ FUNC_END ctzsi2 #endif #endif /* L_clzsi2 */ @@ -1738,7 +1732,7 @@ ARM_FUNC_START ctzsi2 =20 /* Don't bother with the old interworking routines for Thumb-2. */ /* ??? Maybe only omit these on "m" variants. */ -#if !defined(__thumb2__) && !defined(__ARM_ARCH_6M__) +#if !defined(__thumb2__) && __ARM_ARCH_ISA_ARM =20 #if defined L_interwork_call_via_rX =20 @@ -1983,11 +1977,12 @@ LSYM(Lchange_\register): .endm =20 #ifndef __symbian__ -#ifndef __ARM_ARCH_6M__ +/* The condition here must match the one in gcc/config/arm/elf.h. */ +#if __ARM_ARCH_ISA_ARM || __ARM_ARCH_ISA_THUMB !=3D 1 #include "ieee754-df.S" #include "ieee754-sf.S" #include "bpabi.S" -#else /* __ARM_ARCH_6M__ */ +#else /* !__ARM_ARCH_ISA_ARM && __ARM_ARCH_ISA_THUMB =3D=3D 1 */ #include "bpabi-v6m.S" -#endif /* __ARM_ARCH_6M__ */ +#endif /* !__ARM_ARCH_ISA_ARM && __ARM_ARCH_ISA_THUMB =3D=3D 1 */ #endif /* !__symbian__ */ diff --git a/libgcc/config/arm/libunwind.S b/libgcc/config/arm/libunwind.S index cac1022..393ec8a 100644 --- a/libgcc/config/arm/libunwind.S +++ b/libgcc/config/arm/libunwind.S @@ -58,7 +58,7 @@ #endif #endif =20 -#ifdef __ARM_ARCH_6M__ +#if !__ARM_ARCH_ISA_ARM && __ARM_ARCH_ISA_THUMB =3D=3D 1 =20 /* r0 points to a 16-word block. Upload these values to the actual core state. */ @@ -169,7 +169,7 @@ FUNC_START gnu_Unwind_Save_WMMXC UNPREFIX \name .endm =20 -#else /* !__ARM_ARCH_6M__ */ +#else /* __ARM_ARCH_ISA_ARM || __ARM_ARCH_ISA_THUMB !=3D 1 */ =20 /* r0 points to a 16-word block. Upload these values to the actual core state. */ @@ -351,7 +351,7 @@ ARM_FUNC_START gnu_Unwind_Save_WMMXC UNPREFIX \name .endm =20 -#endif /* !__ARM_ARCH_6M__ */ +#endif /* __ARM_ARCH_ISA_ARM || __ARM_ARCH_ISA_THUMB !=3D 1 */ =20 UNWIND_WRAPPER _Unwind_RaiseException 1 UNWIND_WRAPPER _Unwind_Resume 1 diff --git a/libgcc/config/arm/t-softfp b/libgcc/config/arm/t-softfp index 4ede438..554ec9b 100644 --- a/libgcc/config/arm/t-softfp +++ b/libgcc/config/arm/t-softfp @@ -1,2 +1,2 @@ -softfp_wrap_start :=3D '\#ifdef __ARM_ARCH_6M__' +softfp_wrap_start :=3D '\#if !__ARM_ARCH_ISA_ARM && __ARM_ARCH_ISA_THUMB = =3D=3D 1' softfp_wrap_end :=3D '\#endif' Tested by building libgcc and comparing it before and after with objdump -D and readelf -A for all permutations of: Architectures: armv4 armv4t armv5 armv5t armv5te armv6 armv6j armv6k armv6z armv6kz armv6t2 armv6s-m armv7 armv7-a armv7ve armv7-r armv7-m armv7e-m armv8-a armv8-a+crc iwmmxt iwmmxt2 ISAs: thumb arm Optimization Levels: Os O2 Excluding: armv6s-m -marm armv7-m -marm armv7e-m -marm iwmmxt -mthumb iwmmxt2 -mthumb as being rejected by the compiler or assembler. ARMv6-m was not tested beca= use compilation fails due to svc instruction. Best regards, Thomas