From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from server.nextmovesoftware.com (server.nextmovesoftware.com [162.254.253.69]) by sourceware.org (Postfix) with ESMTPS id BD9C53858D35 for ; Thu, 5 Jan 2023 14:10:06 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org BD9C53858D35 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=nextmovesoftware.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=nextmovesoftware.com DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=nextmovesoftware.com; s=default; h=Content-Type:MIME-Version:Message-ID: Date:Subject:Cc:To:From:Sender:Reply-To:Content-Transfer-Encoding:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:In-Reply-To:References:List-Id:List-Help:List-Unsubscribe: List-Subscribe:List-Post:List-Owner:List-Archive; bh=euG1Q84tzO2Wr9eRZlZiVufrVAETA6GVM3mbGx6OoRE=; b=iUXtA0O/8HDUdbdQ8vtu4SXugz KjgEMINirOVo6O01EvIE71XJSG5vva8B0hX5dqOeCyNiHrYzu8MLcmOdrtLct3Ko2o75IpS/JrRS5 l4QFU8WkmEPFB5IGaN1sEdTIBmiFfT0w7r8WZB4472FssHHSPZAhMHh5Hlg0MhSLfJFM9KAq2A0xc a6YKihyVt0CzMHwYbjz1V5vhgAqaHdxnLXaDbsPTWeiQvTFyy5d3XJ251O6e2pylVE2aFZC5GsDnR 1qUsAhZU07n4GlW1JDquoMx3Nz6uxQWSqjWnF/hAqXTHOYaNQIip619cZrYGNQETTabDqoPBQ+Bjd EK+BHplQ==; Received: from [185.62.158.67] (port=51169 helo=Dell) by server.nextmovesoftware.com with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1pDQwX-0005FM-RQ; Thu, 05 Jan 2023 09:10:06 -0500 From: "Roger Sayle" To: "'GCC Patches'" Cc: "'Uros Bizjak'" Subject: [x86_64 PATCH] Introduce insvti_highpart define_insn_and_split. Date: Thu, 5 Jan 2023 14:10:04 -0000 Message-ID: <001501d9210f$694bed70$3be3c850$@nextmovesoftware.com> MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="----=_NextPart_000_0016_01D9210F.694BED70" X-Mailer: Microsoft Outlook 16.0 Thread-Index: AdkhDl4F+DFrwaBXQnuslcZR5qfMjQ== Content-Language: en-gb X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - server.nextmovesoftware.com X-AntiAbuse: Original Domain - gcc.gnu.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - nextmovesoftware.com X-Get-Message-Sender-Via: server.nextmovesoftware.com: authenticated_id: roger@nextmovesoftware.com X-Authenticated-Sender: server.nextmovesoftware.com: roger@nextmovesoftware.com X-Source: X-Source-Args: X-Source-Dir: X-Spam-Status: No, score=-12.5 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,KAM_SHORT,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: This is a multipart message in MIME format. ------=_NextPart_000_0016_01D9210F.694BED70 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit This patch adds a convenient post-reload splitter for setting/updating the highpart of a TImode variable, using the recently added split_double_concat infrastructure. For the new test case below: __int128 foo(__int128 x, unsigned long long y) { __int128 t = (__int128)y << 64; __int128 r = (x & ~0ull) | t; return r; } mainline GCC with -O2 currently generates: foo: movq %rdi, %rcx xorl %eax, %eax xorl %edi, %edi orq %rcx, %rax orq %rdi, %rdx ret with this patch, GCC instead now generates the much better: foo: movq %rdi, %rcx movq %rcx, %rax ret [which interestingly shows the deeper (ABI) issue that I'm trying to fix, this new define_insn_and_split being the next piece]. It turns out that the -m32 equivalent of this testcase, already avoids using explict orl/xor instructions, as it gets optimized (in combine) by a completely different path. Given that this idiom isn't seen in 32-bit code (and therefore this pattern wouldn't match), and also that the shorter 32-bit AND bitmask is represented as a CONST_INT rather than a CONST_WIDE_INT, this new define_insn_and_split is implemented for just TARGET_64BIT rather than contort a "generic" implementation using DWI mode iterators. This patch has been tested on x86_64-pc-linux-gnu with make bootstrap and make -k check, both with and without --target_board=unix{-m32}, with no new failures. Ok for mainline? Please let me know if you'd prefer a different pattern name [insv seemed better than mov]. 2023-01-05 Roger Sayle gcc/ChangeLog * config/i386/i386.md (any_or_plus): Move definition earlier. (*insvti_highpart_1): New define_insn_and_split to overwrite (insv) the highpart of a TImode register/memory. gcc/testsuite/ChangeLog * gcc.target/i386/insvti_highpart-1.c: New test case. Thanks in advance, Roger -- ------=_NextPart_000_0016_01D9210F.694BED70 Content-Type: text/plain; name="patchin.txt" Content-Transfer-Encoding: quoted-printable Content-Disposition: attachment; filename="patchin.txt" diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md=0A= index 890c4c8..9f3c62b 100644=0A= --- a/gcc/config/i386/i386.md=0A= +++ b/gcc/config/i386/i386.md=0A= @@ -3401,6 +3401,31 @@=0A= "mov{b}\t{%h1, %h0|%h0, %h1}"=0A= [(set_attr "type" "imov")=0A= (set_attr "mode" "QI")])=0A= +=0A= +(define_code_iterator any_or_plus [plus ior xor])=0A= +(define_insn_and_split "*insvti_highpart_1"=0A= + [(set (match_operand:TI 0 "nonimmediate_operand" "=3Dro,r,r,&r")=0A= + (any_or_plus:TI=0A= + (and:TI=0A= + (match_operand:TI 1 "nonimmediate_operand" "r,m,r,m")=0A= + (match_operand:TI 3 "const_scalar_int_operand" "n,n,n,n"))=0A= + (ashift:TI=0A= + (zero_extend:TI=0A= + (match_operand:DI 2 "nonimmediate_operand" "r,r,m,m"))=0A= + (const_int 64))))]=0A= + "TARGET_64BIT=0A= + && CONST_WIDE_INT_P (operands[3])=0A= + && CONST_WIDE_INT_NUNITS (operands[3]) =3D=3D 2=0A= + && CONST_WIDE_INT_ELT (operands[3], 0) =3D=3D -1=0A= + && CONST_WIDE_INT_ELT (operands[3], 1) =3D=3D 0"=0A= + "#"=0A= + "&& reload_completed"=0A= + [(clobber (const_int 0))]=0A= +{=0A= + operands[4] =3D gen_lowpart (DImode, operands[1]);=0A= + split_double_concat (TImode, operands[0], operands[4], operands[2]);=0A= + DONE;=0A= +})=0A= =0C=0A= ;; Floating point push instructions.=0A= =0A= @@ -11418,7 +11443,6 @@=0A= (set_attr "mode" "QI")])=0A= =0A= ;; Split DST =3D (HI<<32)|LO early to minimize register usage.=0A= -(define_code_iterator any_or_plus [plus ior xor])=0A= (define_insn_and_split "*concat3_1"=0A= [(set (match_operand: 0 "nonimmediate_operand" "=3Dro,r")=0A= (any_or_plus:=0A= diff --git a/gcc/testsuite/gcc.target/i386/insvti_highpart-1.c = b/gcc/testsuite/gcc.target/i386/insvti_highpart-1.c=0A= new file mode 100644=0A= index 0000000..4ae9ccf=0A= --- /dev/null=0A= +++ b/gcc/testsuite/gcc.target/i386/insvti_highpart-1.c=0A= @@ -0,0 +1,12 @@=0A= +/* { dg-do compile { target int128 } } */=0A= +/* { dg-options "-O2" } */=0A= +=0A= +__int128 foo(__int128 x, unsigned long long y)=0A= +{=0A= + __int128 t =3D (__int128)y << 64;=0A= + __int128 r =3D (x & ~0ull) | t;=0A= + return r;=0A= +}=0A= +=0A= +/* { dg-final { scan-assembler-not "xorl" } } */=0A= +/* { dg-final { scan-assembler-not "orq" } } */=0A= ------=_NextPart_000_0016_01D9210F.694BED70--