From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 15886 invoked by alias); 18 Feb 2013 18:37:04 -0000 Received: (qmail 15206 invoked by uid 22791); 18 Feb 2013 18:36:58 -0000 X-SWARE-Spam-Status: No, hits=-2.0 required=5.0 tests=AWL,BAYES_00,KHOP_RCVD_UNTRUST,KHOP_SPAMHAUS_DROP,KHOP_THREADED,MSGID_MULTIPLE_AT,RCVD_IN_DNSWL_LOW X-Spam-Check-By: sourceware.org Received: from service87.mimecast.com (HELO service87.mimecast.com) (91.220.42.44) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Mon, 18 Feb 2013 18:36:51 +0000 Received: from cam-owa1.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.21]) by service87.mimecast.com; Mon, 18 Feb 2013 18:36:50 +0000 Received: from e103227vm ([10.1.255.212]) by cam-owa1.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.0); Mon, 18 Feb 2013 18:36:49 +0000 From: "Greta Yorsh" To: "Greta Yorsh" , "GCC Patches" Cc: "Richard Earnshaw" , "Ramana Radhakrishnan" , , References: <001101ce0e05$f5928a50$e0b79ef0$@yorsh@arm.com> In-Reply-To: <001101ce0e05$f5928a50$e0b79ef0$@yorsh@arm.com> Subject: [PATCH,ARM][2/n] Split subdi patterns Date: Mon, 18 Feb 2013 18:37:00 -0000 Message-ID: <001701ce0e06$e8069060$b813b120$@yorsh@arm.com> MIME-Version: 1.0 X-MC-Unique: 113021818365000301 Content-Type: multipart/mixed; boundary="----=_NextPart_000_0018_01CE0E06.E8069060" Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org X-SW-Source: 2013-02/txt/msg00858.txt.bz2 This is a multi-part message in MIME format. ------=_NextPart_000_0018_01CE0E06.E8069060 Content-Type: text/plain; charset=WINDOWS-1252 Content-Transfer-Encoding: quoted-printable Content-length: 400 Convert define_insn into define_insn_and_split for various subdi patterns that output multiple assembly instructions. 2013-02-14 Greta Yorsh * config/arm/arm.md (arm_subdi3): Convert define_insn into define_insn_and_split. (subdi_di_zesidi,subdi_di_sesidi): Likewise. (subdi_zesidi_di,subdi_sesidi_di,subdi_zesidi_zesidi): Likewise.= ------=_NextPart_000_0018_01CE0E06.E8069060 Content-Type: text/plain; name=2-split-subdi.patch.txt Content-Transfer-Encoding: quoted-printable Content-Disposition: attachment; filename="2-split-subdi.patch.txt" Content-length: 7278 diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index c708af4d78df9a92ac1c441138b57f6f18178607..000000000000000000000000000= 0000000000000 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -1149,13 +1149,27 @@ (define_expand "subdi3" " ) =20 -(define_insn "*arm_subdi3" +(define_insn_and_split "*arm_subdi3" [(set (match_operand:DI 0 "s_register_operand" "=3D&r,&r,&r") (minus:DI (match_operand:DI 1 "s_register_operand" "0,r,0") (match_operand:DI 2 "s_register_operand" "r,0,0"))) (clobber (reg:CC CC_REGNUM))] "TARGET_32BIT && !TARGET_NEON" - "subs\\t%Q0, %Q1, %Q2\;sbc\\t%R0, %R1, %R2" + "#" ; "subs\\t%Q0, %Q1, %Q2\;sbc\\t%R0, %R1, %R2" + "&& reload_completed" + [(parallel [(set (reg:CC CC_REGNUM) + (compare:CC (match_dup 1) (match_dup 2))) + (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 2)))]) + (set (match_dup 3) (minus:SI (minus:SI (match_dup 4) (match_dup 5)) + (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))] + { + operands[3] =3D gen_highpart (SImode, operands[0]); + operands[0] =3D gen_lowpart (SImode, operands[0]); + operands[4] =3D gen_highpart (SImode, operands[1]); + operands[1] =3D gen_lowpart (SImode, operands[1]); + operands[5] =3D gen_highpart (SImode, operands[2]); + operands[2] =3D gen_lowpart (SImode, operands[2]); + } [(set_attr "conds" "clob") (set_attr "length" "8")] ) @@ -1170,55 +1184,113 @@ (define_insn "*thumb_subdi3" [(set_attr "length" "4")] ) =20 -(define_insn "*subdi_di_zesidi" +(define_insn_and_split "*subdi_di_zesidi" [(set (match_operand:DI 0 "s_register_operand" "=3D&r,&r") (minus:DI (match_operand:DI 1 "s_register_operand" "0,r") (zero_extend:DI (match_operand:SI 2 "s_register_operand" "r,r")))) (clobber (reg:CC CC_REGNUM))] "TARGET_32BIT" - "subs\\t%Q0, %Q1, %2\;sbc\\t%R0, %R1, #0" + "#" ; "subs\\t%Q0, %Q1, %2\;sbc\\t%R0, %R1, #0" + "&& reload_completed" + [(parallel [(set (reg:CC CC_REGNUM) + (compare:CC (match_dup 1) (match_dup 2))) + (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 2)))]) + (set (match_dup 3) (minus:SI (plus:SI (match_dup 4) (match_dup 5)) + (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0)= )))] + { + operands[3] =3D gen_highpart (SImode, operands[0]); + operands[0] =3D gen_lowpart (SImode, operands[0]); + operands[4] =3D gen_highpart (SImode, operands[1]); + operands[1] =3D gen_lowpart (SImode, operands[1]); + operands[5] =3D GEN_INT (~0); + } [(set_attr "conds" "clob") (set_attr "length" "8")] ) =20 -(define_insn "*subdi_di_sesidi" +(define_insn_and_split "*subdi_di_sesidi" [(set (match_operand:DI 0 "s_register_operand" "=3D&r,&r") (minus:DI (match_operand:DI 1 "s_register_operand" "0,r") (sign_extend:DI (match_operand:SI 2 "s_register_operand" "r,r")))) (clobber (reg:CC CC_REGNUM))] "TARGET_32BIT" - "subs\\t%Q0, %Q1, %2\;sbc\\t%R0, %R1, %2, asr #31" + "#" ; "subs\\t%Q0, %Q1, %2\;sbc\\t%R0, %R1, %2, asr #31" + "&& reload_completed" + [(parallel [(set (reg:CC CC_REGNUM) + (compare:CC (match_dup 1) (match_dup 2))) + (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 2)))]) + (set (match_dup 3) (minus:SI (minus:SI (match_dup 4) + (ashiftrt:SI (match_dup 2) + (const_int 31))) + (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0)= )))] + { + operands[3] =3D gen_highpart (SImode, operands[0]); + operands[0] =3D gen_lowpart (SImode, operands[0]); + operands[4] =3D gen_highpart (SImode, operands[1]); + operands[1] =3D gen_lowpart (SImode, operands[1]); + } [(set_attr "conds" "clob") (set_attr "length" "8")] ) =20 -(define_insn "*subdi_zesidi_di" +(define_insn_and_split "*subdi_zesidi_di" [(set (match_operand:DI 0 "s_register_operand" "=3D&r,&r") (minus:DI (zero_extend:DI (match_operand:SI 2 "s_register_operand" "r,r")) (match_operand:DI 1 "s_register_operand" "0,r"))) (clobber (reg:CC CC_REGNUM))] "TARGET_ARM" - "rsbs\\t%Q0, %Q1, %2\;rsc\\t%R0, %R1, #0" + "#" ; "rsbs\\t%Q0, %Q1, %2\;rsc\\t%R0, %R1, #0" + ; is equivalent to: + ; "subs\\t%Q0, %2, %Q1\;rsc\\t%R0, %R1, #0" + "&& reload_completed" + [(parallel [(set (reg:CC CC_REGNUM) + (compare:CC (match_dup 2) (match_dup 1))) + (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 1)))]) + (set (match_dup 3) (minus:SI (minus:SI (const_int 0) (match_dup 4)) + (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))] + { + operands[3] =3D gen_highpart (SImode, operands[0]); + operands[0] =3D gen_lowpart (SImode, operands[0]); + operands[4] =3D gen_highpart (SImode, operands[1]); + operands[1] =3D gen_lowpart (SImode, operands[1]); + } [(set_attr "conds" "clob") (set_attr "length" "8")] ) =20 -(define_insn "*subdi_sesidi_di" +(define_insn_and_split "*subdi_sesidi_di" [(set (match_operand:DI 0 "s_register_operand" "=3D&r,&r") (minus:DI (sign_extend:DI (match_operand:SI 2 "s_register_operand" "r,r")) (match_operand:DI 1 "s_register_operand" "0,r"))) (clobber (reg:CC CC_REGNUM))] "TARGET_ARM" - "rsbs\\t%Q0, %Q1, %2\;rsc\\t%R0, %R1, %2, asr #31" + "#" ; "rsbs\\t%Q0, %Q1, %2\;rsc\\t%R0, %R1, %2, asr #31" + ; is equivalent to: + ; "subs\\t%Q0, %2, %Q1\;rsc\\t%R0, %R1, %2, asr #31" + "&& reload_completed" + [(parallel [(set (reg:CC CC_REGNUM) + (compare:CC (match_dup 2) (match_dup 1))) + (set (match_dup 0) (minus:SI (match_dup 2) (match_dup 1)))]) + (set (match_dup 3) (minus:SI (minus:SI + (ashiftrt:SI (match_dup 2) + (const_int 31)) + (match_dup 4)) + (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))] + { + operands[3] =3D gen_highpart (SImode, operands[0]); + operands[0] =3D gen_lowpart (SImode, operands[0]); + operands[4] =3D gen_highpart (SImode, operands[1]); + operands[1] =3D gen_lowpart (SImode, operands[1]); + } [(set_attr "conds" "clob") (set_attr "length" "8")] ) =20 -(define_insn "*subdi_zesidi_zesidi" +(define_insn_and_split "*subdi_zesidi_zesidi" [(set (match_operand:DI 0 "s_register_operand" "=3Dr") (minus:DI (zero_extend:DI (match_operand:SI 1 "s_register_operand" "r")) @@ -1226,7 +1298,17 @@ (define_insn "*subdi_zesidi_zesidi" (match_operand:SI 2 "s_register_operand" "r")))) (clobber (reg:CC CC_REGNUM))] "TARGET_32BIT" - "subs\\t%Q0, %1, %2\;sbc\\t%R0, %1, %1" + "#" ; "subs\\t%Q0, %1, %2\;sbc\\t%R0, %1, %1" + "&& reload_completed" + [(parallel [(set (reg:CC CC_REGNUM) + (compare:CC (match_dup 1) (match_dup 2))) + (set (match_dup 0) (minus:SI (match_dup 1) (match_dup 2)))]) + (set (match_dup 3) (minus:SI (minus:SI (match_dup 1) (match_dup 1)) + (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))] + { + operands[3] =3D gen_highpart (SImode, operands[0]); + operands[0] =3D gen_lowpart (SImode, operands[0]); + } [(set_attr "conds" "clob") (set_attr "length" "8")] ) ------=_NextPart_000_0018_01CE0E06.E8069060--