From: "Greta Yorsh" <greta.yorsh@arm.com>
To: "Greta Yorsh" <Greta.Yorsh@arm.com>,
"GCC Patches" <gcc-patches@gcc.gnu.org>
Cc: "Richard Earnshaw" <Richard.Earnshaw@arm.com>,
"Ramana Radhakrishnan" <Ramana.Radhakrishnan@arm.com>,
<nickc@redhat.com>, <paul@codesourcery.com>
Subject: [PATCH,ARM][5/n] Split shift di patterns
Date: Mon, 18 Feb 2013 18:43:00 -0000 [thread overview]
Message-ID: <002301ce0e07$c10b3460$43219d20$@yorsh@arm.com> (raw)
In-Reply-To: <001101ce0e05$f5928a50$e0b79ef0$@yorsh@arm.com>
[-- Attachment #1: Type: text/plain, Size: 676 bytes --]
Convert define_insn into define_insn_and_split for various DImode shift
operations that output multiple assembly instructions.
This patch also adds a new pattern for RRX using a new UNSPEC. This pattern
matches RTL insns emitted by arm_ashrdi3_1bit and arm_lshrdi3_1bit
splitters. This patch also adds a new pattern shiftsi3_compare.
gcc/
2013-02-14 Greta Yorsh <Greta.Yorsh@arm.com>
* config/arm/arm.md (arm_ashldi3_1bit): Convert define_insn into
define_insn_and_split.
(arm_ashrdi3_1bit,arm_lshrdi3_1bit): Likewise.
(shiftsi3_compare): New pattern.
(rrx): New pattern.
* config/arm/unspecs.md (UNSPEC_RRX): New.
[-- Attachment #2: 5-split-shiftdi.patch.txt --]
[-- Type: text/plain, Size: 5963 bytes --]
diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md
index cbd0faf636d264dd4e46db9c8a1fe226b431a97e..0000000000000000000000000000000000000000 100644
--- a/gcc/config/arm/arm.md
+++ b/gcc/config/arm/arm.md
@@ -3806,13 +3806,26 @@ (define_expand "ashldi3"
"
)
-(define_insn "arm_ashldi3_1bit"
+(define_insn_and_split "arm_ashldi3_1bit"
[(set (match_operand:DI 0 "s_register_operand" "=r,&r")
(ashift:DI (match_operand:DI 1 "s_register_operand" "0,r")
(const_int 1)))
(clobber (reg:CC CC_REGNUM))]
"TARGET_32BIT"
- "movs\\t%Q0, %Q1, asl #1\;adc\\t%R0, %R1, %R1"
+ "#" ; "movs\\t%Q0, %Q1, asl #1\;adc\\t%R0, %R1, %R1"
+ "&& reload_completed"
+ [(parallel [(set (reg:CC CC_REGNUM)
+ (compare:CC (ashift:SI (match_dup 1) (const_int 1))
+ (const_int 0)))
+ (set (match_dup 0) (ashift:SI (match_dup 1) (const_int 1)))])
+ (set (match_dup 2) (plus:SI (plus:SI (match_dup 3) (match_dup 3))
+ (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))]
+ {
+ operands[2] = gen_highpart (SImode, operands[0]);
+ operands[0] = gen_lowpart (SImode, operands[0]);
+ operands[3] = gen_highpart (SImode, operands[1]);
+ operands[1] = gen_lowpart (SImode, operands[1]);
+ }
[(set_attr "conds" "clob")
(set_attr "length" "8")]
)
@@ -3888,18 +3901,43 @@ (define_expand "ashrdi3"
"
)
-(define_insn "arm_ashrdi3_1bit"
+(define_insn_and_split "arm_ashrdi3_1bit"
[(set (match_operand:DI 0 "s_register_operand" "=r,&r")
(ashiftrt:DI (match_operand:DI 1 "s_register_operand" "0,r")
(const_int 1)))
(clobber (reg:CC CC_REGNUM))]
"TARGET_32BIT"
- "movs\\t%R0, %R1, asr #1\;mov\\t%Q0, %Q1, rrx"
+ "#" ; "movs\\t%R0, %R1, asr #1\;mov\\t%Q0, %Q1, rrx"
+ "&& reload_completed"
+ [(parallel [(set (reg:CC CC_REGNUM)
+ (compare:CC (ashiftrt:SI (match_dup 3) (const_int 1))
+ (const_int 0)))
+ (set (match_dup 2) (ashiftrt:SI (match_dup 3) (const_int 1)))])
+ (set (match_dup 0) (unspec:SI [(match_dup 1)
+ (reg:CC_C CC_REGNUM)]
+ UNSPEC_RRX))]
+ {
+ operands[2] = gen_highpart (SImode, operands[0]);
+ operands[0] = gen_lowpart (SImode, operands[0]);
+ operands[3] = gen_highpart (SImode, operands[1]);
+ operands[1] = gen_lowpart (SImode, operands[1]);
+ }
[(set_attr "conds" "clob")
- (set_attr "insn" "mov")
(set_attr "length" "8")]
)
+(define_insn "*rrx"
+ [(set (match_operand:SI 0 "s_register_operand" "=r")
+ (unspec:SI [(match_operand:SI 1 "s_register_operand" "r")
+ (reg:CC_C CC_REGNUM)]
+ UNSPEC_RRX))]
+ "TARGET_32BIT"
+ "mov\\t%0, %1, rrx"
+ [(set_attr "conds" "use")
+ (set_attr "insn" "mov")
+ (set_attr "type" "alu_shift")]
+)
+
(define_expand "ashrsi3"
[(set (match_operand:SI 0 "s_register_operand" "")
(ashiftrt:SI (match_operand:SI 1 "s_register_operand" "")
@@ -3968,15 +4006,28 @@ (define_expand "lshrdi3"
"
)
-(define_insn "arm_lshrdi3_1bit"
+(define_insn_and_split "arm_lshrdi3_1bit"
[(set (match_operand:DI 0 "s_register_operand" "=r,&r")
(lshiftrt:DI (match_operand:DI 1 "s_register_operand" "0,r")
(const_int 1)))
(clobber (reg:CC CC_REGNUM))]
"TARGET_32BIT"
- "movs\\t%R0, %R1, lsr #1\;mov\\t%Q0, %Q1, rrx"
+ "#" ; "movs\\t%R0, %R1, lsr #1\;mov\\t%Q0, %Q1, rrx"
+ "&& reload_completed"
+ [(parallel [(set (reg:CC CC_REGNUM)
+ (compare:CC (lshiftrt:SI (match_dup 3) (const_int 1))
+ (const_int 0)))
+ (set (match_dup 2) (lshiftrt:SI (match_dup 3) (const_int 1)))])
+ (set (match_dup 0) (unspec:SI [(match_dup 1)
+ (reg:CC_C CC_REGNUM)]
+ UNSPEC_RRX))]
+ {
+ operands[2] = gen_highpart (SImode, operands[0]);
+ operands[0] = gen_lowpart (SImode, operands[0]);
+ operands[3] = gen_highpart (SImode, operands[1]);
+ operands[1] = gen_lowpart (SImode, operands[1]);
+ }
[(set_attr "conds" "clob")
- (set_attr "insn" "mov")
(set_attr "length" "8")]
)
@@ -4064,6 +4115,23 @@ (define_insn "*arm_shiftsi3"
(const_string "alu_shift_reg")))]
)
+(define_insn "*shiftsi3_compare"
+ [(set (reg:CC CC_REGNUM)
+ (compare:CC (match_operator:SI 3 "shift_operator"
+ [(match_operand:SI 1 "s_register_operand" "r")
+ (match_operand:SI 2 "arm_rhs_operand" "rM")])
+ (const_int 0)))
+ (set (match_operand:SI 0 "s_register_operand" "=r")
+ (match_op_dup 3 [(match_dup 1) (match_dup 2)]))]
+ "TARGET_32BIT"
+ "* return arm_output_shift(operands, 1);"
+ [(set_attr "conds" "set")
+ (set_attr "shift" "1")
+ (set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "")
+ (const_string "alu_shift")
+ (const_string "alu_shift_reg")))]
+)
+
(define_insn "*shiftsi3_compare0"
[(set (reg:CC_NOOV CC_REGNUM)
(compare:CC_NOOV (match_operator:SI 3 "shift_operator"
diff --git a/gcc/config/arm/unspecs.md b/gcc/config/arm/unspecs.md
index c3fb03256ceb1049d3cbb55d89075abb803f97c3..0000000000000000000000000000000000000000 100644
--- a/gcc/config/arm/unspecs.md
+++ b/gcc/config/arm/unspecs.md
@@ -83,6 +83,8 @@ (define_c_enum "unspec" [
; FPSCR rounding mode and signal inexactness.
UNSPEC_VRINTA ; Represent a float to integral float rounding
; towards nearest, ties away from zero.
+ UNSPEC_RRX ; Rotate Right with Extend shifts register right
+ ; by one place, with Carry flag shifted into bit[31].
])
(define_c_enum "unspec" [
next prev parent reply other threads:[~2013-02-18 18:43 UTC|newest]
Thread overview: 14+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-02-18 18:30 [PATCH, ARM][0/n] Split patterns that output multiple assembly instruction Greta Yorsh
2013-02-18 18:35 ` [PATCH,ARM][1/n] New patterns for subtract with carry Greta Yorsh
2013-02-22 16:29 ` Richard Earnshaw
[not found] ` <B393A6715F47FC43935D96EA15105EFF3F95D287B4@GEORGE.Emea.Arm.com>
2013-04-05 18:59 ` Ramana Radhakrishnan
2013-02-18 18:37 ` [PATCH,ARM][2/n] Split subdi patterns Greta Yorsh
2013-02-22 16:33 ` Richard Earnshaw
2013-02-18 18:39 ` [PATCH,ARM][3/n] Split various patterns Greta Yorsh
2013-04-09 18:13 ` Richard Earnshaw
2013-02-18 18:41 ` [PATCH,ARM][4/n] Add negdi_extend patterns Greta Yorsh
2013-02-18 18:43 ` Greta Yorsh [this message]
2013-02-18 18:45 ` [PATCH,ARM][6/n] Split min and max patterns Greta Yorsh
2013-04-09 18:02 ` Richard Earnshaw
2013-02-18 18:46 ` [PATCH, ARM][7/n] Comment on splitting THUMB1 patterns Greta Yorsh
[not found] <51227652.834a420a.7f51.4e55SMTPIN_ADDED_BROKEN@mx.google.com>
2013-03-26 13:40 ` [PATCH,ARM][5/n] Split shift di patterns Ramana Radhakrishnan
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to='002301ce0e07$c10b3460$43219d20$@yorsh@arm.com' \
--to=greta.yorsh@arm.com \
--cc=Ramana.Radhakrishnan@arm.com \
--cc=Richard.Earnshaw@arm.com \
--cc=gcc-patches@gcc.gnu.org \
--cc=nickc@redhat.com \
--cc=paul@codesourcery.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).