From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 9300 invoked by alias); 18 Feb 2013 18:43:12 -0000 Received: (qmail 9271 invoked by uid 22791); 18 Feb 2013 18:43:11 -0000 X-SWARE-Spam-Status: No, hits=-2.0 required=5.0 tests=AWL,BAYES_00,KHOP_RCVD_UNTRUST,KHOP_SPAMHAUS_DROP,KHOP_THREADED,MSGID_MULTIPLE_AT,RCVD_IN_DNSWL_LOW X-Spam-Check-By: sourceware.org Received: from service87.mimecast.com (HELO service87.mimecast.com) (91.220.42.44) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Mon, 18 Feb 2013 18:42:57 +0000 Received: from cam-owa1.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.21]) by service87.mimecast.com; Mon, 18 Feb 2013 18:42:55 +0000 Received: from e103227vm ([10.1.255.212]) by cam-owa1.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.0); Mon, 18 Feb 2013 18:42:54 +0000 From: "Greta Yorsh" To: "Greta Yorsh" , "GCC Patches" Cc: "Richard Earnshaw" , "Ramana Radhakrishnan" , , References: <001101ce0e05$f5928a50$e0b79ef0$@yorsh@arm.com> In-Reply-To: <001101ce0e05$f5928a50$e0b79ef0$@yorsh@arm.com> Subject: [PATCH,ARM][5/n] Split shift di patterns Date: Mon, 18 Feb 2013 18:43:00 -0000 Message-ID: <002301ce0e07$c10b3460$43219d20$@yorsh@arm.com> MIME-Version: 1.0 X-MC-Unique: 113021818425500401 Content-Type: multipart/mixed; boundary="----=_NextPart_000_0024_01CE0E07.C10B3460" Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org X-SW-Source: 2013-02/txt/msg00861.txt.bz2 This is a multi-part message in MIME format. ------=_NextPart_000_0024_01CE0E07.C10B3460 Content-Type: text/plain; charset=WINDOWS-1252 Content-Transfer-Encoding: quoted-printable Content-length: 659 Convert define_insn into define_insn_and_split for various DImode shift operations that output multiple assembly instructions. This patch also adds a new pattern for RRX using a new UNSPEC. This pattern matches RTL insns emitted by arm_ashrdi3_1bit and arm_lshrdi3_1bit splitters. This patch also adds a new pattern shiftsi3_compare. gcc/ 2013-02-14 Greta Yorsh * config/arm/arm.md (arm_ashldi3_1bit): Convert define_insn into define_insn_and_split. (arm_ashrdi3_1bit,arm_lshrdi3_1bit): Likewise. (shiftsi3_compare): New pattern. (rrx): New pattern. * config/arm/unspecs.md (UNSPEC_RRX): New. ------=_NextPart_000_0024_01CE0E07.C10B3460 Content-Type: text/plain; name=5-split-shiftdi.patch.txt Content-Transfer-Encoding: quoted-printable Content-Disposition: attachment; filename="5-split-shiftdi.patch.txt" Content-length: 5874 diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index cbd0faf636d264dd4e46db9c8a1fe226b431a97e..000000000000000000000000000= 0000000000000 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -3806,13 +3806,26 @@ (define_expand "ashldi3" " ) =20 -(define_insn "arm_ashldi3_1bit" +(define_insn_and_split "arm_ashldi3_1bit" [(set (match_operand:DI 0 "s_register_operand" "=3Dr,&r") (ashift:DI (match_operand:DI 1 "s_register_operand" "0,r") (const_int 1))) (clobber (reg:CC CC_REGNUM))] "TARGET_32BIT" - "movs\\t%Q0, %Q1, asl #1\;adc\\t%R0, %R1, %R1" + "#" ; "movs\\t%Q0, %Q1, asl #1\;adc\\t%R0, %R1, %R1" + "&& reload_completed" + [(parallel [(set (reg:CC CC_REGNUM) + (compare:CC (ashift:SI (match_dup 1) (const_int 1)) + (const_int 0))) + (set (match_dup 0) (ashift:SI (match_dup 1) (const_int 1)))]) + (set (match_dup 2) (plus:SI (plus:SI (match_dup 3) (match_dup 3)) + (ltu:SI (reg:CC_C CC_REGNUM) (const_int 0))))] + { + operands[2] =3D gen_highpart (SImode, operands[0]); + operands[0] =3D gen_lowpart (SImode, operands[0]); + operands[3] =3D gen_highpart (SImode, operands[1]); + operands[1] =3D gen_lowpart (SImode, operands[1]); + } [(set_attr "conds" "clob") (set_attr "length" "8")] ) @@ -3888,18 +3901,43 @@ (define_expand "ashrdi3" " ) =20 -(define_insn "arm_ashrdi3_1bit" +(define_insn_and_split "arm_ashrdi3_1bit" [(set (match_operand:DI 0 "s_register_operand" "=3Dr,&r") (ashiftrt:DI (match_operand:DI 1 "s_register_operand" "0,r") (const_int 1))) (clobber (reg:CC CC_REGNUM))] "TARGET_32BIT" - "movs\\t%R0, %R1, asr #1\;mov\\t%Q0, %Q1, rrx" + "#" ; "movs\\t%R0, %R1, asr #1\;mov\\t%Q0, %Q1, rrx" + "&& reload_completed" + [(parallel [(set (reg:CC CC_REGNUM) + (compare:CC (ashiftrt:SI (match_dup 3) (const_int 1)) + (const_int 0))) + (set (match_dup 2) (ashiftrt:SI (match_dup 3) (const_int 1))= )]) + (set (match_dup 0) (unspec:SI [(match_dup 1) + (reg:CC_C CC_REGNUM)] + UNSPEC_RRX))] + { + operands[2] =3D gen_highpart (SImode, operands[0]); + operands[0] =3D gen_lowpart (SImode, operands[0]); + operands[3] =3D gen_highpart (SImode, operands[1]); + operands[1] =3D gen_lowpart (SImode, operands[1]); + } [(set_attr "conds" "clob") - (set_attr "insn" "mov") (set_attr "length" "8")] ) =20 +(define_insn "*rrx" + [(set (match_operand:SI 0 "s_register_operand" "=3Dr") + (unspec:SI [(match_operand:SI 1 "s_register_operand" "r") + (reg:CC_C CC_REGNUM)] + UNSPEC_RRX))] + "TARGET_32BIT" + "mov\\t%0, %1, rrx" + [(set_attr "conds" "use") + (set_attr "insn" "mov") + (set_attr "type" "alu_shift")] +) + (define_expand "ashrsi3" [(set (match_operand:SI 0 "s_register_operand" "") (ashiftrt:SI (match_operand:SI 1 "s_register_operand" "") @@ -3968,15 +4006,28 @@ (define_expand "lshrdi3" " ) =20 -(define_insn "arm_lshrdi3_1bit" +(define_insn_and_split "arm_lshrdi3_1bit" [(set (match_operand:DI 0 "s_register_operand" "=3Dr,&r") (lshiftrt:DI (match_operand:DI 1 "s_register_operand" "0,r") (const_int 1))) (clobber (reg:CC CC_REGNUM))] "TARGET_32BIT" - "movs\\t%R0, %R1, lsr #1\;mov\\t%Q0, %Q1, rrx" + "#" ; "movs\\t%R0, %R1, lsr #1\;mov\\t%Q0, %Q1, rrx" + "&& reload_completed" + [(parallel [(set (reg:CC CC_REGNUM) + (compare:CC (lshiftrt:SI (match_dup 3) (const_int 1)) + (const_int 0))) + (set (match_dup 2) (lshiftrt:SI (match_dup 3) (const_int 1))= )]) + (set (match_dup 0) (unspec:SI [(match_dup 1) + (reg:CC_C CC_REGNUM)] + UNSPEC_RRX))] + { + operands[2] =3D gen_highpart (SImode, operands[0]); + operands[0] =3D gen_lowpart (SImode, operands[0]); + operands[3] =3D gen_highpart (SImode, operands[1]); + operands[1] =3D gen_lowpart (SImode, operands[1]); + } [(set_attr "conds" "clob") - (set_attr "insn" "mov") (set_attr "length" "8")] ) =20 @@ -4064,6 +4115,23 @@ (define_insn "*arm_shiftsi3" (const_string "alu_shift_reg")))] ) =20 +(define_insn "*shiftsi3_compare" + [(set (reg:CC CC_REGNUM) + (compare:CC (match_operator:SI 3 "shift_operator" + [(match_operand:SI 1 "s_register_operand" "r") + (match_operand:SI 2 "arm_rhs_operand" "rM")]) + (const_int 0))) + (set (match_operand:SI 0 "s_register_operand" "=3Dr") + (match_op_dup 3 [(match_dup 1) (match_dup 2)]))] + "TARGET_32BIT" + "* return arm_output_shift(operands, 1);" + [(set_attr "conds" "set") + (set_attr "shift" "1") + (set (attr "type") (if_then_else (match_operand 2 "const_int_operand" "= ") + (const_string "alu_shift") + (const_string "alu_shift_reg")))] +) + (define_insn "*shiftsi3_compare0" [(set (reg:CC_NOOV CC_REGNUM) (compare:CC_NOOV (match_operator:SI 3 "shift_operator" diff --git a/gcc/config/arm/unspecs.md b/gcc/config/arm/unspecs.md index c3fb03256ceb1049d3cbb55d89075abb803f97c3..000000000000000000000000000= 0000000000000 100644 --- a/gcc/config/arm/unspecs.md +++ b/gcc/config/arm/unspecs.md @@ -83,6 +83,8 @@ (define_c_enum "unspec" [ ; FPSCR rounding mode and signal inexactness. UNSPEC_VRINTA ; Represent a float to integral float rounding ; towards nearest, ties away from zero. + UNSPEC_RRX ; Rotate Right with Extend shifts register right + ; by one place, with Carry flag shifted into bit[3= 1]. ]) =20 (define_c_enum "unspec" [ ------=_NextPart_000_0024_01CE0E07.C10B3460--