From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from server.nextmovesoftware.com (server.nextmovesoftware.com [162.254.253.69]) by sourceware.org (Postfix) with ESMTPS id 4B818385AFA8 for ; Thu, 20 Jul 2023 07:44:06 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 4B818385AFA8 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=nextmovesoftware.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=nextmovesoftware.com DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=nextmovesoftware.com; s=default; h=Content-Transfer-Encoding:Content-Type: MIME-Version:Message-ID:Date:Subject:In-Reply-To:References:Cc:To:From:Sender :Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Id:List-Help: List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=Y9bx4oGpRHP6Z8CbKX86kFDb7lW6w1OMv3aX7NZqTCs=; b=KmDLDTsXCwLmGcFdxhN1sGgILK yxJ+au5uD11m1jpl0lZrPRIk94O0GC1AJ+emLr//2WaNePiLXm5ZZ3nKJridkHj0nJ3FyNun7CNS/ ZFQ1hmqLzAstzfcVuN+w8gGDZ/Znx8pYzib0sLtaWnJglto6W3n7ywAOCmsT1M70ROpJWwCV4upJC qKqjuu4RUy4JvXPqDSzfkTb+Tu6EhXi1v2Zxd3f1h8h1FzMPZFaHQwyNqWNTW5ZLQAUSo5MXDoMhp aa6jFhHzhNWCdP3zeMYCzGn+y/yuoSJSYHma/V03MyxuwQEXf1zb3fqkI0W3/O6khfi0fGp7QM/3m LYktKDgA==; Received: from host86-161-68-50.range86-161.btcentralplus.com ([86.161.68.50]:50686 helo=Dell) by server.nextmovesoftware.com with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.96) (envelope-from ) id 1qMOKS-0005te-2k; Thu, 20 Jul 2023 03:44:05 -0400 From: "Roger Sayle" To: "'Uros Bizjak'" Cc: References: <009201d9ba7c$a64374d0$f2ca5e70$@nextmovesoftware.com> In-Reply-To: Subject: RE: [x86_64 PATCH] More TImode parameter passing improvements. Date: Thu, 20 Jul 2023 08:44:03 +0100 Message-ID: <002501d9badd$f5675930$e0360b90$@nextmovesoftware.com> MIME-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable X-Mailer: Microsoft Outlook 16.0 Thread-Index: AQFmWcjbRoIbnMwJ+TAQ9d0ZJuzIDAC+/gpdsKMLJgA= Content-Language: en-gb X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - server.nextmovesoftware.com X-AntiAbuse: Original Domain - gcc.gnu.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - nextmovesoftware.com X-Get-Message-Sender-Via: server.nextmovesoftware.com: authenticated_id: roger@nextmovesoftware.com X-Authenticated-Sender: server.nextmovesoftware.com: roger@nextmovesoftware.com X-Source: X-Source-Args: X-Source-Dir: X-Spam-Status: No, score=-10.9 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,KAM_SHORT,RCVD_IN_BARRACUDACENTRAL,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Hi Uros, > From: Uros Bizjak > Sent: 20 July 2023 07:50 >=20 > On Wed, Jul 19, 2023 at 10:07=E2=80=AFPM Roger Sayle = > wrote: > > > > This patch is the next piece of a solution to the x86_64 ABI issues = in > > PR 88873. This splits the *concat3_3 = define_insn_and_split > > into two patterns, a TARGET_64BIT *concatditi3_3 and a !TARGET_64BIT > > *concatsidi3_3. This allows us to add an additional alternative to > > the the 64-bit version, enabling the register allocator to perform > > this operation using SSE registers, which is implemented/split after > > reload using vec_concatv2di. > > > > To demonstrate the improvement, the test case from PR88873: > > > > typedef struct { double x, y; } s_t; > > > > s_t foo (s_t a, s_t b, s_t c) > > { > > return (s_t){ __builtin_fma(a.x, b.x, c.x), __builtin_fma (a.y, = b.y, > > c.y) }; } > > > > when compiled with -O2 -march=3Dcascadelake, currently generates: > > > > foo: vmovq %xmm2, -56(%rsp) > > movq -56(%rsp), %rax > > vmovq %xmm3, -48(%rsp) > > vmovq %xmm4, -40(%rsp) > > movq -48(%rsp), %rcx > > vmovq %xmm5, -32(%rsp) > > vmovq %rax, %xmm6 > > movq -40(%rsp), %rax > > movq -32(%rsp), %rsi > > vpinsrq $1, %rcx, %xmm6, %xmm6 > > vmovq %xmm0, -24(%rsp) > > vmovq %rax, %xmm7 > > vmovq %xmm1, -16(%rsp) > > vmovapd %xmm6, %xmm2 > > vpinsrq $1, %rsi, %xmm7, %xmm7 > > vfmadd132pd -24(%rsp), %xmm7, %xmm2 > > vmovapd %xmm2, -56(%rsp) > > vmovsd -48(%rsp), %xmm1 > > vmovsd -56(%rsp), %xmm0 > > ret > > > > with this change, we avoid many of the reloads via memory, > > > > foo: vpunpcklqdq %xmm3, %xmm2, %xmm7 > > vpunpcklqdq %xmm1, %xmm0, %xmm6 > > vpunpcklqdq %xmm5, %xmm4, %xmm2 > > vmovdqa %xmm7, -24(%rsp) > > vmovdqa %xmm6, %xmm1 > > movq -16(%rsp), %rax > > vpinsrq $1, %rax, %xmm7, %xmm4 > > vmovapd %xmm4, %xmm6 > > vfmadd132pd %xmm1, %xmm2, %xmm6 > > vmovapd %xmm6, -24(%rsp) > > vmovsd -16(%rsp), %xmm1 > > vmovsd -24(%rsp), %xmm0 > > ret > > > > > > This patch has been tested on x86_64-pc-linux-gnu with make = bootstrap > > and make -k check, both with and without --target_board=3Dunix{-m32} > > with no new failures. Ok for mainline? > > > > > > 2023-07-19 Roger Sayle > > > > gcc/ChangeLog > > * config/i386/i386-expand.cc (ix86_expand_move): Don't call > > force_reg, to use SUBREG rather than create a new pseudo = when > > inserting DFmode fields into TImode with = insvti_{high,low}part. > > (*concat3_3): Split into two = define_insn_and_split... > > (*concatditi3_3): 64-bit implementation. Provide = alternative > > that allows register allocation to use SSE registers that is > > split into vec_concatv2di after reload. > > (*concatsidi3_3): 32-bit implementation. > > > > gcc/testsuite/ChangeLog > > * gcc.target/i386/pr88873.c: New test case. >=20 > diff --git a/gcc/config/i386/i386-expand.cc = b/gcc/config/i386/i386-expand.cc > index f9b0dc6..9c3febe 100644 > --- a/gcc/config/i386/i386-expand.cc > +++ b/gcc/config/i386/i386-expand.cc > @@ -558,7 +558,7 @@ ix86_expand_move (machine_mode mode, rtx > operands[]) > op0 =3D SUBREG_REG (op0); > tmp =3D gen_rtx_AND (TImode, copy_rtx (op0), tmp); > if (mode =3D=3D DFmode) > - op1 =3D force_reg (DImode, gen_lowpart (DImode, op1)); > + op1 =3D gen_lowpart (DImode, op1); >=20 > Please note that gen_lowpart will ICE when op1 is a SUBREG. This is = the reason > that we need to first force a SUBREG to a register and then perform = gen_lowpart, > and it is necessary to avoid ICE. The good news is that we know op1 is a register, as this is tested by "&& REG_P (op1)" on line 551. You'll also notice that I'm not removing the force_reg from before the call to gen_lowpart, but removing the call to force_reg after the call to gen_lowpart. When I originally wrote = this, the hope was that placing this SUBREG in its own pseudo would help with register allocation/CSE. Unfortunately, increasing the number of pseudos (in this case) increases compile-time (due to quadratic = behaviour in LRA), as shown by PR rtl-optimization/110587, and keeping the DF->DI conversion in a SUBREG inside the insvti_{high,low}part allows the register allocator to see the DF->DI->TI sequence in a single pattern, and hence choose to keep the TI mode in SSE registers, rather than use a pair of reloads, to write the DF value to memory, then read it back as a scalar in DImode, and perhaps the same again to go the other way. > op1 =3D gen_rtx_ZERO_EXTEND (TImode, op1); > op1 =3D gen_rtx_IOR (TImode, tmp, op1); > } > @@ -570,7 +570,7 @@ ix86_expand_move (machine_mode mode, rtx > operands[]) > op0 =3D SUBREG_REG (op0); > tmp =3D gen_rtx_AND (TImode, copy_rtx (op0), tmp); > if (mode =3D=3D DFmode) > - op1 =3D force_reg (DImode, gen_lowpart (DImode, op1)); > + op1 =3D gen_lowpart (DImode, op1); >=20 > Also here.