From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 12156 invoked by alias); 18 Feb 2013 18:45:12 -0000 Received: (qmail 12116 invoked by uid 22791); 18 Feb 2013 18:45:11 -0000 X-SWARE-Spam-Status: No, hits=-2.0 required=5.0 tests=AWL,BAYES_00,KHOP_RCVD_UNTRUST,KHOP_SPAMHAUS_DROP,KHOP_THREADED,MSGID_MULTIPLE_AT,RCVD_IN_DNSWL_LOW X-Spam-Check-By: sourceware.org Received: from service87.mimecast.com (HELO service87.mimecast.com) (91.220.42.44) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Mon, 18 Feb 2013 18:45:03 +0000 Received: from cam-owa1.Emea.Arm.com (fw-tnat.cambridge.arm.com [217.140.96.21]) by service87.mimecast.com; Mon, 18 Feb 2013 18:45:02 +0000 Received: from e103227vm ([10.1.255.212]) by cam-owa1.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.0); Mon, 18 Feb 2013 18:44:59 +0000 From: "Greta Yorsh" To: "Greta Yorsh" , "GCC Patches" Cc: "Richard Earnshaw" , "Ramana Radhakrishnan" , , References: <001101ce0e05$f5928a50$e0b79ef0$@yorsh@arm.com> In-Reply-To: <001101ce0e05$f5928a50$e0b79ef0$@yorsh@arm.com> Subject: [PATCH,ARM][6/n] Split min and max patterns Date: Mon, 18 Feb 2013 18:45:00 -0000 Message-ID: <002701ce0e08$0bebc0d0$23c34270$@yorsh@arm.com> MIME-Version: 1.0 X-MC-Unique: 113021818450200601 Content-Type: multipart/mixed; boundary="----=_NextPart_000_0028_01CE0E08.0BEBC0D0" Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org X-SW-Source: 2013-02/txt/msg00863.txt.bz2 This is a multi-part message in MIME format. ------=_NextPart_000_0028_01CE0E08.0BEBC0D0 Content-Type: text/plain; charset=WINDOWS-1252 Content-Transfer-Encoding: quoted-printable Content-length: 398 Convert define_insn into define_insn_and_split for various min and max patterns that output multiple assembly instructions. Use movsicc to emit RTL. A separate patch will split movsicc. gcc/ 2013-02-14 Greta Yorsh * config/arm/arm.md (arm_smax_insn): Convert define_insn into define_insn_and_split. (arm_smin_insn,arm_umaxsi3,arm_uminsi3): Likewise.= ------=_NextPart_000_0028_01CE0E08.0BEBC0D0 Content-Type: text/plain; name=6-split-min-max.v4.patch.txt Content-Transfer-Encoding: quoted-printable Content-Disposition: attachment; filename="6-split-min-max.v4.patch.txt" Content-length: 3939 commit 068f9449536fca959fd687ac8b7e0bdae898f8bd Author: Greta Date: Fri Feb 15 14:41:48 2013 +0000 8-split-min-max.v2.patch diff --git a/gcc/config/arm/arm.md b/gcc/config/arm/arm.md index 7c04840..5f5af3c 100644 --- a/gcc/config/arm/arm.md +++ b/gcc/config/arm/arm.md @@ -3443,15 +3443,23 @@ [(set_attr "predicable" "yes")] ) =20 -(define_insn "*arm_smax_insn" +(define_insn_and_split "*arm_smax_insn" [(set (match_operand:SI 0 "s_register_operand" "=3Dr,r") (smax:SI (match_operand:SI 1 "s_register_operand" "%0,?r") (match_operand:SI 2 "arm_rhs_operand" "rI,rI"))) (clobber (reg:CC CC_REGNUM))] "TARGET_ARM" - "@ - cmp\\t%1, %2\;movlt\\t%0, %2 - cmp\\t%1, %2\;movge\\t%0, %1\;movlt\\t%0, %2" + "#" + ; cmp\\t%1, %2\;movlt\\t%0, %2 + ; cmp\\t%1, %2\;movge\\t%0, %1\;movlt\\t%0, %2" + "TARGET_ARM" + [(set (reg:CC CC_REGNUM) + (compare:CC (match_dup 1) (match_dup 2))) + (set (match_dup 0) + (if_then_else:SI (ge:SI (reg:CC CC_REGNUM) (const_int 0)) + (match_dup 1) + (match_dup 2)))] + "" [(set_attr "conds" "clob") (set_attr "length" "8,12")] ) @@ -3483,15 +3491,23 @@ [(set_attr "predicable" "yes")] ) =20 -(define_insn "*arm_smin_insn" +(define_insn_and_split "*arm_smin_insn" [(set (match_operand:SI 0 "s_register_operand" "=3Dr,r") (smin:SI (match_operand:SI 1 "s_register_operand" "%0,?r") (match_operand:SI 2 "arm_rhs_operand" "rI,rI"))) (clobber (reg:CC CC_REGNUM))] "TARGET_ARM" - "@ - cmp\\t%1, %2\;movge\\t%0, %2 - cmp\\t%1, %2\;movlt\\t%0, %1\;movge\\t%0, %2" + "#" + ; cmp\\t%1, %2\;movge\\t%0, %2 + ; cmp\\t%1, %2\;movlt\\t%0, %1\;movge\\t%0, %2" + "TARGET_ARM" + [(set (reg:CC CC_REGNUM) + (compare:CC (match_dup 1) (match_dup 2))) + (set (match_dup 0) + (if_then_else:SI (lt:SI (reg:CC CC_REGNUM) (const_int 0)) + (match_dup 1) + (match_dup 2)))] + "" [(set_attr "conds" "clob") (set_attr "length" "8,12")] ) @@ -3506,16 +3522,24 @@ "" ) =20 -(define_insn "*arm_umaxsi3" +(define_insn_and_split "*arm_umaxsi3" [(set (match_operand:SI 0 "s_register_operand" "=3Dr,r,r") (umax:SI (match_operand:SI 1 "s_register_operand" "0,r,?r") (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI"))) (clobber (reg:CC CC_REGNUM))] "TARGET_ARM" - "@ - cmp\\t%1, %2\;movcc\\t%0, %2 - cmp\\t%1, %2\;movcs\\t%0, %1 - cmp\\t%1, %2\;movcs\\t%0, %1\;movcc\\t%0, %2" + "#" + ; cmp\\t%1, %2\;movcc\\t%0, %2 + ; cmp\\t%1, %2\;movcs\\t%0, %1 + ; cmp\\t%1, %2\;movcs\\t%0, %1\;movcc\\t%0, %2" + "TARGET_ARM" + [(set (reg:CC CC_REGNUM) + (compare:CC (match_dup 1) (match_dup 2))) + (set (match_dup 0) + (if_then_else:SI (geu:SI (reg:CC CC_REGNUM) (const_int 0)) + (match_dup 1) + (match_dup 2)))] + "" [(set_attr "conds" "clob") (set_attr "length" "8,8,12")] ) @@ -3530,16 +3554,24 @@ "" ) =20 -(define_insn "*arm_uminsi3" +(define_insn_and_split "*arm_uminsi3" [(set (match_operand:SI 0 "s_register_operand" "=3Dr,r,r") (umin:SI (match_operand:SI 1 "s_register_operand" "0,r,?r") (match_operand:SI 2 "arm_rhs_operand" "rI,0,rI"))) (clobber (reg:CC CC_REGNUM))] "TARGET_ARM" - "@ - cmp\\t%1, %2\;movcs\\t%0, %2 - cmp\\t%1, %2\;movcc\\t%0, %1 - cmp\\t%1, %2\;movcc\\t%0, %1\;movcs\\t%0, %2" + "#" + ; cmp\\t%1, %2\;movcs\\t%0, %2 + ; cmp\\t%1, %2\;movcc\\t%0, %1 + ; cmp\\t%1, %2\;movcc\\t%0, %1\;movcs\\t%0, %2" + "TARGET_ARM" + [(set (reg:CC CC_REGNUM) + (compare:CC (match_dup 1) (match_dup 2))) + (set (match_dup 0) + (if_then_else:SI (ltu:SI (reg:CC CC_REGNUM) (const_int 0)) + (match_dup 1) + (match_dup 2)))] + "" [(set_attr "conds" "clob") (set_attr "length" "8,8,12")] ) ------=_NextPart_000_0028_01CE0E08.0BEBC0D0--