From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 14236 invoked by alias); 17 Dec 2015 07:01:47 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 14225 invoked by uid 89); 17 Dec 2015 07:01:46 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=3.9 required=5.0 tests=AWL,BAYES_99,BAYES_999,KAM_ASCII_DIVIDERS,KAM_LAZY_DOMAIN_SECURITY,KAM_LOTSOFHASH,T_RP_MATCHES_RCVD autolearn=no version=3.3.2 spammy=chip, UD:libgcov.a, libma, libnosysa X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 17 Dec 2015 07:01:43 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 660664BF for ; Wed, 16 Dec 2015 23:01:17 -0800 (PST) Received: from SHAWIN202 (unknown [10.164.12.31]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 7E2C23F24D for ; Wed, 16 Dec 2015 23:01:41 -0800 (PST) From: "Thomas Preud'homme" To: References: <002a01d1388f$d32ac790$798056b0$@foss.arm.com> In-Reply-To: <002a01d1388f$d32ac790$798056b0$@foss.arm.com> Subject: RE: [arm-embedded][PATCH, libgcc/ARM 1/6] Fix Thumb-1 only == ARMv6-M & Thumb-2 only == ARMv7-M assumptions Date: Thu, 17 Dec 2015 07:01:00 -0000 Message-ID: <002c01d13898$c8484920$58d8db60$@foss.arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-SW-Source: 2015-12/txt/msg01688.txt.bz2 The following was committed, once rebased on top of the embedded branch (pa= tch was generated on top of gcc-5-branch): diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index 8c10ea3c9053e89b8eae1e5353b92d6020499409..bf1a0e874b1669f3ebe1e587055= 6a46b80686b82 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -2336,8 +2336,10 @@ extern int making_const_table; #define TARGET_ARM_ARCH \ (arm_base_arch) \ =20 -#define TARGET_ARM_V6M (!arm_arch_notm && !arm_arch_thumb2) -#define TARGET_ARM_V7M (!arm_arch_notm && arm_arch_thumb2) +#define TARGET_ARM_V6M (TARGET_ARM_ARCH =3D=3D BASE_ARCH_6M && !arm_arch_n= otm \ + && !arm_arch_thumb2) +#define TARGET_ARM_V7M (TARGET_ARM_ARCH =3D=3D BASE_ARCH_7M && !arm_arch_n= otm \ + && arm_arch_thumb2) =20 /* The highest Thumb instruction set version supported by the chip. */ #define TARGET_ARM_ARCH_ISA_THUMB \ diff --git a/gcc/config/arm/elf.h b/gcc/config/arm/elf.h index c56bbdff69466af8b2e8db70f99f33054748b650..fe06cd1a2857db44fb7c1d9407a= a6710a061d4df 100644 --- a/gcc/config/arm/elf.h +++ b/gcc/config/arm/elf.h @@ -149,8 +149,9 @@ while (0) =20 /* Horrible hack: We want to prevent some libgcc routines being included - for some multilibs. */ -#ifndef __ARM_ARCH_6M__ + for some multilibs. The condition should match the one in + libgcc/config/arm/lib1funcs.S. */ +#if __ARM_ARCH_ISA_ARM || __ARM_ARCH_ISA_THUMB !=3D 1 #undef L_fixdfsi #undef L_fixunsdfsi #undef L_truncdfsf2 diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/targ= et-supports.exp index 950db11637636f46e805beee3bd55ead62aec67e..35867a281a01cbbb3810013b17e= 3b2173eb275ee 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -2973,10 +2973,8 @@ proc check_effective_target_arm_cortex_m { } { return 0 } return [check_no_compiler_messages arm_cortex_m assembly { - #if !defined(__ARM_ARCH_7M__) \ - && !defined (__ARM_ARCH_7EM__) \ - && !defined (__ARM_ARCH_6M__) - #error !__ARM_ARCH_7M__ && !__ARM_ARCH_7EM__ && !__ARM_ARCH_6M__ + #if defined(__ARM_ARCH_ISA_ARM) + #error __ARM_ARCH_ISA_ARM is defined #endif int i; } "-mthumb"] diff --git a/libgcc/config/arm/bpabi-v6m.S b/libgcc/config/arm/bpabi-v6m.S index a1e164032a08d04f7e8be80094d3b054b4e8bed4..9ae0bb82d1b3e3f81baf73e11b4= 84f4212ea28e4 100644 --- a/libgcc/config/arm/bpabi-v6m.S +++ b/libgcc/config/arm/bpabi-v6m.S @@ -1,4 +1,4 @@ -/* Miscellaneous BPABI functions. ARMv6M implementation +/* Miscellaneous BPABI functions. Thumb-1 only implementation =20 Copyright (C) 2006-2015 Free Software Foundation, Inc. Contributed by CodeSourcery. diff --git a/libgcc/config/arm/lib1funcs.S b/libgcc/config/arm/lib1funcs.S index a1e41c292b22bcbd6b6ec9e11060d7a1f6e28fba..e8fd73f48a197fe4b81eaf73c13= a11f913bba9e0 100644 --- a/libgcc/config/arm/lib1funcs.S +++ b/libgcc/config/arm/lib1funcs.S @@ -124,7 +124,7 @@ see the files COPYING3 and COPYING.RUNTIME respectively= . If not, see && !defined(__thumb2__) \ && (!defined(__THUMB_INTERWORK__) \ || defined (__OPTIMIZE_SIZE__) \ - || defined(__ARM_ARCH_6M__))) + || !__ARM_ARCH_ISA_ARM)) # define __prefer_thumb__ #endif =20 @@ -305,7 +305,7 @@ LSYM(Lend_fde): =20 #ifdef __ARM_EABI__ .macro THUMB_LDIV0 name signed -#if defined(__ARM_ARCH_6M__) +#if !__ARM_ARCH_ISA_ARM && __ARM_ARCH_ISA_THUMB =3D=3D 1 =20 push {r0, lr} mov r0, #0 @@ -456,7 +456,7 @@ _L__\name: =20 #else /* !(__INTERWORKING_STUBS__ || __thumb2__) */ =20 -#ifdef __ARM_ARCH_6M__ +#if !__ARM_ARCH_ISA_ARM && __ARM_ARCH_ISA_THUMB =3D=3D 1 #define EQUIV .thumb_set #else .macro ARM_FUNC_START name sp_section=3D @@ -488,7 +488,7 @@ SYM (__\name): #endif .endm =20 -#ifndef __ARM_ARCH_6M__ +#if __ARM_ARCH_ISA_ARM || __ARM_ARCH_ISA_THUMB !=3D 1 .macro ARM_FUNC_ALIAS new old .globl SYM (__\new) EQUIV SYM (__\new), SYM (__\old) @@ -1213,7 +1213,7 @@ ARM_FUNC_START aeabi_uidivmod /* -----------------------------------------------------------------------= - */ #ifdef L_umodsi3 =20 -#ifdef __ARM_ARCH_EXT_IDIV__ +#if defined(__ARM_ARCH_EXT_IDIV__) && __ARM_ARCH_ISA_THUMB !=3D 1 =20 ARM_FUNC_START umodsi3 =20 @@ -1424,7 +1424,7 @@ ARM_FUNC_START aeabi_idivmod /* -----------------------------------------------------------------------= - */ #ifdef L_modsi3 =20 -#if defined(__ARM_ARCH_EXT_IDIV__) +#if defined(__ARM_ARCH_EXT_IDIV__) && __ARM_ARCH_ISA_THUMB !=3D 1 =20 ARM_FUNC_START modsi3 =20 @@ -1685,14 +1685,14 @@ LSYM(Lover12): =20 #endif /* __symbian__ */ =20 -#if ((__ARM_ARCH__ > 5) && !defined(__ARM_ARCH_6M__)) \ +#if ((__ARM_ARCH__ > 5) && (__ARM_ARCH_ISA_ARM || __ARM_ARCH_ISA_THUMB != =3D 1)) \ || defined(__ARM_ARCH_5E__) || defined(__ARM_ARCH_5TE__) \ || defined(__ARM_ARCH_5TEJ__) #define HAVE_ARM_CLZ 1 #endif =20 #ifdef L_clzsi2 -#if defined(__ARM_ARCH_6M__) +#if !__ARM_ARCH_ISA_ARM && __ARM_ARCH_ISA_THUMB =3D=3D 1 FUNC_START clzsi2 mov r1, #28 mov r3, #1 @@ -1753,7 +1753,7 @@ ARM_FUNC_START clzsi2 #ifdef L_clzdi2 #if !defined(HAVE_ARM_CLZ) =20 -# if defined(__ARM_ARCH_6M__) +# if !__ARM_ARCH_ISA_ARM && __ARM_ARCH_ISA_THUMB =3D=3D 1 FUNC_START clzdi2 push {r4, lr} # else @@ -1778,7 +1778,7 @@ ARM_FUNC_START clzdi2 bl __clzsi2 # endif 2: -# if defined(__ARM_ARCH_6M__) +# if !__ARM_ARCH_ISA_ARM && __ARM_ARCH_ISA_THUMB =3D=3D 1 pop {r4, pc} # else RETLDM r4 @@ -1800,7 +1800,7 @@ ARM_FUNC_START clzdi2 #endif /* L_clzdi2 */ =20 #ifdef L_ctzsi2 -#if defined(__ARM_ARCH_6M__) +#if !__ARM_ARCH_ISA_ARM && __ARM_ARCH_ISA_THUMB =3D=3D 1 FUNC_START ctzsi2 neg r1, r0 and r0, r0, r1 @@ -1915,7 +1915,7 @@ ARM_FUNC_START ctzsi2 =20 /* Don't bother with the old interworking routines for Thumb-2. */ /* ??? Maybe only omit these on "m" variants. */ -#if !defined(__thumb2__) && !defined(__ARM_ARCH_6M__) +#if __ARM_ARCH_ISA_ARM && __ARM_ARCH_ISA_THUMB =3D=3D 1 =20 #if defined L_interwork_call_via_rX =20 @@ -2150,11 +2150,12 @@ LSYM(Lchange_\register): #endif /* Arch supports thumb. */ =20 #ifndef __symbian__ -#ifndef __ARM_ARCH_6M__ +/* The condition here must match the one in gcc/config/arm/elf.h. */ +#if __ARM_ARCH_ISA_ARM || __ARM_ARCH_ISA_THUMB !=3D 1 #include "ieee754-df.S" #include "ieee754-sf.S" #include "bpabi.S" -#else /* __ARM_ARCH_6M__ */ +#else /* !__ARM_ARCH_ISA_ARM && __ARM_ARCH_ISA_THUMB =3D=3D 1 */ #include "bpabi-v6m.S" -#endif /* __ARM_ARCH_6M__ */ +#endif /* !__ARM_ARCH_ISA_ARM && __ARM_ARCH_ISA_THUMB =3D=3D 1 */ #endif /* !__symbian__ */ diff --git a/libgcc/config/arm/libunwind.S b/libgcc/config/arm/libunwind.S index cac102231914aa85320ff579168a17afa8479f67..393ec8aaee43948154956b72960= 860902400df50 100644 --- a/libgcc/config/arm/libunwind.S +++ b/libgcc/config/arm/libunwind.S @@ -58,7 +58,7 @@ #endif #endif =20 -#ifdef __ARM_ARCH_6M__ +#if !__ARM_ARCH_ISA_ARM && __ARM_ARCH_ISA_THUMB =3D=3D 1 =20 /* r0 points to a 16-word block. Upload these values to the actual core state. */ @@ -169,7 +169,7 @@ FUNC_START gnu_Unwind_Save_WMMXC UNPREFIX \name .endm =20 -#else /* !__ARM_ARCH_6M__ */ +#else /* __ARM_ARCH_ISA_ARM || __ARM_ARCH_ISA_THUMB !=3D 1 */ =20 /* r0 points to a 16-word block. Upload these values to the actual core state. */ @@ -351,7 +351,7 @@ ARM_FUNC_START gnu_Unwind_Save_WMMXC UNPREFIX \name .endm =20 -#endif /* !__ARM_ARCH_6M__ */ +#endif /* __ARM_ARCH_ISA_ARM || __ARM_ARCH_ISA_THUMB !=3D 1 */ =20 UNWIND_WRAPPER _Unwind_RaiseException 1 UNWIND_WRAPPER _Unwind_Resume 1 diff --git a/libgcc/config/arm/t-softfp b/libgcc/config/arm/t-softfp index 4ede438baf6a297737e52db00395f6c3a359f681..554ec9bc47b04445e79e84b1f95= 7bf88680c08d1 100644 --- a/libgcc/config/arm/t-softfp +++ b/libgcc/config/arm/t-softfp @@ -1,2 +1,2 @@ -softfp_wrap_start :=3D '\#ifdef __ARM_ARCH_6M__' +softfp_wrap_start :=3D '\#if !__ARM_ARCH_ISA_ARM && __ARM_ARCH_ISA_THUMB = =3D=3D 1' softfp_wrap_end :=3D '\#endif' Best regards, Thomas > -----Original Message----- > From: gcc-patches-owner@gcc.gnu.org [mailto:gcc-patches- > owner@gcc.gnu.org] On Behalf Of Thomas Preud'homme > Sent: Thursday, December 17, 2015 1:58 PM > To: gcc-patches@gcc.gnu.org > Subject: [arm-embedded][PATCH, libgcc/ARM 1/6] Fix Thumb-1 only =3D=3D > ARMv6-M & Thumb-2 only =3D=3D ARMv7-M assumptions >=20 > Hi, >=20 > We decided to apply the following patch to the ARM embedded 5 branch. > This is *not* intended for trunk for now. We will send a separate email > for trunk. >=20 > This patch is part of a patch series to add support for ARMv8-M[1] to GCC. > This specific patch fixes some assumptions related to M profile > architectures. Currently GCC (mostly libgcc) contains several assumptions > that the only ARM architecture with Thumb-1 only instructions is ARMv6- > M and the only one with Thumb-2 only instructions is ARMv7-M. ARMv8- > M [1] make this wrong since ARMv8-M baseline is also (mostly) Thumb-1 > only and ARMv8-M mainline is also Thumb-2 only. This patch replace > checks for __ARM_ARCH_*__ for checks against > __ARM_ARCH_ISA_THUMB and __ARM_ARCH_ISA_ARM instead. For > instance, Thumb-1 only can be checked with > #if !defined(__ARM_ARCH_ISA_ARM) && (__ARM_ARCH_ISA_THUMB > =3D=3D 1). It also fixes the guard for DIV code to not apply to ARMv8-M > Baseline since it uses Thumb-2 instructions. >=20 > [1] For a quick overview of ARMv8-M please refer to the initial cover > letter. >=20 > ChangeLog entries are as follow: >=20 >=20 > *** gcc/ChangeLog *** >=20 > 2015-11-13 Thomas Preud'homme >=20 > * config/arm/elf.h: Use __ARM_ARCH_ISA_THUMB and > __ARM_ARCH_ISA_ARM to > decide whether to prevent some libgcc routines being included for > some > multilibs rather than __ARM_ARCH_6M__ and add comment to > indicate the > link between this condition and the one in > libgcc/config/arm/lib1func.S. > * config/arm/arm.h (TARGET_ARM_V6M): Add check to > TARGET_ARM_ARCH. > (TARGET_ARM_V7M): Likewise. >=20 >=20 > *** gcc/testsuite/ChangeLog *** >=20 > 2015-11-10 Thomas Preud'homme >=20 > * lib/target-supports.exp (check_effective_target_arm_cortex_m): > Use > __ARM_ARCH_ISA_ARM to test for Cortex-M devices. >=20 >=20 > *** libgcc/ChangeLog *** >=20 > 2015-11-13 Thomas Preud'homme >=20 > * config/arm/bpabi-v6m.S: Fix header comment to mention Thumb- > 1 rather > than ARMv6-M. > * config/arm/lib1funcs.S (__prefer_thumb__): Define among other > cases > for all Thumb-1 only targets. > (__only_thumb1__): Define for all Thumb-1 only targets. > (THUMB_LDIV0): Test for __only_thumb1__ rather than > __ARM_ARCH_6M__. > (EQUIV): Likewise. > (ARM_FUNC_ALIAS): Likewise. > (umodsi3): Add check to __only_thumb1__ to guard the idiv version. > (modsi3): Likewise. > (HAVE_ARM_CLZ): Test for __only_thumb1__ rather than > __ARM_ARCH_6M__. > (clzsi2): Likewise. > (clzdi2): Likewise. > (ctzsi2): Likewise. > (L_interwork_call_via_rX): Test for __ARM_ARCH_ISA_ARM rather > than > __ARM_ARCH_6M__ in guard for checking whether it is defined. > (final includes): Test for __only_thumb1__ rather than > __ARM_ARCH_6M__ and add comment to indicate the connection > between > this condition and the one in gcc/config/arm/elf.h. > * config/arm/libunwind.S: Test for __ARM_ARCH_ISA_THUMB and > __ARM_ARCH_ISA_ARM rather than __ARM_ARCH_6M__. > * config/arm/t-softfp: Likewise. >=20 >=20 > diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h > index 6ed8ad3..06abcf3 100644 > --- a/gcc/config/arm/arm.h > +++ b/gcc/config/arm/arm.h > @@ -2181,8 +2181,10 @@ extern int making_const_table; > #define TARGET_ARM_ARCH \ > (arm_base_arch) \ >=20 > -#define TARGET_ARM_V6M (!arm_arch_notm && !arm_arch_thumb2) > -#define TARGET_ARM_V7M (!arm_arch_notm && arm_arch_thumb2) > +#define TARGET_ARM_V6M (TARGET_ARM_ARCH =3D=3D BASE_ARCH_6M > && !arm_arch_notm \ > + && !arm_arch_thumb2) > +#define TARGET_ARM_V7M (TARGET_ARM_ARCH =3D=3D BASE_ARCH_7M > && !arm_arch_notm \ > + && arm_arch_thumb2) >=20 > /* The highest Thumb instruction set version supported by the chip. */ > #define TARGET_ARM_ARCH_ISA_THUMB \ > diff --git a/gcc/config/arm/elf.h b/gcc/config/arm/elf.h > index 3795728..579a580 100644 > --- a/gcc/config/arm/elf.h > +++ b/gcc/config/arm/elf.h > @@ -148,8 +148,9 @@ > while (0) >=20 > /* Horrible hack: We want to prevent some libgcc routines being > included > - for some multilibs. */ > -#ifndef __ARM_ARCH_6M__ > + for some multilibs. The condition should match the one in > + libgcc/config/arm/lib1funcs.S. */ > +#if __ARM_ARCH_ISA_ARM || __ARM_ARCH_ISA_THUMB !=3D 1 > #undef L_fixdfsi > #undef L_fixunsdfsi > #undef L_truncdfsf2 > diff --git a/gcc/testsuite/lib/target-supports.exp > b/gcc/testsuite/lib/target-supports.exp > index 254c4e3..6cf7ee1 100644 > --- a/gcc/testsuite/lib/target-supports.exp > +++ b/gcc/testsuite/lib/target-supports.exp > @@ -3210,10 +3210,8 @@ proc check_effective_target_arm_cortex_m { } > { > return 0 > } > return [check_no_compiler_messages arm_cortex_m assembly { > - #if !defined(__ARM_ARCH_7M__) \ > - && !defined (__ARM_ARCH_7EM__) \ > - && !defined (__ARM_ARCH_6M__) > - #error !__ARM_ARCH_7M__ && !__ARM_ARCH_7EM__ > && !__ARM_ARCH_6M__ > + #if defined(__ARM_ARCH_ISA_ARM) > + #error __ARM_ARCH_ISA_ARM is defined > #endif > int i; > } "-mthumb"] > diff --git a/libgcc/config/arm/bpabi-v6m.S b/libgcc/config/arm/bpabi- > v6m.S > index a1e1640..9ae0bb8 100644 > --- a/libgcc/config/arm/bpabi-v6m.S > +++ b/libgcc/config/arm/bpabi-v6m.S > @@ -1,4 +1,4 @@ > -/* Miscellaneous BPABI functions. ARMv6M implementation > +/* Miscellaneous BPABI functions. Thumb-1 only implementation >=20 > Copyright (C) 2006-2015 Free Software Foundation, Inc. > Contributed by CodeSourcery. > diff --git a/libgcc/config/arm/lib1funcs.S b/libgcc/config/arm/lib1funcs.S > index 252efcb..befb042 100644 > --- a/libgcc/config/arm/lib1funcs.S > +++ b/libgcc/config/arm/lib1funcs.S > @@ -124,7 +124,7 @@ see the files COPYING3 and COPYING.RUNTIME > respectively. If not, see > && !defined(__thumb2__) \ > && (!defined(__THUMB_INTERWORK__) \ > || defined (__OPTIMIZE_SIZE__) \ > - || defined(__ARM_ARCH_6M__))) > + || !__ARM_ARCH_ISA_ARM)) > # define __prefer_thumb__ > #endif >=20 > @@ -305,7 +305,7 @@ LSYM(Lend_fde): >=20 > #ifdef __ARM_EABI__ > .macro THUMB_LDIV0 name signed > -#if defined(__ARM_ARCH_6M__) > +#if !__ARM_ARCH_ISA_ARM && __ARM_ARCH_ISA_THUMB =3D=3D 1 > .ifc \signed, unsigned > cmp r0, #0 > beq 1f > @@ -478,7 +478,7 @@ _L__\name: >=20 > #else /* !(__INTERWORKING_STUBS__ || __thumb2__) */ >=20 > -#ifdef __ARM_ARCH_6M__ > +#if !__ARM_ARCH_ISA_ARM && __ARM_ARCH_ISA_THUMB =3D=3D 1 > #define EQUIV .thumb_set > #else > .macro ARM_FUNC_START name sp_section=3D > @@ -510,7 +510,7 @@ SYM (__\name): > #endif > .endm >=20 > -#ifndef __ARM_ARCH_6M__ > +#if __ARM_ARCH_ISA_ARM || __ARM_ARCH_ISA_THUMB !=3D 1 > .macro ARM_FUNC_ALIAS new old > .globl SYM (__\new) > EQUIV SYM (__\new), SYM (__\old) > @@ -1054,7 +1054,7 @@ ARM_FUNC_START aeabi_uidivmod > /* ---------------------------------------------------------------------= --- */ > #ifdef L_umodsi3 >=20 > -#ifdef __ARM_ARCH_EXT_IDIV__ > +#if defined(__ARM_ARCH_EXT_IDIV__) && > __ARM_ARCH_ISA_THUMB !=3D 1 >=20 > ARM_FUNC_START umodsi3 >=20 > @@ -1240,7 +1240,7 @@ ARM_FUNC_START aeabi_idivmod > /* ---------------------------------------------------------------------= --- */ > #ifdef L_modsi3 >=20 > -#if defined(__ARM_ARCH_EXT_IDIV__) > +#if defined(__ARM_ARCH_EXT_IDIV__) && > __ARM_ARCH_ISA_THUMB !=3D 1 >=20 > ARM_FUNC_START modsi3 >=20 > @@ -1508,14 +1508,14 @@ LSYM(Lover12): >=20 > #endif /* __symbian__ */ >=20 > -#if ((__ARM_ARCH__ > 5) && !defined(__ARM_ARCH_6M__)) \ > +#if ((__ARM_ARCH__ > 5) && (__ARM_ARCH_ISA_ARM || > __ARM_ARCH_ISA_THUMB !=3D 1)) \ > || defined(__ARM_ARCH_5E__) || defined(__ARM_ARCH_5TE__) \ > || defined(__ARM_ARCH_5TEJ__) > #define HAVE_ARM_CLZ 1 > #endif >=20 > #ifdef L_clzsi2 > -#if defined(__ARM_ARCH_6M__) > +#if !__ARM_ARCH_ISA_ARM && __ARM_ARCH_ISA_THUMB =3D=3D 1 > FUNC_START clzsi2 > mov r1, #28 > mov r3, #1 > @@ -1576,7 +1576,7 @@ ARM_FUNC_START clzsi2 > #ifdef L_clzdi2 > #if !defined(HAVE_ARM_CLZ) >=20 > -# if defined(__ARM_ARCH_6M__) > +# if !__ARM_ARCH_ISA_ARM && __ARM_ARCH_ISA_THUMB =3D=3D 1 > FUNC_START clzdi2 > push {r4, lr} > # else > @@ -1601,7 +1601,7 @@ ARM_FUNC_START clzdi2 > bl __clzsi2 > # endif > 2: > -# if defined(__ARM_ARCH_6M__) > +# if !__ARM_ARCH_ISA_ARM && __ARM_ARCH_ISA_THUMB =3D=3D 1 > pop {r4, pc} > # else > RETLDM r4 > @@ -1623,7 +1623,7 @@ ARM_FUNC_START clzdi2 > #endif /* L_clzdi2 */ >=20 > #ifdef L_ctzsi2 > -#if defined(__ARM_ARCH_6M__) > +#if !__ARM_ARCH_ISA_ARM && __ARM_ARCH_ISA_THUMB =3D=3D 1 > FUNC_START ctzsi2 > neg r1, r0 > and r0, r0, r1 > @@ -1738,7 +1738,7 @@ ARM_FUNC_START ctzsi2 >=20 > /* Don't bother with the old interworking routines for Thumb-2. */ > /* ??? Maybe only omit these on "m" variants. */ > -#if !defined(__thumb2__) && !defined(__ARM_ARCH_6M__) > +#if !defined(__thumb2__) && __ARM_ARCH_ISA_ARM >=20 > #if defined L_interwork_call_via_rX >=20 > @@ -1983,11 +1983,12 @@ LSYM(Lchange_\register): > .endm >=20 > #ifndef __symbian__ > -#ifndef __ARM_ARCH_6M__ > +/* The condition here must match the one in gcc/config/arm/elf.h. */ > +#if __ARM_ARCH_ISA_ARM || __ARM_ARCH_ISA_THUMB !=3D 1 > #include "ieee754-df.S" > #include "ieee754-sf.S" > #include "bpabi.S" > -#else /* __ARM_ARCH_6M__ */ > +#else /* !__ARM_ARCH_ISA_ARM && __ARM_ARCH_ISA_THUMB =3D=3D > 1 */ > #include "bpabi-v6m.S" > -#endif /* __ARM_ARCH_6M__ */ > +#endif /* !__ARM_ARCH_ISA_ARM && __ARM_ARCH_ISA_THUMB =3D=3D > 1 */ > #endif /* !__symbian__ */ > diff --git a/libgcc/config/arm/libunwind.S > b/libgcc/config/arm/libunwind.S > index cac1022..393ec8a 100644 > --- a/libgcc/config/arm/libunwind.S > +++ b/libgcc/config/arm/libunwind.S > @@ -58,7 +58,7 @@ > #endif > #endif >=20 > -#ifdef __ARM_ARCH_6M__ > +#if !__ARM_ARCH_ISA_ARM && __ARM_ARCH_ISA_THUMB =3D=3D 1 >=20 > /* r0 points to a 16-word block. Upload these values to the actual core > state. */ > @@ -169,7 +169,7 @@ FUNC_START gnu_Unwind_Save_WMMXC > UNPREFIX \name > .endm >=20 > -#else /* !__ARM_ARCH_6M__ */ > +#else /* __ARM_ARCH_ISA_ARM || __ARM_ARCH_ISA_THUMB !=3D 1 > */ >=20 > /* r0 points to a 16-word block. Upload these values to the actual core > state. */ > @@ -351,7 +351,7 @@ ARM_FUNC_START gnu_Unwind_Save_WMMXC > UNPREFIX \name > .endm >=20 > -#endif /* !__ARM_ARCH_6M__ */ > +#endif /* __ARM_ARCH_ISA_ARM || __ARM_ARCH_ISA_THUMB !=3D 1 > */ >=20 > UNWIND_WRAPPER _Unwind_RaiseException 1 > UNWIND_WRAPPER _Unwind_Resume 1 > diff --git a/libgcc/config/arm/t-softfp b/libgcc/config/arm/t-softfp > index 4ede438..554ec9b 100644 > --- a/libgcc/config/arm/t-softfp > +++ b/libgcc/config/arm/t-softfp > @@ -1,2 +1,2 @@ > -softfp_wrap_start :=3D '\#ifdef __ARM_ARCH_6M__' > +softfp_wrap_start :=3D '\#if !__ARM_ARCH_ISA_ARM && > __ARM_ARCH_ISA_THUMB =3D=3D 1' > softfp_wrap_end :=3D '\#endif' >=20 >=20 > Testing: >=20 > * Toolchain was built successfully with and without the ARMv8-M > support patches with the following multilib list: armv6-m,armv7- > m,armv7e-m,cortex-m7. The code generation for crtbegin.o, crtend.o, > crti.o, crtn.o, libgcc.a, libgcov.a, libc.a, libg.a, libgloss-linux.a, li= bm.a, > libnosys.a, librdimon.a, librdpmon.a, libstdc++.a and libsupc++.a is > unchanged for all these targets. >=20 > * GCC also showed no testsuite regression when targeting ARMv8-M > Baseline compared to ARMv6-M on ARM Fast Models and when > targeting ARMv6-M and ARMv7-M (compared to without the patch) > * GCC was bootstrapped successfully targeting Thumb-1 and targeting > Thumb-2