From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from server.nextmovesoftware.com (server.nextmovesoftware.com [162.254.253.69]) by sourceware.org (Postfix) with ESMTPS id 7F1A93857803 for ; Fri, 16 Jun 2023 13:27:07 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 7F1A93857803 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=nextmovesoftware.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=nextmovesoftware.com DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=nextmovesoftware.com; s=default; h=Content-Type:MIME-Version:Message-ID: Date:Subject:In-Reply-To:References:Cc:To:From:Sender:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Id: List-Help:List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=PSB92f/1kwcOft2wGbHMg4FPDIc/TDqLaEKri8NITRA=; b=NHJOvkBuqRVucOQDQpo9/L6miF JkQzZnqMXAKfzzi3lvr9CvoBd6GciMPr9NIWWSEb8sbseQ4oGJBEofBOrAXVFsXe5/dZLZSCve96t kt7NvL5ZSvQP7p9NJWUOe7sTK1E7a1nYgsZRVkLX7JThGcQSwKvi4w3trsd9a4ON4UMiwjsmUB4fl vg0C/ot3aTt9mfbjQ9H9U2K5JfcN8kXoUOuP63R8lVeQVm1Q1IPeBBY7UOoqeE2bcE3zZoIxCXGeG KWo8tApAuOZYQENvGukghlr+RAjPjisP15bp9BOlybP5fNJB+i/lO2qTCNMuBlfrkUpX+srCmtZWD mhb1CyeA==; Received: from [185.62.158.67] (port=54318 helo=Dell) by server.nextmovesoftware.com with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.96) (envelope-from ) id 1qA9Tm-0006Oy-28; Fri, 16 Jun 2023 09:27:06 -0400 From: "Roger Sayle" To: "'Uros Bizjak'" Cc: References: <00ce01d99e10$a7e04b20$f7a0e160$@nextmovesoftware.com> In-Reply-To: Subject: RE: [x86 PATCH] Convert ptestz of pandn into ptestc. Date: Fri, 16 Jun 2023 14:27:04 +0100 Message-ID: <005c01d9a056$3f025790$bd0706b0$@nextmovesoftware.com> MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="----=_NextPart_000_005D_01D9A05E.A0C6BF90" X-Mailer: Microsoft Outlook 16.0 Thread-Index: AQL5mGQAs1CDmej7knJirB/ICku16wJw7iCVrTnrmrA= Content-Language: en-gb X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - server.nextmovesoftware.com X-AntiAbuse: Original Domain - gcc.gnu.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - nextmovesoftware.com X-Get-Message-Sender-Via: server.nextmovesoftware.com: authenticated_id: roger@nextmovesoftware.com X-Authenticated-Sender: server.nextmovesoftware.com: roger@nextmovesoftware.com X-Source: X-Source-Args: X-Source-Dir: X-Spam-Status: No, score=-12.5 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,KAM_SHORT,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: This is a multipart message in MIME format. ------=_NextPart_000_005D_01D9A05E.A0C6BF90 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Hi Uros, Here's an updated version of this patch incorporating your comments. It uses emit_insn (target, const1_rtx), bt_comparison operator to combine the sete/setne to setc/setnc, and je/jne to jc/jnc patterns, uses scan-assembler-times in the test cases, and cleans up the silly cut'n'paste issue that mangled strict_low_part/subreg of a register that was already QImode. I tried, but the strict_low_part variant really is required (some of the new test cases fail without it), but things are much neater now, and have few patterns than the original. This patch has been tested on x86_64-pc-linux-gnu with make bootstrap and make -k check, both with and without --target_board=3Dunix{-m32} with no new failures. Ok for mainline? 2023-06-16 Roger Sayle Uros Bizjak gcc/ChangeLog * config/i386/i386-expand.cc (ix86_expand_sse_ptest): Recognize expansion of ptestc with equal operands as producing const1_rtx. * config/i386/i386.cc (ix86_rtx_costs): Provide accurate cost estimates of UNSPEC_PTEST, where the ptest performs the PAND or PAND of its operands. * config/i386/sse.md (define_split): Transform CCCmode = UNSPEC_PTEST of reg_equal_p operands into an x86_stc instruction. (define_split): Split pandn/ptestz/set{n?}e into = ptestc/set{n?}c. (define_split): Similar to above for strict_low_part = destinations. (define_split): Split pandn/ptestz/j{n?}e into ptestc/j{n?}c. gcc/testsuite/ChangeLog * gcc.target/i386/avx-vptest-4.c: New test case. * gcc.target/i386/avx-vptest-5.c: Likewise. * gcc.target/i386/avx-vptest-6.c: Likewise. * gcc.target/i386/pr109973-1.c: Update test case. * gcc.target/i386/pr109973-2.c: Likewise. * gcc.target/i386/sse4_1-ptest-4.c: New test case. * gcc.target/i386/sse4_1-ptest-5.c: Likewise. * gcc.target/i386/sse4_1-ptest-6.c: Likewise. Thanks, Roger -- > -----Original Message----- > From: Uros Bizjak > Sent: 14 June 2023 09:31 > To: Roger Sayle > Cc: gcc-patches@gcc.gnu.org > Subject: Re: [x86 PATCH] Convert ptestz of pandn into ptestc. >=20 > On Tue, Jun 13, 2023 at 6:03=E2=80=AFPM Roger Sayle = > wrote: > > > > > > This patch is the next instalment in a set of backend patches around > > improvements to ptest/vptest. A previous patch optimized the = sequence > > t=3Dpand(x,y); ptestz(t,t) into the equivalent ptestz(x,y), using = the > > property that ZF is set to (X&Y) =3D=3D 0. This patch performs a = similar > > transformation, converting t=3Dpandn(x,y); ptestz(t,t) into the = (almost) > > equivalent ptestc(y,x), using the property that the CF flags is set = to > > (~X&Y) =3D=3D 0. The tricky bit is that this sets the CF flag = instead of > > the ZF flag, so we can only perform this transformation when we can > > also convert the flags' consumer, as well as the producer. > > > > For the test case: > > > > int foo (__m128i x, __m128i y) > > { > > __m128i a =3D x & ~y; > > return __builtin_ia32_ptestz128 (a, a); } > > > > With -O2 -msse4.1 we previously generated: > > > > foo: pandn %xmm0, %xmm1 > > xorl %eax, %eax > > ptest %xmm1, %xmm1 > > sete %al > > ret > > > > with this patch we now generate: > > > > foo: xorl %eax, %eax > > ptest %xmm0, %xmm1 > > setc %al > > ret > > > > At the same time, this patch also provides alternative fixes for PR > > target/109973 and PR target/110118, by recognizing that ptestc(x,x) > > always sets the carry flag (X&~X is always zero). This is achieved > > both by recognizing the special case in ix86_expand_sse_ptest and = with > > a splitter to convert an eligible ptest into an stc. > > > > The next piece is, of course, STV of "if (x & ~y)..." > > > > This patch has been tested on x86_64-pc-linux-gnu with make = bootstrap > > and make -k check, both with and without --target_board=3Dunix{-m32} > > with no new failures. Ok for mainline? > > > > 2023-06-13 Roger Sayle > > > > gcc/ChangeLog > > * config/i386/i386-expand.cc (ix86_expand_sse_ptest): = Recognize > > expansion of ptestc with equal operands as returning = const1_rtx. > > * config/i386/i386.cc (ix86_rtx_costs): Provide accurate = cost > > estimates of UNSPEC_PTEST, where the ptest performs the PAND > > or PAND of its operands. > > * config/i386/sse.md (define_split): Transform CCCmode = UNSPEC_PTEST > > of reg_equal_p operands into an x86_stc instruction. > > (define_split): Split pandn/ptestz/setne into ptestc/setnc. > > (define_split): Split pandn/ptestz/sete into ptestc/setc. > > (define_split): Split pandn/ptestz/je into ptestc/jc. > > (define_split): Split pandn/ptestz/jne into ptestc/jnc. > > > > gcc/testsuite/ChangeLog > > * gcc.target/i386/avx-vptest-4.c: New test case. > > * gcc.target/i386/avx-vptest-5.c: Likewise. > > * gcc.target/i386/avx-vptest-6.c: Likewise. > > * gcc.target/i386/pr109973-1.c: Update test case. > > * gcc.target/i386/pr109973-2.c: Likewise. > > * gcc.target/i386/sse4_1-ptest-4.c: New test case. > > * gcc.target/i386/sse4_1-ptest-5.c: Likewise. > > * gcc.target/i386/sse4_1-ptest-6.c: Likewise. > > > > > > Thanks in advance, > > Roger >=20 > + /* ptest reg, reg sets the carry flag. */ if (comparison =3D=3D = LTU > + && (d->code =3D=3D IX86_BUILTIN_PTESTC > + || d->code =3D=3D IX86_BUILTIN_PTESTC256) > + && rtx_equal_p (op0, op1)) > + return const1_rtx; >=20 > In this function, a RTX that sets a target reg should be emitted, and = a target > register returned. I don't think the above code is correct. >=20 > +;; pandn/ptestz/setne -> ptestc/setnc > +(define_split > + [(set (match_operand:QI 0 "register_operand") > + (ne:QI >=20 > Please note that setcc is a bit tricky on x86. You can actually set a = register in > QI/HI/SI/DImode, and post-reload splitters will do the correct = extension (see the > patterns in i386.md, after "For all sCOND expanders ..." comment). But = you have > to account for all these modes in the pre-reload splitter. Maybe you = should use > the "int248_register_operand" predicate to avoid pattern explosion. >=20 > + (unspec:CCZ [ > + (and:V_AVX (not:V_AVX (match_operand:V_AVX 1 = "register_operand")) > + (match_operand:V_AVX 2 "register_operand")) > + (and:V_AVX (not:V_AVX (match_dup 1)) (match_dup 2))] > + UNSPEC_PTEST) > + (const_int 0)))] > + "TARGET_SSE4_1" > + [(set (reg:CCC FLAGS_REG) > + (unspec:CCC [(match_dup 1) (match_dup 2)] UNSPEC_PTEST)) > + (set (strict_low_part (subreg:QI (match_dup 0) 0)) > + (geu:QI (reg:CCC FLAGS_REG) (const_int 0)))]) >=20 > No need to set strict_low_part, just set a register with EQ/NE of = CCCmode and > post-reload splitters will do their magic. Please also note that you = emit a QI > subreg of a QI register here, which doesn't seem right. >=20 > + > +;; Changing the CCmode of FLAGS_REG requires updating both def and = use. >=20 > Does the above comment also apply to the above pattern? >=20 > +;; pandn/ptestz/sete -> ptestc/setc > +(define_split > + [(set (strict_low_part (subreg:QI (match_operand:SI 0 = "register_operand") 0)) > + (eq:QI > + (unspec:CCZ [ > + (and:V_AVX (not:V_AVX (match_operand:V_AVX 1 = "register_operand")) > + (match_operand:V_AVX 2 "register_operand")) > + (and:V_AVX (not:V_AVX (match_dup 1)) (match_dup 2))] > + UNSPEC_PTEST) > + (const_int 0)))] > + "TARGET_SSE4_1" > + [(set (reg:CCC FLAGS_REG) > + (unspec:CCC [(match_dup 1) (match_dup 2)] UNSPEC_PTEST)) > + (set (strict_low_part (subreg:QI (match_dup 0) 0)) > + (ltu:QI (reg:CCC FLAGS_REG) (const_int 0)))]) >=20 > These two patterns can be merged into one using the (somehow = unfortunately > named) "bt_comparison_operator" (a new name is much > welcome...) operator predicate. The setc/setnc can easily be emitted = using > eq/ne:QI (reg:CCC FLAGS_REG) (const_int 0). >=20 > +;; pandn/ptestz/je -> ptestc/jc > +(define_split > + [(set (pc) > + (if_then_else > + (ne > + (unspec:CCZ [ > + (and:V_AVX > + (not:V_AVX (match_operand:V_AVX 1 "register_operand")) > + (match_operand:V_AVX 2 "register_operand")) > + (and:V_AVX (not:V_AVX (match_dup 1)) (match_dup 2))] > + UNSPEC_PTEST) > + (const_int 0)) > + (match_operand 0) > + (pc)))] > + "TARGET_SSE4_1" > + [(set (reg:CCC FLAGS_REG) > + (unspec:CCC [(match_dup 1) (match_dup 2)] UNSPEC_PTEST)) > + (set (pc) (if_then_else (geu (reg:CCC FLAGS_REG) (const_int 0)) > + (match_dup 0) > + (pc)))]) > + > +;; pandn/ptestz/jne -> ptestc/jnc > +(define_split > + [(set (pc) > + (if_then_else > + (eq > + (unspec:CCZ [ > + (and:V_AVX > + (not:V_AVX (match_operand:V_AVX 1 "register_operand")) > + (match_operand:V_AVX 2 "register_operand")) > + (and:V_AVX (not:V_AVX (match_dup 1)) (match_dup 2))] > + UNSPEC_PTEST) > + (const_int 0)) > + (match_operand 0) > + (pc)))] > + "TARGET_SSE4_1" > + [(set (reg:CCC FLAGS_REG) > + (unspec:CCC [(match_dup 1) (match_dup 2)] UNSPEC_PTEST)) > + (set (pc) (if_then_else (ltu (reg:CCC FLAGS_REG) (const_int 0)) > + (match_dup 0) > + (pc)))]) >=20 > Also the above two can be merged using "bt_comparison_operator" > operator predicate. >=20 > +/* { dg-final { scan-assembler "ptest" } } */ > +/* { dg-final { scan-assembler "jn?c" } } */ > +/* { dg-final { scan-assembler-not "pandn" } } */ > +/* { dg-final { scan-assembler-not "jne" } } */ > +/* { dg-final { scan-assembler-not "je" } } */ >=20 > Please better use scan-assembler-times when checking asm of several = functions. > Otherwise, there could only be only one ptest (out of four) generated, = and the test > will still pass. >=20 > +/* { dg-final { scan-assembler "ptest" } } */ > +/* { dg-final { scan-assembler "setnc" } } */ > +/* { dg-final { scan-assembler-not "pandn" } } */ > +/* { dg-final { scan-assembler-not "setne" } } */ >=20 > Also use scan-assembler-times when two functions are checked, same = reason as > above. >=20 > Uros. ------=_NextPart_000_005D_01D9A05E.A0C6BF90 Content-Type: text/plain; name="patchpt2.txt" Content-Transfer-Encoding: quoted-printable Content-Disposition: attachment; filename="patchpt2.txt" diff --git a/gcc/config/i386/i386-expand.cc = b/gcc/config/i386/i386-expand.cc=0A= index def060a..e844467 100644=0A= --- a/gcc/config/i386/i386-expand.cc=0A= +++ b/gcc/config/i386/i386-expand.cc=0A= @@ -10222,6 +10222,18 @@ ix86_expand_sse_ptest (const struct = builtin_description *d, tree exp,=0A= machine_mode mode1 =3D insn_data[d->icode].operand[1].mode;=0A= enum rtx_code comparison =3D d->comparison;=0A= =0A= + /* ptest reg, reg sets the carry flag. */=0A= + if (comparison =3D=3D LTU=0A= + && (d->code =3D=3D IX86_BUILTIN_PTESTC=0A= + || d->code =3D=3D IX86_BUILTIN_PTESTC256)=0A= + && rtx_equal_p (op0, op1))=0A= + {=0A= + if (!target)=0A= + target =3D gen_reg_rtx (SImode);=0A= + emit_move_insn (target, const1_rtx);=0A= + return target;=0A= + }=0A= +=0A= if (VECTOR_MODE_P (mode0))=0A= op0 =3D safe_vector_operand (op0, mode0);=0A= if (VECTOR_MODE_P (mode1))=0A= diff --git a/gcc/config/i386/i386.cc b/gcc/config/i386/i386.cc=0A= index 3a1444d..3e99e23 100644=0A= --- a/gcc/config/i386/i386.cc=0A= +++ b/gcc/config/i386/i386.cc=0A= @@ -21423,16 +21423,23 @@ ix86_rtx_costs (rtx x, machine_mode mode, int = outer_code_i, int opno,=0A= else if (XINT (x, 1) =3D=3D UNSPEC_PTEST)=0A= {=0A= *total =3D cost->sse_op;=0A= - if (XVECLEN (x, 0) =3D=3D 2=0A= - && GET_CODE (XVECEXP (x, 0, 0)) =3D=3D AND)=0A= + rtx test_op0 =3D XVECEXP (x, 0, 0);=0A= + if (!rtx_equal_p (test_op0, XVECEXP (x, 0, 1)))=0A= + return false;=0A= + if (GET_CODE (test_op0) =3D=3D AND)=0A= {=0A= - rtx andop =3D XVECEXP (x, 0, 0);=0A= - *total +=3D rtx_cost (XEXP (andop, 0), GET_MODE (andop),=0A= - AND, opno, speed)=0A= - + rtx_cost (XEXP (andop, 1), GET_MODE (andop),=0A= - AND, opno, speed);=0A= - return true;=0A= + rtx and_op0 =3D XEXP (test_op0, 0);=0A= + if (GET_CODE (and_op0) =3D=3D NOT)=0A= + and_op0 =3D XEXP (and_op0, 0);=0A= + *total +=3D rtx_cost (and_op0, GET_MODE (and_op0),=0A= + AND, 0, speed)=0A= + + rtx_cost (XEXP (test_op0, 1), GET_MODE (and_op0),=0A= + AND, 1, speed);=0A= }=0A= + else=0A= + *total =3D rtx_cost (test_op0, GET_MODE (test_op0),=0A= + UNSPEC, 0, speed);=0A= + return true;=0A= }=0A= return false;=0A= =0A= diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md=0A= index 9bec09d..ce90ae4 100644=0A= --- a/gcc/config/i386/sse.md=0A= +++ b/gcc/config/i386/sse.md=0A= @@ -23147,6 +23147,70 @@=0A= [(set (reg:CCZ FLAGS_REG)=0A= (unspec:CCZ [(match_dup 0) (match_dup 1)] UNSPEC_PTEST))])=0A= =0A= +;; ptest reg,reg sets the carry flag.=0A= +(define_split=0A= + [(set (reg:CCC FLAGS_REG)=0A= + (unspec:CCC [(match_operand:V_AVX 0 "register_operand")=0A= + (match_operand:V_AVX 1 "register_operand")]=0A= + UNSPEC_PTEST))]=0A= + "TARGET_SSE4_1=0A= + && rtx_equal_p (operands[0], operands[1])"=0A= + [(set (reg:CCC FLAGS_REG)=0A= + (unspec:CCC [(const_int 0)] UNSPEC_STC))])=0A= +=0A= +;; Changing the CCmode of FLAGS_REG requires updating both def and use.=0A= +;; pandn/ptestz/set{n?}e -> ptestc/set{n?}c=0A= +(define_split=0A= + [(set (match_operand:SWI 0 "register_operand")=0A= + (match_operator:SWI 3 "bt_comparison_operator"=0A= + [(unspec:CCZ [=0A= + (and:V_AVX (not:V_AVX (match_operand:V_AVX 1 "register_operand"))=0A= + (match_operand:V_AVX 2 "register_operand"))=0A= + (and:V_AVX (not:V_AVX (match_dup 1)) (match_dup 2))]=0A= + UNSPEC_PTEST)=0A= + (const_int 0)]))]=0A= + "TARGET_SSE4_1"=0A= + [(set (reg:CCC FLAGS_REG)=0A= + (unspec:CCC [(match_dup 1) (match_dup 2)] UNSPEC_PTEST))=0A= + (set (match_dup 0)=0A= + (match_op_dup 3 [(reg:CCC FLAGS_REG) (const_int 0)]))])=0A= +=0A= +(define_split=0A= + [(set (strict_low_part (subreg:QI (match_operand:SI 0 = "register_operand") 0))=0A= + (match_operator:QI 3 "bt_comparison_operator"=0A= + [(unspec:CCZ [=0A= + (and:V_AVX (not:V_AVX (match_operand:V_AVX 1 "register_operand"))=0A= + (match_operand:V_AVX 2 "register_operand"))=0A= + (and:V_AVX (not:V_AVX (match_dup 1)) (match_dup 2))]=0A= + UNSPEC_PTEST)=0A= + (const_int 0)]))]=0A= + "TARGET_SSE4_1"=0A= + [(set (reg:CCC FLAGS_REG)=0A= + (unspec:CCC [(match_dup 1) (match_dup 2)] UNSPEC_PTEST))=0A= + (set (strict_low_part (subreg:QI (match_dup 0) 0))=0A= + (match_op_dup 3 [(reg:CCC FLAGS_REG) (const_int 0)]))])=0A= +=0A= +;; pandn/ptestz/j{n?}e -> ptestc/j{n?}c=0A= +(define_split=0A= + [(set (pc)=0A= + (if_then_else=0A= + (match_operator 3 "bt_comparison_operator"=0A= + [(unspec:CCZ [=0A= + (and:V_AVX=0A= + (not:V_AVX (match_operand:V_AVX 1 "register_operand"))=0A= + (match_operand:V_AVX 2 "register_operand"))=0A= + (and:V_AVX (not:V_AVX (match_dup 1)) (match_dup 2))]=0A= + UNSPEC_PTEST)=0A= + (const_int 0)])=0A= + (match_operand 0)=0A= + (pc)))]=0A= + "TARGET_SSE4_1"=0A= + [(set (reg:CCC FLAGS_REG)=0A= + (unspec:CCC [(match_dup 1) (match_dup 2)] UNSPEC_PTEST))=0A= + (set (pc) (if_then_else (match_op_dup 3 [(reg:CCC FLAGS_REG) = (const_int 0)])=0A= + (match_dup 0)=0A= + (pc)))])=0A= +=0A= (define_expand "nearbyint2"=0A= [(set (match_operand:VFH 0 "register_operand")=0A= (unspec:VFH=0A= diff --git a/gcc/testsuite/gcc.target/i386/avx-vptest-4.c = b/gcc/testsuite/gcc.target/i386/avx-vptest-4.c=0A= new file mode 100644=0A= index 0000000..0a234e1=0A= --- /dev/null=0A= +++ b/gcc/testsuite/gcc.target/i386/avx-vptest-4.c=0A= @@ -0,0 +1,21 @@=0A= +/* { dg-do compile } */=0A= +/* { dg-options "-O2 -mavx" } */=0A= +=0A= +typedef long long __m256i __attribute__ ((__vector_size__ (32)));=0A= +=0A= +int foo (__m256i x, __m256i y)=0A= +{=0A= + __m256i a =3D x & ~y;=0A= + return __builtin_ia32_ptestz256 (a, a);=0A= +}=0A= +=0A= +int bar (__m256i x, __m256i y)=0A= +{=0A= + __m256i a =3D ~x & y;=0A= + return __builtin_ia32_ptestz256 (a, a);=0A= +}=0A= +=0A= +/* { dg-final { scan-assembler-times "vptest\[ \\t\]+%" 2 } } */=0A= +/* { dg-final { scan-assembler-times "setc" 2 } } */=0A= +/* { dg-final { scan-assembler-not "vpandn" } } */=0A= +/* { dg-final { scan-assembler-not "sete" } } */=0A= diff --git a/gcc/testsuite/gcc.target/i386/avx-vptest-5.c = b/gcc/testsuite/gcc.target/i386/avx-vptest-5.c=0A= new file mode 100644=0A= index 0000000..fd0e5e2=0A= --- /dev/null=0A= +++ b/gcc/testsuite/gcc.target/i386/avx-vptest-5.c=0A= @@ -0,0 +1,21 @@=0A= +/* { dg-do compile } */=0A= +/* { dg-options "-O2 -mavx" } */=0A= +=0A= +typedef long long __m256i __attribute__ ((__vector_size__ (32)));=0A= +=0A= +int foo (__m256i x, __m256i y)=0A= +{=0A= + __m256i a =3D x & ~y;=0A= + return !__builtin_ia32_ptestz256 (a, a);=0A= +}=0A= +=0A= +int bar (__m256i x, __m256i y)=0A= +{=0A= + __m256i a =3D ~x & y;=0A= + return !__builtin_ia32_ptestz256 (a, a);=0A= +}=0A= +=0A= +/* { dg-final { scan-assembler-times "vptest\[ \\t\]+%" 2} } */=0A= +/* { dg-final { scan-assembler-times "setnc" 2 } } */=0A= +/* { dg-final { scan-assembler-not "vpandn" } } */=0A= +/* { dg-final { scan-assembler-not "setne" } } */=0A= diff --git a/gcc/testsuite/gcc.target/i386/avx-vptest-6.c = b/gcc/testsuite/gcc.target/i386/avx-vptest-6.c=0A= new file mode 100644=0A= index 0000000..5821a92=0A= --- /dev/null=0A= +++ b/gcc/testsuite/gcc.target/i386/avx-vptest-6.c=0A= @@ -0,0 +1,40 @@=0A= +/* { dg-do compile } */=0A= +/* { dg-options "-O2 -mavx" } */=0A= +=0A= +typedef long long __m256i __attribute__ ((__vector_size__ (32)));=0A= +=0A= +extern void ext (void);=0A= +=0A= +void foo (__m256i x, __m256i y)=0A= +{=0A= + __m256i a =3D x & ~y;=0A= + if (__builtin_ia32_ptestz256 (a, a))=0A= + ext();=0A= +}=0A= +=0A= +void bar (__m256i x, __m256i y)=0A= +{=0A= + __m256i a =3D ~x & y;=0A= + if (__builtin_ia32_ptestz256 (a, a))=0A= + ext();=0A= +}=0A= +=0A= +void foo2 (__m256i x, __m256i y)=0A= +{=0A= + __m256i a =3D x & ~y;=0A= + if (__builtin_ia32_ptestz256 (a, a))=0A= + ext();=0A= +}=0A= +=0A= +void bar2 (__m256i x, __m256i y)=0A= +{=0A= + __m256i a =3D ~x & y;=0A= + if (__builtin_ia32_ptestz256 (a, a))=0A= + ext();=0A= +}=0A= +=0A= +/* { dg-final { scan-assembler-times "ptest\[ \\t\]+%" 4 } } */=0A= +/* { dg-final { scan-assembler-times "jn?c" 4 } } */=0A= +/* { dg-final { scan-assembler-not "pandn" } } */=0A= +/* { dg-final { scan-assembler-not "jne" } } */=0A= +/* { dg-final { scan-assembler-not "je" } } */=0A= diff --git a/gcc/testsuite/gcc.target/i386/pr109973-1.c = b/gcc/testsuite/gcc.target/i386/pr109973-1.c=0A= index a1b6136b..1d812dd 100644=0A= --- a/gcc/testsuite/gcc.target/i386/pr109973-1.c=0A= +++ b/gcc/testsuite/gcc.target/i386/pr109973-1.c=0A= @@ -10,4 +10,4 @@ foo (__m256i x, __m256i y)=0A= return __builtin_ia32_ptestc256 (a, a);=0A= }=0A= =0A= -/* { dg-final { scan-assembler "vpand" } } */=0A= +/* { dg-final { scan-assembler "movl\[ \\t]*\\\$1, %eax" } } */=0A= diff --git a/gcc/testsuite/gcc.target/i386/pr109973-2.c = b/gcc/testsuite/gcc.target/i386/pr109973-2.c=0A= index 167f6ee..1068c3e 100644=0A= --- a/gcc/testsuite/gcc.target/i386/pr109973-2.c=0A= +++ b/gcc/testsuite/gcc.target/i386/pr109973-2.c=0A= @@ -10,4 +10,4 @@ foo (__m128i x, __m128i y)=0A= return __builtin_ia32_ptestc128 (a, a);=0A= }=0A= =0A= -/* { dg-final { scan-assembler "pand" } } */=0A= +/* { dg-final { scan-assembler "movl\[ \\t]*\\\$1, %eax" } } */=0A= diff --git a/gcc/testsuite/gcc.target/i386/sse4_1-ptest-4.c = b/gcc/testsuite/gcc.target/i386/sse4_1-ptest-4.c=0A= new file mode 100644=0A= index 0000000..e74ddb3=0A= --- /dev/null=0A= +++ b/gcc/testsuite/gcc.target/i386/sse4_1-ptest-4.c=0A= @@ -0,0 +1,22 @@=0A= +/* { dg-do compile } */=0A= +/* { dg-options "-O2 -msse4.1" } */=0A= +=0A= +typedef long long __m128i __attribute__ ((__vector_size__ (16)));=0A= +=0A= +int foo (__m128i x, __m128i y)=0A= +{=0A= + __m128i a =3D x & ~y;=0A= + return __builtin_ia32_ptestz128 (a, a);=0A= +}=0A= +=0A= +int bar (__m128i x, __m128i y)=0A= +{=0A= + __m128i a =3D ~x & y;=0A= + return __builtin_ia32_ptestz128 (a, a);=0A= +}=0A= +=0A= +/* { dg-final { scan-assembler-times "ptest\[ \\t\]+%" 2 } } */=0A= +/* { dg-final { scan-assembler-times "setc" 2 } } */=0A= +/* { dg-final { scan-assembler-not "pandn" } } */=0A= +/* { dg-final { scan-assembler-not "sete" } } */=0A= +=0A= diff --git a/gcc/testsuite/gcc.target/i386/sse4_1-ptest-5.c = b/gcc/testsuite/gcc.target/i386/sse4_1-ptest-5.c=0A= new file mode 100644=0A= index 0000000..74b0a8c=0A= --- /dev/null=0A= +++ b/gcc/testsuite/gcc.target/i386/sse4_1-ptest-5.c=0A= @@ -0,0 +1,22 @@=0A= +/* { dg-do compile } */=0A= +/* { dg-options "-O2 -msse4.1" } */=0A= +=0A= +typedef long long __m128i __attribute__ ((__vector_size__ (16)));=0A= +=0A= +int foo (__m128i x, __m128i y)=0A= +{=0A= + __m128i a =3D x & ~y;=0A= + return !__builtin_ia32_ptestz128 (a, a);=0A= +}=0A= +=0A= +int bar (__m128i x, __m128i y)=0A= +{=0A= + __m128i a =3D ~x & y;=0A= + return !__builtin_ia32_ptestz128 (a, a);=0A= +}=0A= +=0A= +/* { dg-final { scan-assembler-times "ptest\[ \\t\]+%" 2 } } */=0A= +/* { dg-final { scan-assembler-times "setnc" 2 } } */=0A= +/* { dg-final { scan-assembler-not "pandn" } } */=0A= +/* { dg-final { scan-assembler-not "setne" } } */=0A= +=0A= diff --git a/gcc/testsuite/gcc.target/i386/sse4_1-ptest-6.c = b/gcc/testsuite/gcc.target/i386/sse4_1-ptest-6.c=0A= new file mode 100644=0A= index 0000000..d9114bb=0A= --- /dev/null=0A= +++ b/gcc/testsuite/gcc.target/i386/sse4_1-ptest-6.c=0A= @@ -0,0 +1,40 @@=0A= +/* { dg-do compile } */=0A= +/* { dg-options "-O2 -msse4.1" } */=0A= +=0A= +typedef long long __m128i __attribute__ ((__vector_size__ (16)));=0A= +=0A= +extern void ext (void);=0A= +=0A= +void foo (__m128i x, __m128i y)=0A= +{=0A= + __m128i a =3D x & ~y;=0A= + if (__builtin_ia32_ptestz128 (a, a))=0A= + ext();=0A= +}=0A= +=0A= +void bar (__m128i x, __m128i y)=0A= +{=0A= + __m128i a =3D ~x & y;=0A= + if (__builtin_ia32_ptestz128 (a, a))=0A= + ext();=0A= +}=0A= +=0A= +void foo2 (__m128i x, __m128i y)=0A= +{=0A= + __m128i a =3D x & ~y;=0A= + if (__builtin_ia32_ptestz128 (a, a))=0A= + ext();=0A= +}=0A= +=0A= +void bar2 (__m128i x, __m128i y)=0A= +{=0A= + __m128i a =3D ~x & y;=0A= + if (__builtin_ia32_ptestz128 (a, a))=0A= + ext();=0A= +}=0A= +=0A= +/* { dg-final { scan-assembler-times "ptest\[ \\t\]+%" 4 } } */=0A= +/* { dg-final { scan-assembler-times "jn?c" 4 } } */=0A= +/* { dg-final { scan-assembler-not "pandn" } } */=0A= +/* { dg-final { scan-assembler-not "jne" } } */=0A= +/* { dg-final { scan-assembler-not "je" } } */=0A= ------=_NextPart_000_005D_01D9A05E.A0C6BF90--