From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from server.nextmovesoftware.com (server.nextmovesoftware.com [162.254.253.69]) by sourceware.org (Postfix) with ESMTPS id 1E6E33858C60 for ; Thu, 15 Jun 2023 22:04:44 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 1E6E33858C60 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=nextmovesoftware.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=nextmovesoftware.com DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=nextmovesoftware.com; s=default; h=Content-Type:MIME-Version:Message-ID: Date:Subject:In-Reply-To:References:Cc:To:From:Sender:Reply-To: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Id: List-Help:List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=Gy41c3tcJr+QmrKYlHgCZfubjUJDdFAIz47/fgDnC+o=; b=Wxabcl7cPL2DXl3uUGRzCI7eiF rzw/d7HXK/yBG9H6ZSDFt5/pvtGkcFeItCPV9e51SaHXwkQ1ZrbdsZHgJq4B0OKlJiBoJaUqQvzYF ZWNLVm4MLK2gLWwHMoCrMKovfBsVBIR74J5PUDrHkY4ktMgclsDNgsSeeUHhQBxyC1we4f0SlUZ0N 8aQ3pGpeUlV8XVOECfSvZMOEb9fmJAiV54wBq89vz1WO5l7dKa5N/bZubj8xFZW/AdoQ9AJjy8IVF pj9U60LmfmUccF0AX6W6UpAD7aTgKMbLbYh4Z8L9Mn9j+u9cFPpg6F0vbsQWpBI2086LEk7ztuhAE jCJ44jgw==; Received: from host86-169-41-81.range86-169.btcentralplus.com ([86.169.41.81]:50525 helo=Dell) by server.nextmovesoftware.com with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.96) (envelope-from ) id 1q9v59-0005Pe-09; Thu, 15 Jun 2023 18:04:43 -0400 From: "Roger Sayle" To: "'Uros Bizjak'" Cc: References: <037101d998cb$6aa8f120$3ffad360$@nextmovesoftware.com> In-Reply-To: Subject: RE: [x86 PATCH] PR target/31985: Improve memory operand use with doubleword add. Date: Thu, 15 Jun 2023 23:04:41 +0100 Message-ID: <006701d99fd5$63e988c0$2bbc9a40$@nextmovesoftware.com> MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="----=_NextPart_000_0068_01D99FDD.C5B03AB0" X-Mailer: Microsoft Outlook 16.0 Content-Language: en-gb Thread-Index: AQFB5tHMbHq6EELnAY41pC+GoDCuTQIHjaRiAlp3oKWwmMqPIA== X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - server.nextmovesoftware.com X-AntiAbuse: Original Domain - gcc.gnu.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - nextmovesoftware.com X-Get-Message-Sender-Via: server.nextmovesoftware.com: authenticated_id: roger@nextmovesoftware.com X-Authenticated-Sender: server.nextmovesoftware.com: roger@nextmovesoftware.com X-Source: X-Source-Args: X-Source-Dir: X-Spam-Status: No, score=-10.8 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,KAM_SHORT,RCVD_IN_BARRACUDACENTRAL,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: This is a multipart message in MIME format. ------=_NextPart_000_0068_01D99FDD.C5B03AB0 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Hi Uros, > On the 7th June 2023, Uros Bizkak wrote: > The register allocator considers the instruction-to-be-split as one = instruction, so it > can allocate output register to match an input register (or a register = that forms an > input address), So, you have to either add an early clobber to the = output, or > somehow prevent output to clobber registers in the second pattern. This implements your suggestion of adding an early clobber to the = output, a one character ('&') change from the previous version of this patch. = Retested with make bootstrap and make -k check, with and without -m32, to confirm there are no issues, and this still fixes the pr31985.c test case. As you've suggested, I'm also working on improving STV in this area. Ok for mainline? 2023-06-15 Roger Sayle Uros Bizjak gcc/ChangeLog PR target/31985 * config/i386/i386.md (*add3_doubleword_concat): New define_insn_and_split combine *add3_doubleword with a *concat3 for more efficient lowering after reload. gcc/testsuite/ChangeLog PR target/31985 * gcc.target/i386/pr31985.c: New test case. Roger -- ------=_NextPart_000_0068_01D99FDD.C5B03AB0 Content-Type: text/plain; name="patchad2.txt" Content-Transfer-Encoding: quoted-printable Content-Disposition: attachment; filename="patchad2.txt" diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md=0A= index e6ebc46..42c302d 100644=0A= --- a/gcc/config/i386/i386.md=0A= +++ b/gcc/config/i386/i386.md=0A= @@ -6124,6 +6124,36 @@=0A= (clobber (reg:CC FLAGS_REG))])]=0A= "split_double_mode (mode, &operands[0], 2, &operands[0], = &operands[3]);")=0A= =0A= +(define_insn_and_split "*add3_doubleword_concat"=0A= + [(set (match_operand: 0 "register_operand" "=3D&r")=0A= + (plus:=0A= + (any_or_plus:=0A= + (ashift:=0A= + (zero_extend:=0A= + (match_operand:DWIH 2 "nonimmediate_operand" "rm"))=0A= + (match_operand: 3 "const_int_operand"))=0A= + (zero_extend:=0A= + (match_operand:DWIH 4 "nonimmediate_operand" "rm")))=0A= + (match_operand: 1 "register_operand" "0")))=0A= + (clobber (reg:CC FLAGS_REG))]=0A= + "INTVAL (operands[3]) =3D=3D * BITS_PER_UNIT"=0A= + "#"=0A= + "&& reload_completed"=0A= + [(parallel [(set (reg:CCC FLAGS_REG)=0A= + (compare:CCC=0A= + (plus:DWIH (match_dup 1) (match_dup 4))=0A= + (match_dup 1)))=0A= + (set (match_dup 0)=0A= + (plus:DWIH (match_dup 1) (match_dup 4)))])=0A= + (parallel [(set (match_dup 5)=0A= + (plus:DWIH=0A= + (plus:DWIH=0A= + (ltu:DWIH (reg:CC FLAGS_REG) (const_int 0))=0A= + (match_dup 6))=0A= + (match_dup 2)))=0A= + (clobber (reg:CC FLAGS_REG))])]=0A= + "split_double_mode (mode, &operands[0], 2, &operands[0], = &operands[5]);")=0A= +=0A= (define_insn "*add_1"=0A= [(set (match_operand:SWI48 0 "nonimmediate_operand" "=3Drm,r,r,r")=0A= (plus:SWI48=0A= diff --git a/gcc/testsuite/gcc.target/i386/pr31985.c = b/gcc/testsuite/gcc.target/i386/pr31985.c=0A= new file mode 100644=0A= index 0000000..a6de1b5=0A= --- /dev/null=0A= +++ b/gcc/testsuite/gcc.target/i386/pr31985.c=0A= @@ -0,0 +1,14 @@=0A= +/* { dg-do compile { target ia32 } } */=0A= +/* { dg-options "-O2" } */=0A= +=0A= +void test_c (unsigned int a, unsigned int b, unsigned int c, unsigned = int d)=0A= +{=0A= + volatile unsigned int x, y;=0A= + unsigned long long __a =3D b | ((unsigned long long)a << 32);=0A= + unsigned long long __b =3D d | ((unsigned long long)c << 32);=0A= + unsigned long long __c =3D __a + __b;=0A= + x =3D (unsigned int)(__c & 0xffffffff);=0A= + y =3D (unsigned int)(__c >> 32);=0A= +}=0A= +=0A= +/* { dg-final { scan-assembler-times "movl" 4 } } */=0A= ------=_NextPart_000_0068_01D99FDD.C5B03AB0--