* [PATCH, ARM 7/6] Enable atomics for ARMv8-M Mainline
@ 2015-12-17 9:39 Thomas Preud'homme
2016-05-17 10:15 ` [PATCH, ARM 7/7, ping1] " Thomas Preudhomme
0 siblings, 1 reply; 8+ messages in thread
From: Thomas Preud'homme @ 2015-12-17 9:39 UTC (permalink / raw)
To: gcc-patches, Richard Earnshaw, Ramana Radhakrishnan, Kyrylo Tkachov
Hi,
This patch is part of a patch series to add support for ARMv8-M[1] to GCC. This specific patch enable atomics for ARMv8-M Mainline. No change is needed to existing patterns since Thumb-2 backend can already handle them fine.
[1] For a quick overview of ARMv8-M please refer to the initial cover letter.
ChangeLog entries are as follow:
*** gcc/ChangeLog ***
2015-12-17 Thomas Preud'homme <thomas.preudhomme@arm.com>
* config/arm/arm.h (TARGET_HAVE_LDACQ): Enable for ARMv8-M Mainline.
diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
index 1f79c37b5c36a410a2d500ba92c62a5ba4ca1178..fa2a6fb03ffd2ca53bfb7e7c8f03022b626880e0 100644
--- a/gcc/config/arm/arm.h
+++ b/gcc/config/arm/arm.h
@@ -258,7 +258,7 @@ extern void (*arm_lang_output_object_attributes_hook)(void);
|| arm_arch7) && arm_arch_notm)
/* Nonzero if this chip supports load-acquire and store-release. */
-#define TARGET_HAVE_LDACQ (TARGET_ARM_ARCH >= 8 && arm_arch_notm)
+#define TARGET_HAVE_LDACQ (TARGET_ARM_ARCH >= 8 && TARGET_32BIT)
/* Nonzero if this chip provides the movw and movt instructions. */
#define TARGET_HAVE_MOVT (arm_arch_thumb2 || arm_arch8)
Testing:
* Toolchain was built successfully with and without the ARMv8-M support patches with the following multilib list: armv6-m,armv7-m,armv7e-m,cortex-m7. The code generation for crtbegin.o, crtend.o, crti.o, crtn.o, libgcc.a, libgcov.a, libc.a, libg.a, libgloss-linux.a, libm.a, libnosys.a, librdimon.a, librdpmon.a, libstdc++.a and libsupc++.a is unchanged for all these targets.
* GCC also showed no testsuite regression when targeting ARMv8-M Baseline compared to ARMv6-M on ARM Fast Models and when targeting ARMv6-M and ARMv7-M (compared to without the patch)
* GCC was bootstrapped successfully targeting Thumb-1 and targeting Thumb-2
Is this ok for stage3?
Best regards,
Thomas
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH, ARM 7/7, ping1] Enable atomics for ARMv8-M Mainline
2015-12-17 9:39 [PATCH, ARM 7/6] Enable atomics for ARMv8-M Mainline Thomas Preud'homme
@ 2016-05-17 10:15 ` Thomas Preudhomme
2016-05-19 16:18 ` Kyrill Tkachov
0 siblings, 1 reply; 8+ messages in thread
From: Thomas Preudhomme @ 2016-05-17 10:15 UTC (permalink / raw)
To: Richard Earnshaw, Ramana Radhakrishnan, Kyrylo Tkachov; +Cc: gcc-patches
Ping?
*** gcc/ChangeLog ***
2015-12-17 Thomas Preud'homme <thomas.preudhomme@arm.com>
* config/arm/arm.h (TARGET_HAVE_LDACQ): Enable for ARMv8-M Mainline.
diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
index
347b5b0a5cc0bc1e3b5020c8124d968e76ce48a4..e154bd31b8084f9f45ad4409e7b38de652538c51
100644
--- a/gcc/config/arm/arm.h
+++ b/gcc/config/arm/arm.h
@@ -266,7 +266,7 @@ extern void (*arm_lang_output_object_attributes_hook)
(void);
|| arm_arch7) && arm_arch_notm)
/* Nonzero if this chip supports load-acquire and store-release. */
-#define TARGET_HAVE_LDACQ (TARGET_ARM_ARCH >= 8 && arm_arch_notm)
+#define TARGET_HAVE_LDACQ (TARGET_ARM_ARCH >= 8 && TARGET_32BIT)
/* Nonzero if this chip provides the movw and movt instructions. */
#define TARGET_HAVE_MOVT (arm_arch_thumb2 || arm_arch8)
Best regards,
Thomas
On Thursday 17 December 2015 17:39:29 Thomas Preud'homme wrote:
> Hi,
>
> This patch is part of a patch series to add support for ARMv8-M[1] to GCC.
> This specific patch enable atomics for ARMv8-M Mainline. No change is
> needed to existing patterns since Thumb-2 backend can already handle them
> fine.
>
> [1] For a quick overview of ARMv8-M please refer to the initial cover
> letter.
>
>
> ChangeLog entries are as follow:
>
> *** gcc/ChangeLog ***
>
> 2015-12-17 Thomas Preud'homme <thomas.preudhomme@arm.com>
>
> * config/arm/arm.h (TARGET_HAVE_LDACQ): Enable for ARMv8-M Mainline.
>
>
> diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
> index
> 1f79c37b5c36a410a2d500ba92c62a5ba4ca1178..fa2a6fb03ffd2ca53bfb7e7c8f03022b6
> 26880e0 100644 --- a/gcc/config/arm/arm.h
> +++ b/gcc/config/arm/arm.h
> @@ -258,7 +258,7 @@ extern void
> (*arm_lang_output_object_attributes_hook)(void);
> || arm_arch7) && arm_arch_notm)
>
> /* Nonzero if this chip supports load-acquire and store-release. */
> -#define TARGET_HAVE_LDACQ (TARGET_ARM_ARCH >= 8 && arm_arch_notm)
> +#define TARGET_HAVE_LDACQ (TARGET_ARM_ARCH >= 8 && TARGET_32BIT)
>
> /* Nonzero if this chip provides the movw and movt instructions. */
> #define TARGET_HAVE_MOVT (arm_arch_thumb2 || arm_arch8)
>
>
> Testing:
>
> * Toolchain was built successfully with and without the ARMv8-M support
> patches with the following multilib list:
> armv6-m,armv7-m,armv7e-m,cortex-m7. The code generation for crtbegin.o,
> crtend.o, crti.o, crtn.o, libgcc.a, libgcov.a, libc.a, libg.a,
> libgloss-linux.a, libm.a, libnosys.a, librdimon.a, librdpmon.a, libstdc++.a
> and libsupc++.a is unchanged for all these targets.
>
> * GCC also showed no testsuite regression when targeting ARMv8-M Baseline
> compared to ARMv6-M on ARM Fast Models and when targeting ARMv6-M and
> ARMv7-M (compared to without the patch) * GCC was bootstrapped successfully
> targeting Thumb-1 and targeting Thumb-2
>
> Is this ok for stage3?
>
> Best regards,
>
> Thomas
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH, ARM 7/7, ping1] Enable atomics for ARMv8-M Mainline
2016-05-17 10:15 ` [PATCH, ARM 7/7, ping1] " Thomas Preudhomme
@ 2016-05-19 16:18 ` Kyrill Tkachov
2016-05-19 16:48 ` Thomas Preudhomme
2016-07-14 13:38 ` [PATCH, ARM 7/7] " Thomas Preudhomme
0 siblings, 2 replies; 8+ messages in thread
From: Kyrill Tkachov @ 2016-05-19 16:18 UTC (permalink / raw)
To: Thomas Preudhomme, Richard Earnshaw, Ramana Radhakrishnan; +Cc: gcc-patches
Hi Thomas,
On 17/05/16 11:15, Thomas Preudhomme wrote:
> Ping?
>
> *** gcc/ChangeLog ***
>
> 2015-12-17 Thomas Preud'homme <thomas.preudhomme@arm.com>
>
> * config/arm/arm.h (TARGET_HAVE_LDACQ): Enable for ARMv8-M Mainline.
>
>
> diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
> index
> 347b5b0a5cc0bc1e3b5020c8124d968e76ce48a4..e154bd31b8084f9f45ad4409e7b38de652538c51
> 100644
> --- a/gcc/config/arm/arm.h
> +++ b/gcc/config/arm/arm.h
> @@ -266,7 +266,7 @@ extern void (*arm_lang_output_object_attributes_hook)
> (void);
> || arm_arch7) && arm_arch_notm)
>
> /* Nonzero if this chip supports load-acquire and store-release. */
> -#define TARGET_HAVE_LDACQ (TARGET_ARM_ARCH >= 8 && arm_arch_notm)
> +#define TARGET_HAVE_LDACQ (TARGET_ARM_ARCH >= 8 && TARGET_32BIT)
>
So this change is correct because ARMv8-M Mainline uses Thumb2
and is therefore TARGET_32BIT.
This is ok but I'd like to see a follow up patch to enable the tests
that exercise acquire-release instructions in the arm.exp testsuite
for ARMv8-M Mainline so that we can be sure they get proper testsuite
coverage.
Thanks,
Kyrill
> /* Nonzero if this chip provides the movw and movt instructions. */
> #define TARGET_HAVE_MOVT (arm_arch_thumb2 || arm_arch8)
>
>
> Best regards,
>
> Thomas
>
> On Thursday 17 December 2015 17:39:29 Thomas Preud'homme wrote:
>> Hi,
>>
>> This patch is part of a patch series to add support for ARMv8-M[1] to GCC.
>> This specific patch enable atomics for ARMv8-M Mainline. No change is
>> needed to existing patterns since Thumb-2 backend can already handle them
>> fine.
>>
>> [1] For a quick overview of ARMv8-M please refer to the initial cover
>> letter.
>>
>>
>> ChangeLog entries are as follow:
>>
>> *** gcc/ChangeLog ***
>>
>> 2015-12-17 Thomas Preud'homme <thomas.preudhomme@arm.com>
>>
>> * config/arm/arm.h (TARGET_HAVE_LDACQ): Enable for ARMv8-M Mainline.
>>
>>
>> diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
>> index
>> 1f79c37b5c36a410a2d500ba92c62a5ba4ca1178..fa2a6fb03ffd2ca53bfb7e7c8f03022b6
>> 26880e0 100644 --- a/gcc/config/arm/arm.h
>> +++ b/gcc/config/arm/arm.h
>> @@ -258,7 +258,7 @@ extern void
>> (*arm_lang_output_object_attributes_hook)(void);
>> || arm_arch7) && arm_arch_notm)
>>
>> /* Nonzero if this chip supports load-acquire and store-release. */
>> -#define TARGET_HAVE_LDACQ (TARGET_ARM_ARCH >= 8 && arm_arch_notm)
>> +#define TARGET_HAVE_LDACQ (TARGET_ARM_ARCH >= 8 && TARGET_32BIT)
>>
>> /* Nonzero if this chip provides the movw and movt instructions. */
>> #define TARGET_HAVE_MOVT (arm_arch_thumb2 || arm_arch8)
>>
>>
>> Testing:
>>
>> * Toolchain was built successfully with and without the ARMv8-M support
>> patches with the following multilib list:
>> armv6-m,armv7-m,armv7e-m,cortex-m7. The code generation for crtbegin.o,
>> crtend.o, crti.o, crtn.o, libgcc.a, libgcov.a, libc.a, libg.a,
>> libgloss-linux.a, libm.a, libnosys.a, librdimon.a, librdpmon.a, libstdc++.a
>> and libsupc++.a is unchanged for all these targets.
>>
>> * GCC also showed no testsuite regression when targeting ARMv8-M Baseline
>> compared to ARMv6-M on ARM Fast Models and when targeting ARMv6-M and
>> ARMv7-M (compared to without the patch) * GCC was bootstrapped successfully
>> targeting Thumb-1 and targeting Thumb-2
>>
>> Is this ok for stage3?
>>
>> Best regards,
>>
>> Thomas
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH, ARM 7/7, ping1] Enable atomics for ARMv8-M Mainline
2016-05-19 16:18 ` Kyrill Tkachov
@ 2016-05-19 16:48 ` Thomas Preudhomme
2016-07-14 13:38 ` [PATCH, ARM 7/7] " Thomas Preudhomme
1 sibling, 0 replies; 8+ messages in thread
From: Thomas Preudhomme @ 2016-05-19 16:48 UTC (permalink / raw)
To: Kyrill Tkachov; +Cc: Richard Earnshaw, Ramana Radhakrishnan, gcc-patches
On Thursday 19 May 2016 17:18:29 Kyrill Tkachov wrote:
> Hi Thomas,
>
> On 17/05/16 11:15, Thomas Preudhomme wrote:
> > Ping?
> >
> > *** gcc/ChangeLog ***
> >
> > 2015-12-17 Thomas Preud'homme <thomas.preudhomme@arm.com>
> >
> > * config/arm/arm.h (TARGET_HAVE_LDACQ): Enable for ARMv8-M
> > Mainline.
> >
> > diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
> > index
> > 347b5b0a5cc0bc1e3b5020c8124d968e76ce48a4..e154bd31b8084f9f45ad4409e7b38de6
> > 52538c51 100644
> > --- a/gcc/config/arm/arm.h
> > +++ b/gcc/config/arm/arm.h
> > @@ -266,7 +266,7 @@ extern void (*arm_lang_output_object_attributes_hook)
> > (void);
> >
> > || arm_arch7) && arm_arch_notm)
> >
> > /* Nonzero if this chip supports load-acquire and store-release. */
> >
> > -#define TARGET_HAVE_LDACQ (TARGET_ARM_ARCH >= 8 && arm_arch_notm)
> > +#define TARGET_HAVE_LDACQ (TARGET_ARM_ARCH >= 8 && TARGET_32BIT)
>
> So this change is correct because ARMv8-M Mainline uses Thumb2
> and is therefore TARGET_32BIT.
>
> This is ok but I'd like to see a follow up patch to enable the tests
> that exercise acquire-release instructions in the arm.exp testsuite
> for ARMv8-M Mainline so that we can be sure they get proper testsuite
> coverage.
Good thing I already have one around. I need to separate it from other stuff
though, so I'll probably send it on Monday.
Cheers,
Thomas
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH, ARM 7/7] Enable atomics for ARMv8-M Mainline
2016-05-19 16:18 ` Kyrill Tkachov
2016-05-19 16:48 ` Thomas Preudhomme
@ 2016-07-14 13:38 ` Thomas Preudhomme
2016-07-14 16:24 ` Kyrill Tkachov
1 sibling, 1 reply; 8+ messages in thread
From: Thomas Preudhomme @ 2016-07-14 13:38 UTC (permalink / raw)
To: Kyrill Tkachov; +Cc: Richard Earnshaw, Ramana Radhakrishnan, gcc-patches
[-- Attachment #1: Type: text/plain, Size: 4137 bytes --]
Hi Kyrill,
On Thursday 19 May 2016 17:18:29 Kyrill Tkachov wrote:
> Hi Thomas,
>
> On 17/05/16 11:15, Thomas Preudhomme wrote:
> > Ping?
> >
> > *** gcc/ChangeLog ***
> >
> > 2015-12-17 Thomas Preud'homme <thomas.preudhomme@arm.com>
> >
> > * config/arm/arm.h (TARGET_HAVE_LDACQ): Enable for ARMv8-M
> > Mainline.
> >
> > diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
> > index
> > 347b5b0a5cc0bc1e3b5020c8124d968e76ce48a4..e154bd31b8084f9f45ad4409e7b38de6
> > 52538c51 100644
> > --- a/gcc/config/arm/arm.h
> > +++ b/gcc/config/arm/arm.h
> > @@ -266,7 +266,7 @@ extern void (*arm_lang_output_object_attributes_hook)
> > (void);
> >
> > || arm_arch7) && arm_arch_notm)
> >
> > /* Nonzero if this chip supports load-acquire and store-release. */
> >
> > -#define TARGET_HAVE_LDACQ (TARGET_ARM_ARCH >= 8 && arm_arch_notm)
> > +#define TARGET_HAVE_LDACQ (TARGET_ARM_ARCH >= 8 && TARGET_32BIT)
>
> So this change is correct because ARMv8-M Mainline uses Thumb2
> and is therefore TARGET_32BIT.
>
> This is ok but I'd like to see a follow up patch to enable the tests
> that exercise acquire-release instructions in the arm.exp testsuite
> for ARMv8-M Mainline so that we can be sure they get proper testsuite
> coverage.
I've respinned the patch because of the changes to atomic_loaddi output
template in config/arm/sync.md. This patch now creates a new macro
TARGET_HAVE_LDACQEXD to guard LDACQEXD and STLEXD instructions that are not
available in ARMv8-M Mainline. It took advantage of the respin to also add the
tests you were asking for.
ChangeLog entries are as follow:
*** gcc/ChangeLog ***
2016-07-05 Thomas Preud'homme <thomas.preudhomme@arm.com>
* config/arm/arm.h (TARGET_HAVE_LDACQ): Enable for ARMv8-M Mainline.
(TARGET_HAVE_LDACQD): New macro.
* config/arm/sync.md (atomic_loaddi): Use TARGET_HAVE_LDACQD rather
than TARGET_HAVE_LDACQ.
(arm_load_acquire_exclusivedi): Likewise.
(arm_store_release_exclusivedi): Likewise.
*** gcc/testsuite/ChangeLog ***
2016-07-05 Thomas Preud'homme <thomas.preudhomme@arm.com>
* gcc.target/arm/atomic-comp-swap-release-acquire.c: Rename into ...
* gcc.target/arm/atomic-comp-swap-release-acquire-1.c: This.
* gcc.target/arm/atomic-op-acq_rel.c: Rename into ...
* gcc.target/arm/atomic-op-acq_rel-1.c: This.
* gcc.target/arm/atomic-op-acquire.c: Rename into ...
* gcc.target/arm/atomic-op-acquire-1.c: This.
* gcc.target/arm/atomic-op-char.c: Rename into ...
* gcc.target/arm/atomic-op-char-1.c: This.
* gcc.target/arm/atomic-op-consume.c: Rename into ...
* gcc.target/arm/atomic-op-consume-1.c: This.
* gcc.target/arm/atomic-op-int.c: Rename into ...
* gcc.target/arm/atomic-op-int-1.c: This.
* gcc.target/arm/atomic-op-relaxed.c: Rename into ...
* gcc.target/arm/atomic-op-relaxed-1.c: This.
* gcc.target/arm/atomic-op-release.c: Rename into ...
* gcc.target/arm/atomic-op-release-1.c: This.
* gcc.target/arm/atomic-op-seq_cst.c: Rename into ...
* gcc.target/arm/atomic-op-seq_cst-1.c: This.
* gcc.target/arm/atomic-op-short.c: Rename into ...
* gcc.target/arm/atomic-op-short-1.c: This.
* gcc.target/arm/atomic-comp-swap-release-acquire-2.c: New test.
* gcc.target/arm/atomic-op-acq_rel-2.c: Likewise.
* gcc.target/arm/atomic-op-acquire-2.c: Likewise.
* gcc.target/arm/atomic-op-char-2.c: Likewise.
* gcc.target/arm/atomic-op-consume-2.c: Likewise.
* gcc.target/arm/atomic-op-int-2.c: Likewise.
* gcc.target/arm/atomic-op-relaxed-2.c: Likewise.
* gcc.target/arm/atomic-op-release-2.c: Likewise.
* gcc.target/arm/atomic-op-seq_cst-2.c: Likewise.
* gcc.target/arm/atomic-op-short-2.c: Likewise.
Testsuite shows no regression and atomic tests [1] are passing for ARMv8-M
Mainline.
[1] gcc.dg/atomic*, g++.dg/ext/atomic*, gcc.target/arm/atomic*,
gcc.target/arm/sync* and libstdc++-v3/testsuite/29_atomic/*
Best regards,
Thomas
[-- Attachment #2: v8m_main_atomic.patch --]
[-- Type: text/x-patch, Size: 12600 bytes --]
diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
index 317885cf7197b6755c4d9b5717afe61662626786..c7149d1f49738f9f01232cdcb610caca0e5f7e5d 100644
--- a/gcc/config/arm/arm.h
+++ b/gcc/config/arm/arm.h
@@ -261,7 +261,12 @@ extern void (*arm_lang_output_object_attributes_hook)(void);
|| arm_arch7) && arm_arch_notm)
/* Nonzero if this chip supports load-acquire and store-release. */
-#define TARGET_HAVE_LDACQ (TARGET_ARM_ARCH >= 8 && arm_arch_notm)
+#define TARGET_HAVE_LDACQ (TARGET_ARM_ARCH >= 8 && TARGET_32BIT)
+
+/* Nonzero if this chip supports LDAEXD and STLEXD. */
+#define TARGET_HAVE_LDACQEXD (TARGET_ARM_ARCH >= 8 \
+ && TARGET_32BIT \
+ && arm_arch_notm)
/* Nonzero if this chip provides the MOVW and MOVT instructions. */
#define TARGET_HAVE_MOVT (arm_arch_thumb2 || arm_arch8)
diff --git a/gcc/config/arm/sync.md b/gcc/config/arm/sync.md
index abcfbcb1eacaabc597c9fde475c1b56624fb5a59..d10ede4175f94e627a23bf32d19d2b5f3de76771 100644
--- a/gcc/config/arm/sync.md
+++ b/gcc/config/arm/sync.md
@@ -117,7 +117,7 @@
[(match_operand:DI 0 "s_register_operand") ;; val out
(match_operand:DI 1 "mem_noofs_operand") ;; memory
(match_operand:SI 2 "const_int_operand")] ;; model
- "(TARGET_HAVE_LDREXD || TARGET_HAVE_LPAE || TARGET_HAVE_LDACQ)
+ "(TARGET_HAVE_LDREXD || TARGET_HAVE_LPAE || TARGET_HAVE_LDACQEXD)
&& ARM_DOUBLEWORD_ALIGN"
{
memmodel model = memmodel_from_int (INTVAL (operands[2]));
@@ -125,7 +125,7 @@
/* For ARMv8-A we can use an LDAEXD to atomically load two 32-bit registers
when acquire or stronger semantics are needed. When the relaxed model is
used this can be relaxed to a normal LDRD. */
- if (TARGET_HAVE_LDACQ)
+ if (TARGET_HAVE_LDACQEXD)
{
if (is_mm_relaxed (model))
emit_insn (gen_arm_atomic_loaddi2_ldrd (operands[0], operands[1]));
@@ -436,7 +436,7 @@
(unspec_volatile:DI
[(match_operand:DI 1 "mem_noofs_operand" "Ua")]
VUNSPEC_LAX))]
- "TARGET_HAVE_LDACQ && ARM_DOUBLEWORD_ALIGN"
+ "TARGET_HAVE_LDACQEXD && ARM_DOUBLEWORD_ALIGN"
"ldaexd%?\t%0, %H0, %C1"
[(set_attr "predicable" "yes")
(set_attr "predicable_short_it" "no")])
@@ -472,7 +472,7 @@
(unspec_volatile:DI
[(match_operand:DI 2 "s_register_operand" "r")]
VUNSPEC_SLX))]
- "TARGET_HAVE_LDACQ && ARM_DOUBLEWORD_ALIGN"
+ "TARGET_HAVE_LDACQEXD && ARM_DOUBLEWORD_ALIGN"
{
/* See comment in arm_store_exclusive<mode> above. */
gcc_assert ((REGNO (operands[2]) & 1) == 0 || TARGET_THUMB2);
diff --git a/gcc/testsuite/gcc.target/arm/atomic-comp-swap-release-acquire-2.c b/gcc/testsuite/gcc.target/arm/atomic-comp-swap-release-acquire-2.c
new file mode 100644
index 0000000000000000000000000000000000000000..73b140aaae4ee65e12ff8bc67b33c29f6f720f6e
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/atomic-comp-swap-release-acquire-2.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_arch_v8m_main_ok } */
+/* { dg-options "-O2 -fno-ipa-icf" } */
+/* { dg-add-options arm_arch_v8m_main } */
+
+#include "../aarch64/atomic-comp-swap-release-acquire.x"
+
+/* { dg-final { scan-assembler-times "ldaex" 4 } } */
+/* { dg-final { scan-assembler-times "stlex" 4 } } */
+/* { dg-final { scan-assembler-not "dmb" } } */
diff --git a/gcc/testsuite/gcc.target/arm/atomic-comp-swap-release-acquire.c b/gcc/testsuite/gcc.target/arm/atomic-comp-swap-release-acquire-1.c
similarity index 100%
rename from gcc/testsuite/gcc.target/arm/atomic-comp-swap-release-acquire.c
rename to gcc/testsuite/gcc.target/arm/atomic-comp-swap-release-acquire-1.c
diff --git a/gcc/testsuite/gcc.target/arm/atomic-op-acq_rel-2.c b/gcc/testsuite/gcc.target/arm/atomic-op-acq_rel-2.c
new file mode 100644
index 0000000000000000000000000000000000000000..26f88c8775a09f7948bc3b503649686acd4ca5df
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/atomic-op-acq_rel-2.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_arch_v8m_main_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_arch_v8m_main } */
+
+#include "../aarch64/atomic-op-acq_rel.x"
+
+/* { dg-final { scan-assembler-times "ldaex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+/* { dg-final { scan-assembler-times "stlex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+/* { dg-final { scan-assembler-not "dmb" } } */
diff --git a/gcc/testsuite/gcc.target/arm/atomic-op-acq_rel.c b/gcc/testsuite/gcc.target/arm/atomic-op-acq_rel-1.c
similarity index 100%
rename from gcc/testsuite/gcc.target/arm/atomic-op-acq_rel.c
rename to gcc/testsuite/gcc.target/arm/atomic-op-acq_rel-1.c
diff --git a/gcc/testsuite/gcc.target/arm/atomic-op-acquire-2.c b/gcc/testsuite/gcc.target/arm/atomic-op-acquire-2.c
new file mode 100644
index 0000000000000000000000000000000000000000..09062eba358724ea5207d865d5e5dda54e4950ef
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/atomic-op-acquire-2.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_arch_v8m_main_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_arch_v8m_main } */
+
+#include "../aarch64/atomic-op-acquire.x"
+
+/* { dg-final { scan-assembler-times "ldaex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+/* { dg-final { scan-assembler-times "strex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+/* { dg-final { scan-assembler-not "dmb" } } */
diff --git a/gcc/testsuite/gcc.target/arm/atomic-op-acquire.c b/gcc/testsuite/gcc.target/arm/atomic-op-acquire-1.c
similarity index 100%
rename from gcc/testsuite/gcc.target/arm/atomic-op-acquire.c
rename to gcc/testsuite/gcc.target/arm/atomic-op-acquire-1.c
diff --git a/gcc/testsuite/gcc.target/arm/atomic-op-char-2.c b/gcc/testsuite/gcc.target/arm/atomic-op-char-2.c
new file mode 100644
index 0000000000000000000000000000000000000000..3f33857cf68929420617ea12b25d7a6ac0210c81
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/atomic-op-char-2.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_arch_v8m_main_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_arch_v8m_main } */
+
+#include "../aarch64/atomic-op-char.x"
+
+/* { dg-final { scan-assembler-times "ldrexb\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+/* { dg-final { scan-assembler-times "strexb\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+/* { dg-final { scan-assembler-not "dmb" } } */
diff --git a/gcc/testsuite/gcc.target/arm/atomic-op-char.c b/gcc/testsuite/gcc.target/arm/atomic-op-char-1.c
similarity index 100%
rename from gcc/testsuite/gcc.target/arm/atomic-op-char.c
rename to gcc/testsuite/gcc.target/arm/atomic-op-char-1.c
diff --git a/gcc/testsuite/gcc.target/arm/atomic-op-consume-2.c b/gcc/testsuite/gcc.target/arm/atomic-op-consume-2.c
new file mode 100644
index 0000000000000000000000000000000000000000..9771d817f02cb95a2e9d4f7020ae45c3fcf02aec
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/atomic-op-consume-2.c
@@ -0,0 +1,11 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_arch_v8m_main_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_arch_v8m_main } */
+
+#include "../aarch64/atomic-op-consume.x"
+
+/* Scan for ldaex is a PR59448 consume workaround. */
+/* { dg-final { scan-assembler-times "ldaex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+/* { dg-final { scan-assembler-times "strex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+/* { dg-final { scan-assembler-not "dmb" } } */
diff --git a/gcc/testsuite/gcc.target/arm/atomic-op-consume.c b/gcc/testsuite/gcc.target/arm/atomic-op-consume-1.c
similarity index 100%
rename from gcc/testsuite/gcc.target/arm/atomic-op-consume.c
rename to gcc/testsuite/gcc.target/arm/atomic-op-consume-1.c
diff --git a/gcc/testsuite/gcc.target/arm/atomic-op-int-2.c b/gcc/testsuite/gcc.target/arm/atomic-op-int-2.c
new file mode 100644
index 0000000000000000000000000000000000000000..ce0fbfcc0cb74c92648f0ffd9dce4131f1d98e05
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/atomic-op-int-2.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_arch_v8m_main_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_arch_v8m_main } */
+
+#include "../aarch64/atomic-op-int.x"
+
+/* { dg-final { scan-assembler-times "ldrex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+/* { dg-final { scan-assembler-times "strex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+/* { dg-final { scan-assembler-not "dmb" } } */
diff --git a/gcc/testsuite/gcc.target/arm/atomic-op-int.c b/gcc/testsuite/gcc.target/arm/atomic-op-int-1.c
similarity index 100%
rename from gcc/testsuite/gcc.target/arm/atomic-op-int.c
rename to gcc/testsuite/gcc.target/arm/atomic-op-int-1.c
diff --git a/gcc/testsuite/gcc.target/arm/atomic-op-relaxed-2.c b/gcc/testsuite/gcc.target/arm/atomic-op-relaxed-2.c
new file mode 100644
index 0000000000000000000000000000000000000000..207baf77d2af6dfe814b86075fc95810268f6a47
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/atomic-op-relaxed-2.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_arch_v8m_main_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_arch_v8m_main } */
+
+#include "../aarch64/atomic-op-relaxed.x"
+
+/* { dg-final { scan-assembler-times "ldrex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+/* { dg-final { scan-assembler-times "strex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+/* { dg-final { scan-assembler-not "dmb" } } */
diff --git a/gcc/testsuite/gcc.target/arm/atomic-op-relaxed.c b/gcc/testsuite/gcc.target/arm/atomic-op-relaxed-1.c
similarity index 100%
rename from gcc/testsuite/gcc.target/arm/atomic-op-relaxed.c
rename to gcc/testsuite/gcc.target/arm/atomic-op-relaxed-1.c
diff --git a/gcc/testsuite/gcc.target/arm/atomic-op-release-2.c b/gcc/testsuite/gcc.target/arm/atomic-op-release-2.c
new file mode 100644
index 0000000000000000000000000000000000000000..376f8597581c82e02b9685085a19abe704855c55
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/atomic-op-release-2.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_arch_v8m_main_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_arch_v8m_main } */
+
+#include "../aarch64/atomic-op-release.x"
+
+/* { dg-final { scan-assembler-times "ldrex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+/* { dg-final { scan-assembler-times "stlex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+/* { dg-final { scan-assembler-not "dmb" } } */
diff --git a/gcc/testsuite/gcc.target/arm/atomic-op-release.c b/gcc/testsuite/gcc.target/arm/atomic-op-release-1.c
similarity index 100%
rename from gcc/testsuite/gcc.target/arm/atomic-op-release.c
rename to gcc/testsuite/gcc.target/arm/atomic-op-release-1.c
diff --git a/gcc/testsuite/gcc.target/arm/atomic-op-seq_cst-2.c b/gcc/testsuite/gcc.target/arm/atomic-op-seq_cst-2.c
new file mode 100644
index 0000000000000000000000000000000000000000..4b31083dc42629594c3096fbe13e32505d491582
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/atomic-op-seq_cst-2.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_arch_v8m_main_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_arch_v8m_main } */
+
+#include "../aarch64/atomic-op-seq_cst.x"
+
+/* { dg-final { scan-assembler-times "ldaex\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+/* { dg-final { scan-assembler-times "stlex\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+/* { dg-final { scan-assembler-not "dmb" } } */
diff --git a/gcc/testsuite/gcc.target/arm/atomic-op-seq_cst.c b/gcc/testsuite/gcc.target/arm/atomic-op-seq_cst-1.c
similarity index 100%
rename from gcc/testsuite/gcc.target/arm/atomic-op-seq_cst.c
rename to gcc/testsuite/gcc.target/arm/atomic-op-seq_cst-1.c
diff --git a/gcc/testsuite/gcc.target/arm/atomic-op-short-2.c b/gcc/testsuite/gcc.target/arm/atomic-op-short-2.c
new file mode 100644
index 0000000000000000000000000000000000000000..e9b35f3d0a76280b3ef7a972230d91d7d04d2acf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/arm/atomic-op-short-2.c
@@ -0,0 +1,10 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target arm_arch_v8m_main_ok } */
+/* { dg-options "-O2" } */
+/* { dg-add-options arm_arch_v8m_main } */
+
+#include "../aarch64/atomic-op-short.x"
+
+/* { dg-final { scan-assembler-times "ldrexh\tr\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+/* { dg-final { scan-assembler-times "strexh\t...?, r\[0-9\]+, \\\[r\[0-9\]+\\\]" 6 } } */
+/* { dg-final { scan-assembler-not "dmb" } } */
diff --git a/gcc/testsuite/gcc.target/arm/atomic-op-short.c b/gcc/testsuite/gcc.target/arm/atomic-op-short-1.c
similarity index 100%
rename from gcc/testsuite/gcc.target/arm/atomic-op-short.c
rename to gcc/testsuite/gcc.target/arm/atomic-op-short-1.c
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH, ARM 7/7] Enable atomics for ARMv8-M Mainline
2016-07-14 13:38 ` [PATCH, ARM 7/7] " Thomas Preudhomme
@ 2016-07-14 16:24 ` Kyrill Tkachov
2016-07-14 16:35 ` Thomas Preudhomme
0 siblings, 1 reply; 8+ messages in thread
From: Kyrill Tkachov @ 2016-07-14 16:24 UTC (permalink / raw)
To: Thomas Preudhomme; +Cc: Richard Earnshaw, Ramana Radhakrishnan, gcc-patches
Hi Thomas,
On 14/07/16 14:37, Thomas Preudhomme wrote:
> Hi Kyrill,
>
> On Thursday 19 May 2016 17:18:29 Kyrill Tkachov wrote:
>> Hi Thomas,
>>
>> On 17/05/16 11:15, Thomas Preudhomme wrote:
>>> Ping?
>>>
>>> *** gcc/ChangeLog ***
>>>
>>> 2015-12-17 Thomas Preud'homme <thomas.preudhomme@arm.com>
>>>
>>> * config/arm/arm.h (TARGET_HAVE_LDACQ): Enable for ARMv8-M
>>> Mainline.
>>>
>>> diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
>>> index
>>> 347b5b0a5cc0bc1e3b5020c8124d968e76ce48a4..e154bd31b8084f9f45ad4409e7b38de6
>>> 52538c51 100644
>>> --- a/gcc/config/arm/arm.h
>>> +++ b/gcc/config/arm/arm.h
>>> @@ -266,7 +266,7 @@ extern void (*arm_lang_output_object_attributes_hook)
>>> (void);
>>>
>>> || arm_arch7) && arm_arch_notm)
>>>
>>> /* Nonzero if this chip supports load-acquire and store-release. */
>>>
>>> -#define TARGET_HAVE_LDACQ (TARGET_ARM_ARCH >= 8 && arm_arch_notm)
>>> +#define TARGET_HAVE_LDACQ (TARGET_ARM_ARCH >= 8 && TARGET_32BIT)
>> So this change is correct because ARMv8-M Mainline uses Thumb2
>> and is therefore TARGET_32BIT.
>>
>> This is ok but I'd like to see a follow up patch to enable the tests
>> that exercise acquire-release instructions in the arm.exp testsuite
>> for ARMv8-M Mainline so that we can be sure they get proper testsuite
>> coverage.
> I've respinned the patch because of the changes to atomic_loaddi output
> template in config/arm/sync.md. This patch now creates a new macro
> TARGET_HAVE_LDACQEXD to guard LDACQEXD and STLEXD instructions that are not
> available in ARMv8-M Mainline. It took advantage of the respin to also add the
> tests you were asking for.
>
> ChangeLog entries are as follow:
>
> *** gcc/ChangeLog ***
>
> 2016-07-05 Thomas Preud'homme <thomas.preudhomme@arm.com>
>
> * config/arm/arm.h (TARGET_HAVE_LDACQ): Enable for ARMv8-M Mainline.
> (TARGET_HAVE_LDACQD): New macro.
> * config/arm/sync.md (atomic_loaddi): Use TARGET_HAVE_LDACQD rather
> than TARGET_HAVE_LDACQ.
> (arm_load_acquire_exclusivedi): Likewise.
> (arm_store_release_exclusivedi): Likewise.
>
>
> *** gcc/testsuite/ChangeLog ***
>
> 2016-07-05 Thomas Preud'homme <thomas.preudhomme@arm.com>
>
> * gcc.target/arm/atomic-comp-swap-release-acquire.c: Rename into ...
> * gcc.target/arm/atomic-comp-swap-release-acquire-1.c: This.
> * gcc.target/arm/atomic-op-acq_rel.c: Rename into ...
> * gcc.target/arm/atomic-op-acq_rel-1.c: This.
> * gcc.target/arm/atomic-op-acquire.c: Rename into ...
> * gcc.target/arm/atomic-op-acquire-1.c: This.
> * gcc.target/arm/atomic-op-char.c: Rename into ...
> * gcc.target/arm/atomic-op-char-1.c: This.
> * gcc.target/arm/atomic-op-consume.c: Rename into ...
> * gcc.target/arm/atomic-op-consume-1.c: This.
> * gcc.target/arm/atomic-op-int.c: Rename into ...
> * gcc.target/arm/atomic-op-int-1.c: This.
> * gcc.target/arm/atomic-op-relaxed.c: Rename into ...
> * gcc.target/arm/atomic-op-relaxed-1.c: This.
> * gcc.target/arm/atomic-op-release.c: Rename into ...
> * gcc.target/arm/atomic-op-release-1.c: This.
> * gcc.target/arm/atomic-op-seq_cst.c: Rename into ...
> * gcc.target/arm/atomic-op-seq_cst-1.c: This.
> * gcc.target/arm/atomic-op-short.c: Rename into ...
> * gcc.target/arm/atomic-op-short-1.c: This.
> * gcc.target/arm/atomic-comp-swap-release-acquire-2.c: New test.
> * gcc.target/arm/atomic-op-acq_rel-2.c: Likewise.
> * gcc.target/arm/atomic-op-acquire-2.c: Likewise.
> * gcc.target/arm/atomic-op-char-2.c: Likewise.
> * gcc.target/arm/atomic-op-consume-2.c: Likewise.
> * gcc.target/arm/atomic-op-int-2.c: Likewise.
> * gcc.target/arm/atomic-op-relaxed-2.c: Likewise.
> * gcc.target/arm/atomic-op-release-2.c: Likewise.
> * gcc.target/arm/atomic-op-seq_cst-2.c: Likewise.
> * gcc.target/arm/atomic-op-short-2.c: Likewise.
>
>
> Testsuite shows no regression and atomic tests [1] are passing for ARMv8-M
> Mainline.
>
> [1] gcc.dg/atomic*, g++.dg/ext/atomic*, gcc.target/arm/atomic*,
> gcc.target/arm/sync* and libstdc++-v3/testsuite/29_atomic/*
Thanks, this is ok if testing on arm-none-linux-gnueabihf is ok.
In particular, please make sure that the tests still pass for an A-profile target.
Kyrill
>
> Best regards,
>
> Thomas
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: [PATCH, ARM 7/7] Enable atomics for ARMv8-M Mainline
2016-07-14 16:24 ` Kyrill Tkachov
@ 2016-07-14 16:35 ` Thomas Preudhomme
2016-09-01 12:43 ` [arm-embedded] " Thomas Preudhomme
0 siblings, 1 reply; 8+ messages in thread
From: Thomas Preudhomme @ 2016-07-14 16:35 UTC (permalink / raw)
To: Kyrill Tkachov; +Cc: Richard Earnshaw, Ramana Radhakrishnan, gcc-patches
On Thursday 14 July 2016 17:23:46 Kyrill Tkachov wrote:
> Hi Thomas,
>
> On 14/07/16 14:37, Thomas Preudhomme wrote:
> > Hi Kyrill,
> >
> > On Thursday 19 May 2016 17:18:29 Kyrill Tkachov wrote:
> >> Hi Thomas,
> >>
> >> On 17/05/16 11:15, Thomas Preudhomme wrote:
> >>> Ping?
> >>>
> >>> *** gcc/ChangeLog ***
> >>>
> >>> 2015-12-17 Thomas Preud'homme <thomas.preudhomme@arm.com>
> >>>
> >>> * config/arm/arm.h (TARGET_HAVE_LDACQ): Enable for ARMv8-M
> >>> Mainline.
> >>>
> >>> diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
> >>> index
> >>> 347b5b0a5cc0bc1e3b5020c8124d968e76ce48a4..e154bd31b8084f9f45ad4409e7b38d
> >>> e6
> >>> 52538c51 100644
> >>> --- a/gcc/config/arm/arm.h
> >>> +++ b/gcc/config/arm/arm.h
> >>> @@ -266,7 +266,7 @@ extern void
> >>> (*arm_lang_output_object_attributes_hook)
> >>> (void);
> >>>
> >>> || arm_arch7) && arm_arch_notm)
> >>>
> >>> /* Nonzero if this chip supports load-acquire and store-release. */
> >>>
> >>> -#define TARGET_HAVE_LDACQ (TARGET_ARM_ARCH >= 8 && arm_arch_notm)
> >>> +#define TARGET_HAVE_LDACQ (TARGET_ARM_ARCH >= 8 && TARGET_32BIT)
> >>
> >> So this change is correct because ARMv8-M Mainline uses Thumb2
> >> and is therefore TARGET_32BIT.
> >>
> >> This is ok but I'd like to see a follow up patch to enable the tests
> >> that exercise acquire-release instructions in the arm.exp testsuite
> >> for ARMv8-M Mainline so that we can be sure they get proper testsuite
> >> coverage.
> >
> > I've respinned the patch because of the changes to atomic_loaddi output
> > template in config/arm/sync.md. This patch now creates a new macro
> > TARGET_HAVE_LDACQEXD to guard LDACQEXD and STLEXD instructions that are
> > not
> > available in ARMv8-M Mainline. It took advantage of the respin to also add
> > the tests you were asking for.
> >
> > ChangeLog entries are as follow:
> >
> > *** gcc/ChangeLog ***
> >
> > 2016-07-05 Thomas Preud'homme <thomas.preudhomme@arm.com>
> >
> > * config/arm/arm.h (TARGET_HAVE_LDACQ): Enable for ARMv8-M
> > Mainline.
> > (TARGET_HAVE_LDACQD): New macro.
> > * config/arm/sync.md (atomic_loaddi): Use TARGET_HAVE_LDACQD
> > rather
> > than TARGET_HAVE_LDACQ.
> > (arm_load_acquire_exclusivedi): Likewise.
> > (arm_store_release_exclusivedi): Likewise.
> >
> > *** gcc/testsuite/ChangeLog ***
> >
> > 2016-07-05 Thomas Preud'homme <thomas.preudhomme@arm.com>
> >
> > * gcc.target/arm/atomic-comp-swap-release-acquire.c: Rename into
> > ...
> > * gcc.target/arm/atomic-comp-swap-release-acquire-1.c: This.
> > * gcc.target/arm/atomic-op-acq_rel.c: Rename into ...
> > * gcc.target/arm/atomic-op-acq_rel-1.c: This.
> > * gcc.target/arm/atomic-op-acquire.c: Rename into ...
> > * gcc.target/arm/atomic-op-acquire-1.c: This.
> > * gcc.target/arm/atomic-op-char.c: Rename into ...
> > * gcc.target/arm/atomic-op-char-1.c: This.
> > * gcc.target/arm/atomic-op-consume.c: Rename into ...
> > * gcc.target/arm/atomic-op-consume-1.c: This.
> > * gcc.target/arm/atomic-op-int.c: Rename into ...
> > * gcc.target/arm/atomic-op-int-1.c: This.
> > * gcc.target/arm/atomic-op-relaxed.c: Rename into ...
> > * gcc.target/arm/atomic-op-relaxed-1.c: This.
> > * gcc.target/arm/atomic-op-release.c: Rename into ...
> > * gcc.target/arm/atomic-op-release-1.c: This.
> > * gcc.target/arm/atomic-op-seq_cst.c: Rename into ...
> > * gcc.target/arm/atomic-op-seq_cst-1.c: This.
> > * gcc.target/arm/atomic-op-short.c: Rename into ...
> > * gcc.target/arm/atomic-op-short-1.c: This.
> > * gcc.target/arm/atomic-comp-swap-release-acquire-2.c: New test.
> > * gcc.target/arm/atomic-op-acq_rel-2.c: Likewise.
> > * gcc.target/arm/atomic-op-acquire-2.c: Likewise.
> > * gcc.target/arm/atomic-op-char-2.c: Likewise.
> > * gcc.target/arm/atomic-op-consume-2.c: Likewise.
> > * gcc.target/arm/atomic-op-int-2.c: Likewise.
> > * gcc.target/arm/atomic-op-relaxed-2.c: Likewise.
> > * gcc.target/arm/atomic-op-release-2.c: Likewise.
> > * gcc.target/arm/atomic-op-seq_cst-2.c: Likewise.
> > * gcc.target/arm/atomic-op-short-2.c: Likewise.
> >
> > Testsuite shows no regression and atomic tests [1] are passing for ARMv8-M
> > Mainline.
> >
> > [1] gcc.dg/atomic*, g++.dg/ext/atomic*, gcc.target/arm/atomic*,
> > gcc.target/arm/sync* and libstdc++-v3/testsuite/29_atomic/*
>
> Thanks, this is ok if testing on arm-none-linux-gnueabihf is ok.
> In particular, please make sure that the tests still pass for an A-profile
> target.
Oh yes, I forgot to mention that I also tested the same tests for armv8-a
without any code generation change for both ARM and Thumb. The whole testsuite
shows no regression as well.
Best regards,
Thomas
^ permalink raw reply [flat|nested] 8+ messages in thread
* [arm-embedded] [PATCH, ARM 7/7] Enable atomics for ARMv8-M Mainline
2016-07-14 16:35 ` Thomas Preudhomme
@ 2016-09-01 12:43 ` Thomas Preudhomme
0 siblings, 0 replies; 8+ messages in thread
From: Thomas Preudhomme @ 2016-09-01 12:43 UTC (permalink / raw)
To: gcc-patches
Hi,
We've decided to apply the following patch to ARM/embedded-6-branch.
Best regards,
Thomas
-------- Forwarded Message --------
Subject: Re: [PATCH, ARM 7/7] Enable atomics for ARMv8-M Mainline
Date: Thu, 14 Jul 2016 17:34:44 +0100
From: Thomas Preudhomme <thomas.preudhomme@foss.arm.com>
Organization: ARM
To: Kyrill Tkachov <kyrylo.tkachov@foss.arm.com>
CC: Richard Earnshaw <Richard.Earnshaw@arm.com>, Ramana Radhakrishnan
<ramana.radhakrishnan@arm.com>, gcc-patches@gcc.gnu.org
On Thursday 14 July 2016 17:23:46 Kyrill Tkachov wrote:
> Hi Thomas,
>
> On 14/07/16 14:37, Thomas Preudhomme wrote:
> > Hi Kyrill,
> >
> > On Thursday 19 May 2016 17:18:29 Kyrill Tkachov wrote:
> >> Hi Thomas,
> >>
> >> On 17/05/16 11:15, Thomas Preudhomme wrote:
> >>> Ping?
> >>>
> >>> *** gcc/ChangeLog ***
> >>>
> >>> 2015-12-17 Thomas Preud'homme <thomas.preudhomme@arm.com>
> >>>
> >>> * config/arm/arm.h (TARGET_HAVE_LDACQ): Enable for ARMv8-M
> >>> Mainline.
> >>>
> >>> diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h
> >>> index
> >>> 347b5b0a5cc0bc1e3b5020c8124d968e76ce48a4..e154bd31b8084f9f45ad4409e7b38d
> >>> e6
> >>> 52538c51 100644
> >>> --- a/gcc/config/arm/arm.h
> >>> +++ b/gcc/config/arm/arm.h
> >>> @@ -266,7 +266,7 @@ extern void
> >>> (*arm_lang_output_object_attributes_hook)
> >>> (void);
> >>>
> >>> || arm_arch7) && arm_arch_notm)
> >>>
> >>> /* Nonzero if this chip supports load-acquire and store-release. */
> >>>
> >>> -#define TARGET_HAVE_LDACQ (TARGET_ARM_ARCH >= 8 && arm_arch_notm)
> >>> +#define TARGET_HAVE_LDACQ (TARGET_ARM_ARCH >= 8 && TARGET_32BIT)
> >>
> >> So this change is correct because ARMv8-M Mainline uses Thumb2
> >> and is therefore TARGET_32BIT.
> >>
> >> This is ok but I'd like to see a follow up patch to enable the tests
> >> that exercise acquire-release instructions in the arm.exp testsuite
> >> for ARMv8-M Mainline so that we can be sure they get proper testsuite
> >> coverage.
> >
> > I've respinned the patch because of the changes to atomic_loaddi output
> > template in config/arm/sync.md. This patch now creates a new macro
> > TARGET_HAVE_LDACQEXD to guard LDACQEXD and STLEXD instructions that are
> > not
> > available in ARMv8-M Mainline. It took advantage of the respin to also add
> > the tests you were asking for.
> >
> > ChangeLog entries are as follow:
> >
> > *** gcc/ChangeLog ***
> >
> > 2016-07-05 Thomas Preud'homme <thomas.preudhomme@arm.com>
> >
> > * config/arm/arm.h (TARGET_HAVE_LDACQ): Enable for ARMv8-M
> > Mainline.
> > (TARGET_HAVE_LDACQD): New macro.
> > * config/arm/sync.md (atomic_loaddi): Use TARGET_HAVE_LDACQD
> > rather
> > than TARGET_HAVE_LDACQ.
> > (arm_load_acquire_exclusivedi): Likewise.
> > (arm_store_release_exclusivedi): Likewise.
> >
> > *** gcc/testsuite/ChangeLog ***
> >
> > 2016-07-05 Thomas Preud'homme <thomas.preudhomme@arm.com>
> >
> > * gcc.target/arm/atomic-comp-swap-release-acquire.c: Rename into
> > ...
> > * gcc.target/arm/atomic-comp-swap-release-acquire-1.c: This.
> > * gcc.target/arm/atomic-op-acq_rel.c: Rename into ...
> > * gcc.target/arm/atomic-op-acq_rel-1.c: This.
> > * gcc.target/arm/atomic-op-acquire.c: Rename into ...
> > * gcc.target/arm/atomic-op-acquire-1.c: This.
> > * gcc.target/arm/atomic-op-char.c: Rename into ...
> > * gcc.target/arm/atomic-op-char-1.c: This.
> > * gcc.target/arm/atomic-op-consume.c: Rename into ...
> > * gcc.target/arm/atomic-op-consume-1.c: This.
> > * gcc.target/arm/atomic-op-int.c: Rename into ...
> > * gcc.target/arm/atomic-op-int-1.c: This.
> > * gcc.target/arm/atomic-op-relaxed.c: Rename into ...
> > * gcc.target/arm/atomic-op-relaxed-1.c: This.
> > * gcc.target/arm/atomic-op-release.c: Rename into ...
> > * gcc.target/arm/atomic-op-release-1.c: This.
> > * gcc.target/arm/atomic-op-seq_cst.c: Rename into ...
> > * gcc.target/arm/atomic-op-seq_cst-1.c: This.
> > * gcc.target/arm/atomic-op-short.c: Rename into ...
> > * gcc.target/arm/atomic-op-short-1.c: This.
> > * gcc.target/arm/atomic-comp-swap-release-acquire-2.c: New test.
> > * gcc.target/arm/atomic-op-acq_rel-2.c: Likewise.
> > * gcc.target/arm/atomic-op-acquire-2.c: Likewise.
> > * gcc.target/arm/atomic-op-char-2.c: Likewise.
> > * gcc.target/arm/atomic-op-consume-2.c: Likewise.
> > * gcc.target/arm/atomic-op-int-2.c: Likewise.
> > * gcc.target/arm/atomic-op-relaxed-2.c: Likewise.
> > * gcc.target/arm/atomic-op-release-2.c: Likewise.
> > * gcc.target/arm/atomic-op-seq_cst-2.c: Likewise.
> > * gcc.target/arm/atomic-op-short-2.c: Likewise.
> >
> > Testsuite shows no regression and atomic tests [1] are passing for ARMv8-M
> > Mainline.
> >
> > [1] gcc.dg/atomic*, g++.dg/ext/atomic*, gcc.target/arm/atomic*,
> > gcc.target/arm/sync* and libstdc++-v3/testsuite/29_atomic/*
>
> Thanks, this is ok if testing on arm-none-linux-gnueabihf is ok.
> In particular, please make sure that the tests still pass for an A-profile
> target.
Oh yes, I forgot to mention that I also tested the same tests for armv8-a
without any code generation change for both ARM and Thumb. The whole testsuite
shows no regression as well.
Best regards,
Thomas
^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2016-09-01 12:43 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2015-12-17 9:39 [PATCH, ARM 7/6] Enable atomics for ARMv8-M Mainline Thomas Preud'homme
2016-05-17 10:15 ` [PATCH, ARM 7/7, ping1] " Thomas Preudhomme
2016-05-19 16:18 ` Kyrill Tkachov
2016-05-19 16:48 ` Thomas Preudhomme
2016-07-14 13:38 ` [PATCH, ARM 7/7] " Thomas Preudhomme
2016-07-14 16:24 ` Kyrill Tkachov
2016-07-14 16:35 ` Thomas Preudhomme
2016-09-01 12:43 ` [arm-embedded] " Thomas Preudhomme
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for read-only IMAP folder(s) and NNTP newsgroup(s).