From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 97570 invoked by alias); 17 Dec 2015 09:39:36 -0000 Mailing-List: contact gcc-patches-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-patches-owner@gcc.gnu.org Received: (qmail 97524 invoked by uid 89); 17 Dec 2015 09:39:36 -0000 Authentication-Results: sourceware.org; auth=none X-Virus-Found: No X-Spam-SWARE-Status: No, score=2.1 required=5.0 tests=AWL,BAYES_50,KAM_LAZY_DOMAIN_SECURITY,T_RP_MATCHES_RCVD autolearn=no version=3.3.2 spammy=chip, UD:libgcov.a, libma, libnosysa X-HELO: foss.arm.com Received: from foss.arm.com (HELO foss.arm.com) (217.140.101.70) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Thu, 17 Dec 2015 09:39:35 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.72.51.249]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 9CD7A55D; Thu, 17 Dec 2015 01:39:09 -0800 (PST) Received: from SHAWIN202 (unknown [10.164.12.31]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 611333F21A; Thu, 17 Dec 2015 01:39:31 -0800 (PST) From: "Thomas Preud'homme" To: , "Richard Earnshaw" , "Ramana Radhakrishnan" , "Kyrylo Tkachov" Subject: [PATCH, ARM 7/6] Enable atomics for ARMv8-M Mainline Date: Thu, 17 Dec 2015 09:39:00 -0000 Message-ID: <006a01d138ae$d5014430$7f03cc90$@foss.arm.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-SW-Source: 2015-12/txt/msg01722.txt.bz2 Hi, This patch is part of a patch series to add support for ARMv8-M[1] to GCC. = This specific patch enable atomics for ARMv8-M Mainline. No change is neede= d to existing patterns since Thumb-2 backend can already handle them fine. [1] For a quick overview of ARMv8-M please refer to the initial cover lette= r. ChangeLog entries are as follow: *** gcc/ChangeLog *** 2015-12-17 Thomas Preud'homme * config/arm/arm.h (TARGET_HAVE_LDACQ): Enable for ARMv8-M Mainline. diff --git a/gcc/config/arm/arm.h b/gcc/config/arm/arm.h index 1f79c37b5c36a410a2d500ba92c62a5ba4ca1178..fa2a6fb03ffd2ca53bfb7e7c8f0= 3022b626880e0 100644 --- a/gcc/config/arm/arm.h +++ b/gcc/config/arm/arm.h @@ -258,7 +258,7 @@ extern void (*arm_lang_output_object_attributes_hook)(v= oid); || arm_arch7) && arm_arch_notm) =20 /* Nonzero if this chip supports load-acquire and store-release. */ -#define TARGET_HAVE_LDACQ (TARGET_ARM_ARCH >=3D 8 && arm_arch_notm) +#define TARGET_HAVE_LDACQ (TARGET_ARM_ARCH >=3D 8 && TARGET_32BIT) =20 /* Nonzero if this chip provides the movw and movt instructions. */ #define TARGET_HAVE_MOVT (arm_arch_thumb2 || arm_arch8) Testing: * Toolchain was built successfully with and without the ARMv8-M support pat= ches with the following multilib list: armv6-m,armv7-m,armv7e-m,cortex-m7. = The code generation for crtbegin.o, crtend.o, crti.o, crtn.o, libgcc.a, lib= gcov.a, libc.a, libg.a, libgloss-linux.a, libm.a, libnosys.a, librdimon.a, = librdpmon.a, libstdc++.a and libsupc++.a is unchanged for all these targets= .=20 * GCC also showed no testsuite regression when targeting ARMv8-M Baseline c= ompared to ARMv6-M on ARM Fast Models and when targeting ARMv6-M and ARMv7-= M (compared to without the patch) * GCC was bootstrapped successfully targeting Thumb-1 and targeting Thumb-2 Is this ok for stage3? Best regards, Thomas