From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from server.nextmovesoftware.com (server.nextmovesoftware.com [162.254.253.69]) by sourceware.org (Postfix) with ESMTPS id 807613857BA8 for ; Thu, 30 Jun 2022 10:56:31 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 807613857BA8 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=nextmovesoftware.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=nextmovesoftware.com DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=nextmovesoftware.com; s=default; h=Content-Type:MIME-Version:Message-ID: Date:Subject:Cc:To:From:Sender:Reply-To:Content-Transfer-Encoding:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:In-Reply-To:References:List-Id:List-Help:List-Unsubscribe: List-Subscribe:List-Post:List-Owner:List-Archive; bh=qY8X+/h7w2PU3G4QpUxnZg2T6GpkE1nFCa7iw7uUPTk=; b=FibtyHjZVrtwAU6MpQRMjMaFkf owITuJpLVDllUMRGVrMP0IXfJ7w6KaKLkQn9M02kusA+J8RD+TwlB8sRaMoUID0tsQbBwhn0TgGPa TJ0asjvIFgr4CjBkG58ofdrp54bxPfOdOINuHy/oM5RcNnZ7Qqark2n5O4Rz8QI2azwrtBAVNOK4S xTtgQW/OW67n2W8vIZfqd+rIy9/gOPe8BIX+yZrBSqebPmUenzsUGEOvaVic9FAOGV5z97r/83UX5 tIGu/BSf/s4M9ioMSfJ3BTm5ATZ3AxV2BIsNlurcEi0jzn8bbgTV68UNOXEym0qLDhwNyv/oMW4H4 bWJhw/wA==; Received: from host86-130-134-60.range86-130.btcentralplus.com ([86.130.134.60]:62634 helo=Dell) by server.nextmovesoftware.com with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1o6rqY-00062J-L7; Thu, 30 Jun 2022 06:56:30 -0400 From: "Roger Sayle" To: "'Uros Bizjak'" Cc: Subject: [x86 PATCH take #2] Double word logical operation clean-ups in i386.md. Date: Thu, 30 Jun 2022 11:56:26 +0100 Message-ID: <006b01d88c70$0dbc7530$29355f90$@nextmovesoftware.com> MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="----=_NextPart_000_006C_01D88C78.6F85BF30" X-Mailer: Microsoft Outlook 16.0 Thread-Index: AdiMasnwEWYHLMRaSR2ju8MOwFqSxQ== Content-Language: en-gb X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - server.nextmovesoftware.com X-AntiAbuse: Original Domain - gcc.gnu.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - nextmovesoftware.com X-Get-Message-Sender-Via: server.nextmovesoftware.com: authenticated_id: roger@nextmovesoftware.com X-Authenticated-Sender: server.nextmovesoftware.com: roger@nextmovesoftware.com X-Source: X-Source-Args: X-Source-Dir: X-Spam-Status: No, score=-10.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, MEDICAL_SUBJECT, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Thu, 30 Jun 2022 10:56:34 -0000 This is a multipart message in MIME format. ------=_NextPart_000_006C_01D88C78.6F85BF30 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Hi Uros, Many thanks for your review of the "double word logical operation = clean-up" patch. The revision below incorporates the majority of your feedback, but with = one or two exceptions (required to allow the patch to bootstrap) that I thought I'd = double check with you before pushing. Firstly, great catch that we no longer need to test rtx_equal = (operands[0], operands[1]) when moving a splitter from before reload to after reload, as this is = guaranteed by the "0" constraints. I've cleaned this up in all the doubleword splitters = (including the case that's now moved). Also, as you've suggested, this patch = uses a pair of define_insn_and_split for ANDN, one for TARGET_BMI (split = post-reload) and the other for !TARGET_BMI (that's lowered rather than split, = pre-load/post-STV). Unfortunately, the "force_reg of tricky immediate constants" checks = really are required for these expanders. I agree normally the predicate is = checked/guaranteed for a define_insn, but in this case the gen_iordi3 function and related = expanders are frequently called directly by the middle-end or from i386-expand, which = bypasses the checks made by the later RTL passes. When given arbitrary immediate = constants, this results in ICEs from insns not matching their predicates soon after = expand (breaking bootstrap with an ICE). It's only "standard name" expanders = that require this treatment, define_insn{_and_split} templates do enforce their = predicates. And finally, we can't/shouldn't use in the = actual doubleword splitters, as the mode being iterated over is DWIH (not DWI), where we require the predicate for the corresponding mode. It = turns out that it's always appropriate to use x86_64_hilo_general_operand = wherever we use the "r" constraint, and that's used consistently in this = patch. I hope these exceptions are acceptable. The attached revised patch has been tested on x86_64-pc-linux-gnu with make bootstrap and make -k check both with and with --target_board=3Dunix{-m32} with no new failures. Are these revisions OK for mainline? 2022-06-30 Roger Sayle Uro=C5=A1 Bizjak gcc/ChangeLog * config/i386/i386.md (general_szext_operand): Add TImode support using x86_64_hilo_general_operand predicate. (*cmp_doubleword): Use x86_64_hilo_general_operand = predicate. (*add3_doubleword): Improved optimization of zero addition. (and3): Use SDWIM mode iterator to add support for double word bit-wise AND in TImode. Use force_reg when double word immediate operand isn't x86_64_hilo_general_operand. (and3_doubleword): Generalized from anddi3_doubleword and converted into a post-reload splitter. (*andndi3_doubleword): Old define_insn deleted. (*andn3_doubleword_bmi): New define_insn_and_split for TARGET_BMI that splits post-reload. (*andn3_doubleword): New define_insn_and_split for !TARGET_BMI, that lowers/splits before reload. (3): Use SDWIM mode iterator to add suppport for double word bit-wise XOR and bit-wise IOR in TImode. Use force_reg when double word immediate operand isn't x86_64_hilo_general_operand. (*di3_doubleword): Generalized from = di3_doubleword. (one_cmpl2): Use SDWIM mode iterator to add support for double word bit-wise NOT in TImode. (one_cmpl2_doubleword): Generalize from = one_cmpldi2_doubleword and converted into a post-reload splitter. Thanks again, Roger -- > -----Original Message----- > From: Uros Bizjak > Sent: 28 June 2022 16:38 > To: Roger Sayle > Cc: gcc-patches@gcc.gnu.org > Subject: Re: [x86 PATCH] Double word logical operation clean-ups in = i386.md. >=20 > On Tue, Jun 28, 2022 at 1:34 PM Roger Sayle = > wrote: > > > > > > Hi Uros, > > As you've requested/suggested, here's a patch that tidies up and > > unifies doubleword handling in i386.md; converting all doubleword > > splitters for logic operations to post-reload form, generalizing = their > > define_insn_and_split templates to form (supporting = TARGET_64BIT > > ? TImode : DImode), and where required tweaking the corresponding > > expanders to use SDWIM to support TImode doubleword operations. = These > > changes incorporate your feedback from > > https://gcc.gnu.org/pipermail/gcc-patches/2022-June/596205.html > > where I included many/several of these clean-ups, in a patch to add = a > > new optimization. I agree, it's better to split these out (this > > patch), and I'll resubmit the (smaller) optimization patch as a > > follow-up. > > > > This patch has been tested on x86_64-pc-linux-gnu with make = bootstrap > > and make -k check, both with and without = --target_board=3Dunix{-m32}, > > with no new failures. Ok for mainline? > > > > > > 2022-06-28 Roger Sayle > > > > gcc/ChangeLog > > * config/i386/i386.md (general_szext_operand): Add TImode > > support using x86_64_hilo_general_operand predicate. > > (*cmp_doubleword): Use x86_64_hilo_general_operand = predicate. > > (*add3_doubleword): Improved optimization of zero = addition. > > (and3): Use SDWIM mode iterator to add support for = double > > word bit-wise AND in TImode. Use force_reg when double word > > immediate operand isn't x86_64_hilo_general_operand. > > (and3_doubleword): Generalized from anddi3_doubleword = and > > converted into a post-reload splitter. > > (*andn3_doubleword): Generalized from = *andndi3_doubleword. > > (define_split): Generalize DImode splitters for andn to = . > > One splitter for TARGET_BMI, the other for !TARGET_BMI. > > (3): Use SDWIM mode iterator to add suppport = for > > double word bit-wise XOR and bit-wise IOR in TImode. Use > > force_reg when double word immediate operand isn't > > x86_64_hilo_general_operand. > > (*di3_doubleword): Generalized from = di3_doubleword. > > (one_cmpl2): Use SDWIM mode iterator to add support = for > > double word bit-wise NOT in TImode. > > (one_cmpl2_doubleword): Generalize from > one_cmpldi2_doubleword > > and converted into a post-reload splitter. >=20 >=20 > (define_expand "and3" > - [(set (match_operand:SWIM1248x 0 "nonimmediate_operand") > - (and:SWIM1248x (match_operand:SWIM1248x 1 "nonimmediate_operand") > - (match_operand:SWIM1248x 2 = "")))] > + [(set (match_operand:SDWIM 0 "nonimmediate_operand") > + (and:SDWIM (match_operand:SDWIM 1 "nonimmediate_operand") > + (match_operand:SDWIM 2 "")))] > "" > { > machine_mode mode =3D mode; >=20 > - if (mode =3D=3D DImode && !TARGET_64BIT) > - ; > - else if (const_int_operand (operands[2], mode) > - && register_operand (operands[0], mode) > - && !(TARGET_ZERO_EXTEND_WITH_AND > - && optimize_function_for_speed_p (cfun))) > + if (GET_MODE_SIZE (mode) > UNITS_PER_WORD > + && !x86_64_hilo_general_operand (operands[2], mode)) > + operands[2] =3D force_reg (mode, operands[2]); >=20 > You don't have to do that - when the predicate can't be satisfied, the = middle-end > pushes the value to a register as a last resort by default. >=20 > + bool emit_insn_deleted_note_p =3D false; > + > + split_double_mode (mode, &operands[0], 3, &operands[0], > + &operands[3]); >=20 > if (operands[2] =3D=3D const0_rtx) > emit_move_insn (operands[0], const0_rtx); > else if (operands[2] =3D=3D constm1_rtx) > - emit_move_insn (operands[0], operands[1]); > + { > + if (!rtx_equal_p (operands[0], operands[1])) > + emit_move_insn (operands[0], operands[1]); > + else > + emit_insn_deleted_note_p =3D true; > + } >=20 > Please note that when operands[2] is an immediate, constraints after = reload > *guarantee* that operands[1] match operands[0]. So, the insn should = always be > deleted (I think that this functionality was in your patch - = it is > unneeded there, too). >=20 > +(define_insn "*andn3_doubleword" > + [(set (match_operand:DWI 0 "register_operand") > + (and:DWI > + (not:DWI (match_operand:DWI 1 "register_operand")) > + (match_operand:DWI 2 "nonimmediate_operand"))) > (clobber (reg:CC FLAGS_REG))] > - "!TARGET_64BIT && TARGET_STV && TARGET_SSE2 > - && ix86_pre_reload_split ()" > + "ix86_pre_reload_split ()" > "#") >=20 > Please introduce two ANDN double-word insn-and-split patterns, one for = BMI > and one for !BMI. The one for BMI should be moved to a post-reload = splitter, > too. As we figured out, *all* double-word patterns should either be of = pre- > reload or of post-reload type. >=20 > (define_split > - [(set (match_operand:DI 0 "register_operand") > - (and:DI > - (not:DI (match_operand:DI 1 "register_operand")) > - (match_operand:DI 2 "nonimmediate_operand"))) > + [(set (match_operand:DWI 0 "register_operand") > + (and:DWI > + (not:DWI (match_operand:DWI 1 "register_operand")) > + (match_operand:DWI 2 "nonimmediate_operand"))) > (clobber (reg:CC FLAGS_REG))] > - "!TARGET_64BIT && !TARGET_BMI && TARGET_STV && TARGET_SSE2 > + "!TARGET_BMI >=20 > Without BMI, the ANDN should be split to a double-word NOT + AND = before > reload (and these two insns are split to single-word operations after = reload). > This simplifies splitting logic quite a bit. >=20 > (define_expand "3" > - [(set (match_operand:SWIM1248x 0 "nonimmediate_operand") > - (any_or:SWIM1248x (match_operand:SWIM1248x 1 > "nonimmediate_operand") > - (match_operand:SWIM1248x 2 "")))] > + [(set (match_operand:SDWIM 0 "nonimmediate_operand") > + (any_or:SDWIM (match_operand:SDWIM 1 "nonimmediate_operand") > + (match_operand:SDWIM 2 "")))] >=20 > Use here ... >=20 > "" > - "ix86_expand_binary_operator (, mode, operands); = DONE;") > +{ >=20 > -(define_insn_and_split "*di3_doubleword" > - [(set (match_operand:DI 0 "nonimmediate_operand" "=3Dro,r") > - (any_or:DI > - (match_operand:DI 1 "nonimmediate_operand" "0,0") > - (match_operand:DI 2 "x86_64_szext_general_operand" "re,o"))) > + if (GET_MODE_SIZE (mode) > UNITS_PER_WORD > + && !x86_64_hilo_general_operand (operands[2], mode)) > + operands[2] =3D force_reg (mode, operands[2]); >=20 > ... to avoid the above fixup. >=20 > +(define_insn_and_split "*3_doubleword" > + [(set (match_operand: 0 "nonimmediate_operand" "=3Dro,r") > + (any_or: > + (match_operand: 1 "nonimmediate_operand" "%0,0") > + (match_operand: 2 "x86_64_hilo_general_operand" = "r,o"))) >=20 > for consistency. >=20 > Otherwise OK. >=20 > Uros. ------=_NextPart_000_006C_01D88C78.6F85BF30 Content-Type: text/plain; name="patchdw2.txt" Content-Transfer-Encoding: quoted-printable Content-Disposition: attachment; filename="patchdw2.txt" diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md=0A= index 125a3b4..3947b05 100644=0A= --- a/gcc/config/i386/i386.md=0A= +++ b/gcc/config/i386/i386.md=0A= @@ -1192,7 +1192,8 @@=0A= [(QI "general_operand")=0A= (HI "general_operand")=0A= (SI "x86_64_szext_general_operand")=0A= - (DI "x86_64_szext_general_operand")])=0A= + (DI "x86_64_szext_general_operand")=0A= + (TI "x86_64_hilo_general_operand")])=0A= =0A= (define_mode_attr nonmemory_szext_operand=0A= [(QI "nonmemory_operand")=0A= @@ -1509,7 +1510,7 @@=0A= (define_insn_and_split "*cmp_doubleword"=0A= [(set (reg:CCZ FLAGS_REG)=0A= (compare:CCZ (match_operand: 0 "nonimmediate_operand")=0A= - (match_operand: 1 "x86_64_general_operand")))]=0A= + (match_operand: 1 "x86_64_hilo_general_operand")))]=0A= "ix86_pre_reload_split ()"=0A= "#"=0A= "&& 1"=0A= @@ -5802,7 +5803,12 @@=0A= split_double_mode (mode, &operands[0], 3, &operands[0], = &operands[3]);=0A= if (operands[2] =3D=3D const0_rtx)=0A= {=0A= - ix86_expand_binary_operator (PLUS, mode, &operands[3]);=0A= + if (operands[5] !=3D const0_rtx)=0A= + ix86_expand_binary_operator (PLUS, mode, &operands[3]);=0A= + else if (!rtx_equal_p (operands[3], operands[4]))=0A= + emit_move_insn (operands[3], operands[4]);=0A= + else=0A= + emit_note (NOTE_INSN_DELETED);=0A= DONE;=0A= }=0A= })=0A= @@ -9846,19 +9852,22 @@=0A= ;; it should be done with splitters.=0A= =0A= (define_expand "and3"=0A= - [(set (match_operand:SWIM1248x 0 "nonimmediate_operand")=0A= - (and:SWIM1248x (match_operand:SWIM1248x 1 "nonimmediate_operand")=0A= - (match_operand:SWIM1248x 2 "")))]=0A= + [(set (match_operand:SDWIM 0 "nonimmediate_operand")=0A= + (and:SDWIM (match_operand:SDWIM 1 "nonimmediate_operand")=0A= + (match_operand:SDWIM 2 "")))]=0A= ""=0A= {=0A= machine_mode mode =3D mode;=0A= =0A= - if (mode =3D=3D DImode && !TARGET_64BIT)=0A= - ;=0A= - else if (const_int_operand (operands[2], mode)=0A= - && register_operand (operands[0], mode)=0A= - && !(TARGET_ZERO_EXTEND_WITH_AND=0A= - && optimize_function_for_speed_p (cfun)))=0A= + if (GET_MODE_SIZE (mode) > UNITS_PER_WORD=0A= + && !x86_64_hilo_general_operand (operands[2], mode))=0A= + operands[2] =3D force_reg (mode, operands[2]);=0A= +=0A= + if (GET_MODE_SIZE (mode) <=3D UNITS_PER_WORD=0A= + && const_int_operand (operands[2], mode)=0A= + && register_operand (operands[0], mode)=0A= + && !(TARGET_ZERO_EXTEND_WITH_AND=0A= + && optimize_function_for_speed_p (cfun)))=0A= {=0A= unsigned HOST_WIDE_INT ival =3D UINTVAL (operands[2]);=0A= =0A= @@ -9880,34 +9889,37 @@=0A= DONE;=0A= })=0A= =0A= -(define_insn_and_split "*anddi3_doubleword"=0A= - [(set (match_operand:DI 0 "nonimmediate_operand")=0A= - (and:DI=0A= - (match_operand:DI 1 "nonimmediate_operand")=0A= - (match_operand:DI 2 "x86_64_szext_general_operand")))=0A= +(define_insn_and_split "*and3_doubleword"=0A= + [(set (match_operand: 0 "nonimmediate_operand" "=3Dro,r")=0A= + (and:=0A= + (match_operand: 1 "nonimmediate_operand" "%0,0")=0A= + (match_operand: 2 "x86_64_hilo_general_operand" "r,o")))=0A= (clobber (reg:CC FLAGS_REG))]=0A= - "!TARGET_64BIT=0A= - && ix86_binary_operator_ok (AND, DImode, operands)=0A= - && ix86_pre_reload_split ()"=0A= + "ix86_binary_operator_ok (AND, mode, operands)"=0A= "#"=0A= - "&& 1"=0A= - [(const_int 0)]=0A= + "&& reload_completed"=0A= + [(const_int:DWIH 0)]=0A= {=0A= - split_double_mode (DImode, &operands[0], 3, &operands[0], = &operands[3]);=0A= + bool emit_insn_deleted_note_p =3D false;=0A= +=0A= + split_double_mode (mode, &operands[0], 3, &operands[0], = &operands[3]);=0A= =0A= if (operands[2] =3D=3D const0_rtx)=0A= emit_move_insn (operands[0], const0_rtx);=0A= else if (operands[2] =3D=3D constm1_rtx)=0A= - emit_move_insn (operands[0], operands[1]);=0A= + emit_insn_deleted_note_p =3D true;=0A= else=0A= - emit_insn (gen_andsi3 (operands[0], operands[1], operands[2]));=0A= + ix86_expand_binary_operator (AND, mode, &operands[0]);=0A= =0A= if (operands[5] =3D=3D const0_rtx)=0A= emit_move_insn (operands[3], const0_rtx);=0A= else if (operands[5] =3D=3D constm1_rtx)=0A= - emit_move_insn (operands[3], operands[4]);=0A= + {=0A= + if (emit_insn_deleted_note_p)=0A= + emit_note (NOTE_INSN_DELETED);=0A= + }=0A= else=0A= - emit_insn (gen_andsi3 (operands[3], operands[4], operands[5]));=0A= + ix86_expand_binary_operator (AND, mode, &operands[3]);=0A= =0A= DONE;=0A= })=0A= @@ -10391,54 +10403,38 @@=0A= operands[2] =3D gen_int_mode (INTVAL (operands[2]), QImode);=0A= })=0A= =0A= -(define_insn "*andndi3_doubleword"=0A= - [(set (match_operand:DI 0 "register_operand")=0A= - (and:DI=0A= - (not:DI (match_operand:DI 1 "register_operand"))=0A= - (match_operand:DI 2 "nonimmediate_operand")))=0A= - (clobber (reg:CC FLAGS_REG))]=0A= - "!TARGET_64BIT && TARGET_STV && TARGET_SSE2=0A= - && ix86_pre_reload_split ()"=0A= - "#")=0A= -=0A= -(define_split=0A= - [(set (match_operand:DI 0 "register_operand")=0A= - (and:DI=0A= - (not:DI (match_operand:DI 1 "register_operand"))=0A= - (match_operand:DI 2 "nonimmediate_operand")))=0A= +(define_insn_and_split "*andn3_doubleword_bmi"=0A= + [(set (match_operand: 0 "register_operand")=0A= + (and:=0A= + (not: (match_operand: 1 "register_operand"))=0A= + (match_operand: 2 "nonimmediate_operand")))=0A= (clobber (reg:CC FLAGS_REG))]=0A= - "!TARGET_64BIT && TARGET_BMI && TARGET_STV && TARGET_SSE2=0A= - && can_create_pseudo_p ()"=0A= + "TARGET_BMI"=0A= + "#"=0A= + "&& reload_completed"=0A= [(parallel [(set (match_dup 0)=0A= - (and:SI (not:SI (match_dup 1)) (match_dup 2)))=0A= + (and:DWIH (not:DWIH (match_dup 1)) (match_dup 2)))=0A= (clobber (reg:CC FLAGS_REG))])=0A= (parallel [(set (match_dup 3)=0A= - (and:SI (not:SI (match_dup 4)) (match_dup 5)))=0A= + (and:DWIH (not:DWIH (match_dup 4)) (match_dup 5)))=0A= (clobber (reg:CC FLAGS_REG))])]=0A= - "split_double_mode (DImode, &operands[0], 3, &operands[0], = &operands[3]);")=0A= + "split_double_mode (mode, &operands[0], 3, &operands[0], = &operands[3]);")=0A= =0A= -(define_split=0A= - [(set (match_operand:DI 0 "register_operand")=0A= - (and:DI=0A= - (not:DI (match_operand:DI 1 "register_operand"))=0A= - (match_operand:DI 2 "nonimmediate_operand")))=0A= +(define_insn_and_split "*andn3_doubleword"=0A= + [(set (match_operand:DWI 0 "register_operand")=0A= + (and:DWI=0A= + (not:DWI (match_operand:DWI 1 "register_operand"))=0A= + (match_operand:DWI 2 "nonimmediate_operand")))=0A= (clobber (reg:CC FLAGS_REG))]=0A= - "!TARGET_64BIT && !TARGET_BMI && TARGET_STV && TARGET_SSE2=0A= - && can_create_pseudo_p ()"=0A= - [(set (match_dup 6) (not:SI (match_dup 1)))=0A= + "!TARGET_BMI=0A= + && ix86_pre_reload_split ()"=0A= + "#"=0A= + "&& 1"=0A= + [(set (match_dup 3) (not:DWI (match_dup 1)))=0A= (parallel [(set (match_dup 0)=0A= - (and:SI (match_dup 6) (match_dup 2)))=0A= - (clobber (reg:CC FLAGS_REG))])=0A= - (set (match_dup 7) (not:SI (match_dup 4)))=0A= - (parallel [(set (match_dup 3)=0A= - (and:SI (match_dup 7) (match_dup 5)))=0A= + (and:DWI (match_dup 3) (match_dup 2)))=0A= (clobber (reg:CC FLAGS_REG))])]=0A= -{=0A= - operands[6] =3D gen_reg_rtx (SImode);=0A= - operands[7] =3D gen_reg_rtx (SImode);=0A= -=0A= - split_double_mode (DImode, &operands[0], 3, &operands[0], = &operands[3]);=0A= -})=0A= + "operands[3] =3D gen_reg_rtx (mode);")=0A= =0A= (define_insn "*andn_1"=0A= [(set (match_operand:SWI48 0 "register_operand" "=3Dr,r,?k")=0A= @@ -10532,52 +10528,51 @@=0A= ;; If this is considered useful, it should be done with splitters.=0A= =0A= (define_expand "3"=0A= - [(set (match_operand:SWIM1248x 0 "nonimmediate_operand")=0A= - (any_or:SWIM1248x (match_operand:SWIM1248x 1 "nonimmediate_operand")=0A= - (match_operand:SWIM1248x 2 "")))]=0A= + [(set (match_operand:SDWIM 0 "nonimmediate_operand")=0A= + (any_or:SDWIM (match_operand:SDWIM 1 "nonimmediate_operand")=0A= + (match_operand:SDWIM 2 "")))]=0A= ""=0A= - "ix86_expand_binary_operator (, mode, operands); DONE;")=0A= +{=0A= + if (GET_MODE_SIZE (mode) > UNITS_PER_WORD=0A= + && !x86_64_hilo_general_operand (operands[2], mode))=0A= + operands[2] =3D force_reg (mode, operands[2]);=0A= =0A= -(define_insn_and_split "*di3_doubleword"=0A= - [(set (match_operand:DI 0 "nonimmediate_operand" "=3Dro,r")=0A= - (any_or:DI=0A= - (match_operand:DI 1 "nonimmediate_operand" "0,0")=0A= - (match_operand:DI 2 "x86_64_szext_general_operand" "re,o")))=0A= + ix86_expand_binary_operator (, mode, operands);=0A= + DONE;=0A= +})=0A= +=0A= +(define_insn_and_split "*3_doubleword"=0A= + [(set (match_operand: 0 "nonimmediate_operand" "=3Dro,r")=0A= + (any_or:=0A= + (match_operand: 1 "nonimmediate_operand" "%0,0")=0A= + (match_operand: 2 "x86_64_hilo_general_operand" "r,o")))=0A= (clobber (reg:CC FLAGS_REG))]=0A= - "!TARGET_64BIT=0A= - && ix86_binary_operator_ok (, DImode, operands)"=0A= + "ix86_binary_operator_ok (, mode, operands)"=0A= "#"=0A= "&& reload_completed"=0A= - [(const_int 0)]=0A= + [(const_int:DWIH 0)]=0A= {=0A= /* This insn may disappear completely when operands[2] =3D=3D = const0_rtx=0A= and operands[0] =3D=3D operands[1], which requires a = NOTE_INSN_DELETED. */=0A= bool emit_insn_deleted_note_p =3D false;=0A= =0A= - split_double_mode (DImode, &operands[0], 3, &operands[0], = &operands[3]);=0A= + split_double_mode (mode, &operands[0], 3, &operands[0], = &operands[3]);=0A= =0A= if (operands[2] =3D=3D const0_rtx)=0A= - {=0A= - if (!rtx_equal_p (operands[0], operands[1]))=0A= - emit_move_insn (operands[0], operands[1]);=0A= - else=0A= - emit_insn_deleted_note_p =3D true;=0A= - }=0A= + emit_insn_deleted_note_p =3D true;=0A= else if (operands[2] =3D=3D constm1_rtx)=0A= {=0A= if ( =3D=3D IOR)=0A= emit_move_insn (operands[0], constm1_rtx);=0A= else=0A= - ix86_expand_unary_operator (NOT, SImode, &operands[0]);=0A= + ix86_expand_unary_operator (NOT, mode, &operands[0]);=0A= }=0A= else=0A= - ix86_expand_binary_operator (, SImode, &operands[0]);=0A= + ix86_expand_binary_operator (, mode, &operands[0]);=0A= =0A= if (operands[5] =3D=3D const0_rtx)=0A= {=0A= - if (!rtx_equal_p (operands[3], operands[4]))=0A= - emit_move_insn (operands[3], operands[4]);=0A= - else if (emit_insn_deleted_note_p)=0A= + if (emit_insn_deleted_note_p)=0A= emit_note (NOTE_INSN_DELETED);=0A= }=0A= else if (operands[5] =3D=3D constm1_rtx)=0A= @@ -10585,10 +10580,10 @@=0A= if ( =3D=3D IOR)=0A= emit_move_insn (operands[3], constm1_rtx);=0A= else=0A= - ix86_expand_unary_operator (NOT, SImode, &operands[3]);=0A= + ix86_expand_unary_operator (NOT, mode, &operands[3]);=0A= }=0A= else=0A= - ix86_expand_binary_operator (, SImode, &operands[3]);=0A= + ix86_expand_binary_operator (, mode, &operands[3]);=0A= =0A= DONE;=0A= })=0A= @@ -11727,24 +11722,22 @@=0A= ;; One complement instructions=0A= =0A= (define_expand "one_cmpl2"=0A= - [(set (match_operand:SWIM1248x 0 "nonimmediate_operand")=0A= - (not:SWIM1248x (match_operand:SWIM1248x 1 "nonimmediate_operand")))]=0A= + [(set (match_operand:SDWIM 0 "nonimmediate_operand")=0A= + (not:SDWIM (match_operand:SDWIM 1 "nonimmediate_operand")))]=0A= ""=0A= "ix86_expand_unary_operator (NOT, mode, operands); DONE;")=0A= =0A= -(define_insn_and_split "*one_cmpldi2_doubleword"=0A= - [(set (match_operand:DI 0 "nonimmediate_operand")=0A= - (not:DI (match_operand:DI 1 "nonimmediate_operand")))]=0A= - "!TARGET_64BIT=0A= - && ix86_unary_operator_ok (NOT, DImode, operands)=0A= - && ix86_pre_reload_split ()"=0A= +(define_insn_and_split "*one_cmpl2_doubleword"=0A= + [(set (match_operand: 0 "nonimmediate_operand" "=3Dro")=0A= + (not: (match_operand: 1 "nonimmediate_operand" "0")))]=0A= + "ix86_unary_operator_ok (NOT, mode, operands)"=0A= "#"=0A= - "&& 1"=0A= + "&& reload_completed"=0A= [(set (match_dup 0)=0A= - (not:SI (match_dup 1)))=0A= + (not:DWIH (match_dup 1)))=0A= (set (match_dup 2)=0A= - (not:SI (match_dup 3)))]=0A= - "split_double_mode (DImode, &operands[0], 2, &operands[0], = &operands[2]);")=0A= + (not:DWIH (match_dup 3)))]=0A= + "split_double_mode (mode, &operands[0], 2, &operands[0], = &operands[2]);")=0A= =0A= (define_insn "*one_cmpl2_1"=0A= [(set (match_operand:SWI248 0 "nonimmediate_operand" "=3Drm,?k")=0A= ------=_NextPart_000_006C_01D88C78.6F85BF30--