From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from eggs.gnu.org (eggs.gnu.org [IPv6:2001:470:142:3::10]) by sourceware.org (Postfix) with ESMTPS id 39F353858CDB for ; Wed, 3 Apr 2024 01:48:32 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 39F353858CDB Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: sourceware.org; spf=fail smtp.mailfrom=loongson.cn ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 39F353858CDB Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=2001:470:142:3::10 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1712108915; cv=none; b=FeIQLUM41dj0C2yVfthDI/d4LuhBFgg9HeSGN+ZoYN5ERPP0rGaTIy09yohGGV55cySa1kU9IzYdIPTZ01dXqoEXsQuKi2JWx1HtPg+AcApXQeW+Qw5ILy40bPSRsbtTlzPDh9jDq9xQDBy3jXRS69aB+OoHEU60UGKI8HtwFns= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1712108915; c=relaxed/simple; bh=nlSxT28RENX4JvCogQEeXAl7BWY7U+TjWG62ZF5Du/k=; h=Subject:To:From:Message-ID:Date:MIME-Version; b=EvaU+hcC0z6nT0L+ZBLjBJFYgyVYZsvA9lro1sKE9tgOsuYJT2II/jTZNhSTKzkywwLpEmMB4/FZoIJGBex0as8o16ClQpvV5NpL7Hyes9sjVQKKV+2f9n0E7jQunJahhcmPb71LLMW69oS/68aOX0g37q+dgj1PpIXo4L7Gb/s= ARC-Authentication-Results: i=1; server2.sourceware.org Received: from mail.loongson.cn ([114.242.206.163]) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1rrpjo-000245-PZ for gcc-patches@gcc.gnu.org; Tue, 02 Apr 2024 21:48:31 -0400 Received: from loongson.cn (unknown [10.20.4.107]) by gateway (Coremail) with SMTP id _____8AxjutgtQxmH5oiAA--.13710S3; Wed, 03 Apr 2024 09:48:16 +0800 (CST) Received: from [10.20.4.107] (unknown [10.20.4.107]) by localhost.localdomain (Coremail) with SMTP id AQAAf8BxXRNftQxmaylyAA--.24538S3; Wed, 03 Apr 2024 09:48:15 +0800 (CST) Subject: Re:[pushed] [PATCH] LoongArch: Remove unused code To: Jiahao Xu , gcc-patches@gcc.gnu.org Cc: xry111@xry111.site, i@xen0n.name, xuchenghua@loongson.cn References: <20240402063330.65347-1-xujiahao@loongson.cn> From: Lulu Cheng Message-ID: <00b0334f-ddc4-0f6e-0060-607d84addda5@loongson.cn> Date: Wed, 3 Apr 2024 09:48:15 +0800 User-Agent: Mozilla/5.0 (X11; Linux loongarch64; rv:68.0) Gecko/20100101 Thunderbird/68.7.0 MIME-Version: 1.0 In-Reply-To: <20240402063330.65347-1-xujiahao@loongson.cn> Content-Type: text/plain; charset=gbk; format=flowed Content-Transfer-Encoding: 8bit Content-Language: en-US X-CM-TRANSID:AQAAf8BxXRNftQxmaylyAA--.24538S3 X-CM-SenderInfo: xfkh0wpoxo3qxorr0wxvrqhubq/ X-Coremail-Antispam: 1Uk129KBj93XoW3Zr45WF4UuF17tw17tr1rZrc_yoWkuFy8p3 9ru3Z7Jr48Jrn2g3Wktay5Xw4qyr17Ka12vF9xJ39rCry7Ww1qqa4Fkr9IqFyYvw1Sg3yj qa18Za15Way5KwcCm3ZEXasCq-sJn29KB7ZKAUJUUUU8529EdanIXcx71UUUUU7KY7ZEXa sCq-sGcSsGvfJ3Ic02F40EFcxC0VAKzVAqx4xG6I80ebIjqfuFe4nvWSU5nxnvy29KBjDU 0xBIdaVrnRJUUUv0b4IE77IF4wAFF20E14v26r1j6r4UM7CY07I20VC2zVCF04k26cxKx2 IYs7xG6rWj6s0DM7CIcVAFz4kK6r1Y6r17M28lY4IEw2IIxxk0rwA2F7IY1VAKz4vEj48v e4kI8wA2z4x0Y4vE2Ix0cI8IcVAFwI0_JFI_Gr1l84ACjcxK6xIIjxv20xvEc7CjxVAFwI 0_Gr0_Cr1l84ACjcxK6I8E87Iv67AKxVW8JVWxJwA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_ Gr0_Gr1UM2AIxVAIcxkEcVAq07x20xvEncxIr21l57IF6xkI12xvs2x26I8E6xACxx1l5I 8CrVACY4xI64kE6c02F40Ex7xfMcIj6xIIjxv20xvE14v26r106r15McIj6I8E87Iv67AK xVWUJVW8JwAm72CE4IkC6x0Yz7v_Jr0_Gr1lF7xvr2IY64vIr41lc7I2V7IY0VAS07AlzV AYIcxG8wCF04k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F40E 14v26r1j6r18MI8I3I0E7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_JF0_Jw1lIx kGc2Ij64vIr41lIxAIcVC0I7IYx2IY67AKxVWUJVWUCwCI42IY6xIIjxv20xvEc7CjxVAF wI0_Jr0_Gr1lIxAIcVCF04k26cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r1j6r 4UMIIF0xvEx4A2jsIEc7CjxVAFwI0_Jr0_GrUvcSsGvfC2KfnxnUUI43ZEXa7IU8j-e5UU UUU== Received-SPF: pass client-ip=114.242.206.163; envelope-from=chenglulu@loongson.cn; helo=mail.loongson.cn X-Spam_score_int: 2 X-Spam_score: 0.2 X-Spam_bar: / X-Spam_report: (0.2 / 5.0 requ) BAYES_00=-1.9,MIME_CHARSET_FARAWAY=2.45,NICE_REPLY_A=-0.376,SPF_HELO_NONE=0.001,SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-Spam-Status: No, score=-10.7 required=5.0 tests=BAYES_00,GIT_PATCH_0,KAM_DMARC_STATUS,KAM_SHORT,MIME_CHARSET_FARAWAY,NICE_REPLY_A,SPF_FAIL,SPF_HELO_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: Pushed to r14-9766. ÔÚ 2024/4/2 ÏÂÎç2:33, Jiahao Xu дµÀ: > For machines that satisfy ISA_HAS_LSX && !TARGET_64BIT, we will not support them now > and in the future, so this patch removes these unused code. > > gcc/ChangeLog: > > * config/loongarch/lasx.md: Remove unused code. > * config/loongarch/loongarch-protos.h (loongarch_split_lsx_copy_d): Remove. > (loongarch_split_lsx_insert_d): Ditto. > (loongarch_split_lsx_fill_d): Ditto. > * config/loongarch/loongarch.cc (loongarch_split_lsx_copy_d): Ditto. > (loongarch_split_lsx_insert_d): Ditto. > (loongarch_split_lsx_fill_d): Ditto. > * config/loongarch/lsx.md (lsx_vpickve2gr_du): Remove splitter. > (lsx_vpickve2gr_): Ditto. > (abs2): Remove expander. > (vabs2): Rename to abs2. > > gcc/testsuite/ChangeLog: > > * gcc.target/loongarch/vector/lsx/lsx-abs.c: New test. > --- > gcc/config/loongarch/lasx.md | 12 +-- > gcc/config/loongarch/loongarch-protos.h | 3 - > gcc/config/loongarch/loongarch.cc | 76 ---------------- > gcc/config/loongarch/lsx.md | 89 ++----------------- > .../gcc.target/loongarch/vector/lsx/lsx-abs.c | 26 ++++++ > 5 files changed, 35 insertions(+), 171 deletions(-) > create mode 100644 gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-abs.c > > diff --git a/gcc/config/loongarch/lasx.md b/gcc/config/loongarch/lasx.md > index 2fa5e46c8e8..7bd61f8ed5b 100644 > --- a/gcc/config/loongarch/lasx.md > +++ b/gcc/config/loongarch/lasx.md > @@ -572,12 +572,7 @@ (define_insn "lasx_xvinsgr2vr_" > (match_operand 3 "const__operand" "")))] > "ISA_HAS_LASX" > { > -#if 0 > - if (!TARGET_64BIT && (mode == V4DImode || mode == V4DFmode)) > - return "#"; > - else > -#endif > - return "xvinsgr2vr.\t%u0,%z1,%y3"; > + return "xvinsgr2vr.\t%u0,%z1,%y3"; > } > [(set_attr "type" "simd_insert") > (set_attr "mode" "")]) > @@ -1446,10 +1441,7 @@ (define_insn "lasx_xvreplgr2vr_" > if (which_alternative == 1) > return "xvldi.b\t%u0,0" ; > > - if (!TARGET_64BIT && (mode == V2DImode || mode == V2DFmode)) > - return "#"; > - else > - return "xvreplgr2vr.\t%u0,%z1"; > + return "xvreplgr2vr.\t%u0,%z1"; > } > [(set_attr "type" "simd_fill") > (set_attr "mode" "") > diff --git a/gcc/config/loongarch/loongarch-protos.h b/gcc/config/loongarch/loongarch-protos.h > index e3ed2b912a5..e238d795a73 100644 > --- a/gcc/config/loongarch/loongarch-protos.h > +++ b/gcc/config/loongarch/loongarch-protos.h > @@ -89,9 +89,6 @@ extern void loongarch_split_128bit_move (rtx, rtx); > extern bool loongarch_split_128bit_move_p (rtx, rtx); > extern void loongarch_split_256bit_move (rtx, rtx); > extern bool loongarch_split_256bit_move_p (rtx, rtx); > -extern void loongarch_split_lsx_copy_d (rtx, rtx, rtx, rtx (*)(rtx, rtx, rtx)); > -extern void loongarch_split_lsx_insert_d (rtx, rtx, rtx, rtx); > -extern void loongarch_split_lsx_fill_d (rtx, rtx); > extern const char *loongarch_output_move (rtx, rtx); > #ifdef RTX_CODE > extern void loongarch_expand_scc (rtx *); > diff --git a/gcc/config/loongarch/loongarch.cc b/gcc/config/loongarch/loongarch.cc > index a69a203fbe6..8438cc64b0d 100644 > --- a/gcc/config/loongarch/loongarch.cc > +++ b/gcc/config/loongarch/loongarch.cc > @@ -4756,82 +4756,6 @@ loongarch_split_256bit_move (rtx dest, rtx src) > } > } > > - > -/* Split a COPY_S.D with operands DEST, SRC and INDEX. GEN is a function > - used to generate subregs. */ > - > -void > -loongarch_split_lsx_copy_d (rtx dest, rtx src, rtx index, > - rtx (*gen_fn)(rtx, rtx, rtx)) > -{ > - gcc_assert ((GET_MODE (src) == V2DImode && GET_MODE (dest) == DImode) > - || (GET_MODE (src) == V2DFmode && GET_MODE (dest) == DFmode)); > - > - /* Note that low is always from the lower index, and high is always > - from the higher index. */ > - rtx low = loongarch_subword (dest, false); > - rtx high = loongarch_subword (dest, true); > - rtx new_src = simplify_gen_subreg (V4SImode, src, GET_MODE (src), 0); > - > - emit_insn (gen_fn (low, new_src, GEN_INT (INTVAL (index) * 2))); > - emit_insn (gen_fn (high, new_src, GEN_INT (INTVAL (index) * 2 + 1))); > -} > - > -/* Split a INSERT.D with operand DEST, SRC1.INDEX and SRC2. */ > - > -void > -loongarch_split_lsx_insert_d (rtx dest, rtx src1, rtx index, rtx src2) > -{ > - int i; > - gcc_assert (GET_MODE (dest) == GET_MODE (src1)); > - gcc_assert ((GET_MODE (dest) == V2DImode > - && (GET_MODE (src2) == DImode || src2 == const0_rtx)) > - || (GET_MODE (dest) == V2DFmode && GET_MODE (src2) == DFmode)); > - > - /* Note that low is always from the lower index, and high is always > - from the higher index. */ > - rtx low = loongarch_subword (src2, false); > - rtx high = loongarch_subword (src2, true); > - rtx new_dest = simplify_gen_subreg (V4SImode, dest, GET_MODE (dest), 0); > - rtx new_src1 = simplify_gen_subreg (V4SImode, src1, GET_MODE (src1), 0); > - i = exact_log2 (INTVAL (index)); > - gcc_assert (i != -1); > - > - emit_insn (gen_lsx_vinsgr2vr_w (new_dest, low, new_src1, > - GEN_INT (1 << (i * 2)))); > - emit_insn (gen_lsx_vinsgr2vr_w (new_dest, high, new_dest, > - GEN_INT (1 << (i * 2 + 1)))); > -} > - > -/* Split FILL.D. */ > - > -void > -loongarch_split_lsx_fill_d (rtx dest, rtx src) > -{ > - gcc_assert ((GET_MODE (dest) == V2DImode > - && (GET_MODE (src) == DImode || src == const0_rtx)) > - || (GET_MODE (dest) == V2DFmode && GET_MODE (src) == DFmode)); > - > - /* Note that low is always from the lower index, and high is always > - from the higher index. */ > - rtx low, high; > - if (src == const0_rtx) > - { > - low = src; > - high = src; > - } > - else > - { > - low = loongarch_subword (src, false); > - high = loongarch_subword (src, true); > - } > - rtx new_dest = simplify_gen_subreg (V4SImode, dest, GET_MODE (dest), 0); > - emit_insn (gen_lsx_vreplgr2vr_w (new_dest, low)); > - emit_insn (gen_lsx_vinsgr2vr_w (new_dest, high, new_dest, GEN_INT (1 << 1))); > - emit_insn (gen_lsx_vinsgr2vr_w (new_dest, high, new_dest, GEN_INT (1 << 3))); > -} > - > - > /* Return the appropriate instructions to move SRC into DEST. Assume > that SRC is operand 1 and DEST is operand 0. */ > > diff --git a/gcc/config/loongarch/lsx.md b/gcc/config/loongarch/lsx.md > index 87d3e7c5d9f..454cda47876 100644 > --- a/gcc/config/loongarch/lsx.md > +++ b/gcc/config/loongarch/lsx.md > @@ -582,28 +582,11 @@ (define_insn "lsx_vinsgr2vr_" > (match_operand 3 "const__operand" "")))] > "ISA_HAS_LSX" > { > - if (!TARGET_64BIT && (mode == V2DImode || mode == V2DFmode)) > - return "#"; > - else > - return "vinsgr2vr.\t%w0,%z1,%y3"; > + return "vinsgr2vr.\t%w0,%z1,%y3"; > } > [(set_attr "type" "simd_insert") > (set_attr "mode" "")]) > > -(define_split > - [(set (match_operand:LSX_D 0 "register_operand") > - (vec_merge:LSX_D > - (vec_duplicate:LSX_D > - (match_operand: 1 "_operand")) > - (match_operand:LSX_D 2 "register_operand") > - (match_operand 3 "const__operand")))] > - "reload_completed && ISA_HAS_LSX && !TARGET_64BIT" > - [(const_int 0)] > -{ > - loongarch_split_lsx_insert_d (operands[0], operands[2], operands[3], operands[1]); > - DONE; > -}) > - > (define_insn "lsx_vextrins__internal" > [(set (match_operand:LSX 0 "register_operand" "=f") > (vec_merge:LSX > @@ -653,70 +636,26 @@ (define_insn "lsx_vpickve2gr_" > [(set_attr "type" "simd_copy") > (set_attr "mode" "")]) > > -(define_insn_and_split "lsx_vpickve2gr_du" > +(define_insn "lsx_vpickve2gr_du" > [(set (match_operand:DI 0 "register_operand" "=r") > (vec_select:DI > (match_operand:V2DI 1 "register_operand" "f") > (parallel [(match_operand 2 "const_0_or_1_operand" "")])))] > "ISA_HAS_LSX" > -{ > - if (TARGET_64BIT) > - return "vpickve2gr.du\t%0,%w1,%2"; > - else > - return "#"; > -} > - "reload_completed && ISA_HAS_LSX && !TARGET_64BIT" > - [(const_int 0)] > -{ > - loongarch_split_lsx_copy_d (operands[0], operands[1], operands[2], > - gen_lsx_vpickve2gr_wu); > - DONE; > -} > + "vpickve2gr.du\t%0,%w1,%2" > [(set_attr "type" "simd_copy") > (set_attr "mode" "V2DI")]) > > -(define_insn_and_split "lsx_vpickve2gr_" > +(define_insn "lsx_vpickve2gr_" > [(set (match_operand: 0 "register_operand" "=r") > (vec_select: > (match_operand:LSX_D 1 "register_operand" "f") > (parallel [(match_operand 2 "const__operand" "")])))] > "ISA_HAS_LSX" > -{ > - if (TARGET_64BIT) > - return "vpickve2gr.\t%0,%w1,%2"; > - else > - return "#"; > -} > - "reload_completed && ISA_HAS_LSX && !TARGET_64BIT" > - [(const_int 0)] > -{ > - loongarch_split_lsx_copy_d (operands[0], operands[1], operands[2], > - gen_lsx_vpickve2gr_w); > - DONE; > -} > + "vpickve2gr.\t%0,%w1,%2" > [(set_attr "type" "simd_copy") > (set_attr "mode" "")]) > > - > -(define_expand "abs2" > - [(match_operand:ILSX 0 "register_operand" "=f") > - (abs:ILSX (match_operand:ILSX 1 "register_operand" "f"))] > - "ISA_HAS_LSX" > -{ > - if (ISA_HAS_LSX) > - { > - emit_insn (gen_vabs2 (operands[0], operands[1])); > - DONE; > - } > - else > - { > - rtx reg = gen_reg_rtx (mode); > - emit_move_insn (reg, CONST0_RTX (mode)); > - emit_insn (gen_lsx_vadda_ (operands[0], operands[1], reg)); > - DONE; > - } > -}) > - > (define_expand "neg2" > [(set (match_operand:ILSX 0 "register_operand") > (neg:ILSX (match_operand:ILSX 1 "register_operand")))] > @@ -1369,25 +1308,11 @@ (define_insn "lsx_vreplgr2vr_" > if (which_alternative == 1) > return "vldi.\t%w0,0"; > > - if (!TARGET_64BIT && (mode == V2DImode || mode == V2DFmode)) > - return "#"; > - else > - return "vreplgr2vr.\t%w0,%z1"; > + return "vreplgr2vr.\t%w0,%z1"; > } > [(set_attr "type" "simd_fill") > (set_attr "mode" "")]) > > -(define_split > - [(set (match_operand:LSX_D 0 "register_operand") > - (vec_duplicate:LSX_D > - (match_operand: 1 "register_operand")))] > - "reload_completed && ISA_HAS_LSX && !TARGET_64BIT" > - [(const_int 0)] > -{ > - loongarch_split_lsx_fill_d (operands[0], operands[1]); > - DONE; > -}) > - > (define_insn "logb2" > [(set (match_operand:FLSX 0 "register_operand" "=f") > (unspec:FLSX [(match_operand:FLSX 1 "register_operand" "f")] > @@ -2428,7 +2353,7 @@ (define_insn "vandn3" > [(set_attr "type" "simd_logic") > (set_attr "mode" "")]) > > -(define_insn "vabs2" > +(define_insn "abs2" > [(set (match_operand:ILSX 0 "register_operand" "=f") > (abs:ILSX (match_operand:ILSX 1 "register_operand" "f")))] > "ISA_HAS_LSX" > diff --git a/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-abs.c b/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-abs.c > new file mode 100644 > index 00000000000..cf971badb51 > --- /dev/null > +++ b/gcc/testsuite/gcc.target/loongarch/vector/lsx/lsx-abs.c > @@ -0,0 +1,26 @@ > +/* { dg-do compile } */ > +/* { dg-options "-O2 -mlsx" } */ > +/* { dg-final { scan-assembler-times "vsigncov.w" 1 } } */ > +/* { dg-final { scan-assembler-times "vsigncov.d" 1 } } */ > + > +int a[4], b[4]; > + > +extern int abs (int); > + > +void > +foo1 (void) > +{ > + for (int i = 0; i < 4; i++) > + a[i] = abs (b[i]); > +} > + > +long la[2], lb[2]; > + > +extern long labs (long); > + > +void > +foo2 (void) > +{ > + for (int i = 0; i < 2; i++) > + la[i] = labs (lb[i]); > +}