From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from server.nextmovesoftware.com (server.nextmovesoftware.com [162.254.253.69]) by sourceware.org (Postfix) with ESMTPS id 72DA83858C50 for ; Sun, 23 Apr 2023 10:38:11 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 72DA83858C50 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=nextmovesoftware.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=nextmovesoftware.com DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=nextmovesoftware.com; s=default; h=Content-Transfer-Encoding:Content-Type: MIME-Version:Message-ID:Date:Subject:In-Reply-To:References:To:From:Sender: Reply-To:Cc:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Id:List-Help: List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=6587d6ndM7R+vdBImdgTiRzJYpfJ2OpdIhK/JvC5R1I=; b=s7l7iUrpFWOnYFgI5hFN9/bOzD tEmXSwoKBiY/Yjm6uMxVW2ml3nnVV1iqe04xBJoc2Rj5eckkTOPMkwwjJSWTuA78j8iDhCdLTFH4J +u+SMHyG0URW3rV04AbsPNGL6E4ry7TdlqO/sUaoecNveYivly2PlODsOFlhgWQRaqXdGtDkV5D1C +yHEmbsh/lxYjPeGDhRC1ZURXD4LQs00wqKGmdYc0+0cnZ8BlpTzCK2oOFQ6in/7IpuRqfwDe5YSW QLHo2jCH4jklIFXzbpYSYcGf7fqI/EbDG8noHg8xNnORQdbfcawt3clVVY5CnC+/ch8fOx91hfHvs XEErf2YA==; Received: from host86-169-41-81.range86-169.btcentralplus.com ([86.169.41.81]:64230 helo=Dell) by server.nextmovesoftware.com with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.96) (envelope-from ) id 1pqX6g-0005oU-2S; Sun, 23 Apr 2023 06:38:10 -0400 From: "Roger Sayle" To: "'Jeff Law'" , "'GCC Patches'" References: <026001d9755d$19b30030$4d190090$@nextmovesoftware.com> In-Reply-To: Subject: RE: [xstormy16] Add extendhisi2 and zero_extendhisi2 patterns to stormy16.md Date: Sun, 23 Apr 2023 11:38:09 +0100 Message-ID: <00d901d975cf$b3643830$1a2ca890$@nextmovesoftware.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Mailer: Microsoft Outlook 16.0 Thread-Index: AQJvyjWYtZj/6ggeq+SpMQGj5/tLawLhKrRtrfTy31A= Content-Language: en-gb X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - server.nextmovesoftware.com X-AntiAbuse: Original Domain - gcc.gnu.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - nextmovesoftware.com X-Get-Message-Sender-Via: server.nextmovesoftware.com: authenticated_id: roger@nextmovesoftware.com X-Authenticated-Sender: server.nextmovesoftware.com: roger@nextmovesoftware.com X-Source: X-Source-Args: X-Source-Dir: X-Spam-Status: No, score=-0.8 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,KAM_SHORT,MEDICAL_SUBJECT,RCVD_IN_BARRACUDACENTRAL,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: On 4/33/23, Jeff Law wrote: > On 4/22/23 14:57, Roger Sayle wrote: > > Whilst there, I also fixed the instruction lengths and formatting of > > the zero_extendqihi2 pattern. Then, mostly for documentation = purposes > > as the 'T' constraint isn't yet implemented, I've added a "and = Rx,#255" > > alternative to zero_extendqihi2 that takes advantage of its = efficient > > instruction encoding. > > > > This patch has been tested by building a cross-compiler to > > xstormy16-elf on x86_64-pc-linux-gnu, and confirming that the new = test > > case passes with "make -k check-gcc". Ok for mainline? > > > > > > 2023-04-22 Roger Sayle > > > > gcc/ChangeLog > > * config/stormy16/stormy16.cc (xstormy16_print_operand): = Add %h > > format specifier to output high_part register name of = SImode reg. > > * config/stormy16/stormy16.md (extendhisi2): New = define_insn. > > (zero_extendqihi2): Fix lengths, consistent formatting and = add > > "and Rx,#255" alternative, for documentation purposes. > > (zero_extendhisi2): New define_insn. > > > > gcc/testsuite/ChangeLog > > * gcc.target/xstormy16/extendhisi2.c: New test case. > > * gcc.target/xstormy16/zextendhisi2.c: Likewise. > Does the "T" alternative ever match? AFAICT its constraint check = always > fails: >=20 > > (define_constraint "T" > > "@internal" > > ;; For Rx; not implemented yet. > > (match_test "0")) >=20 > No objections, but just not sure what's going on with that T = constraint. This is an interesting/cool artifact of the xstormy16 = architecture/instruction set that isn't yet (fully) supported in GCC, but much of the infrastructure = is in place. Instructions on xstormy16 are encoded by either one or two 16-bit words. If an immediate constant is between 0..15, arithmetic instructions can = be encoded in a single word, otherwise they require two words, with a full 16-bit immediate constant in the second word. The possibly unique = feature of xstormy is an "Rx" addressing mode, that can be used when the = destination register is the same destination as the previous instruction, which by = implicitly encoding DEST, allows 8-bit immediate constants, to be encoded in a = single word instruction. Handling this dependency between instructions is tricky, with Rx (aka = Rpsw) depending upon the N0..N3 bits in the flags register, and these bits being = modified/updated by almost every instruction. The 'T' constraint is a placeholder, that = currently always returns false but in theory allows the register allocator to = identify/select this alternative, and the psw_operand attribute on each instruction = indicating how it updates N0..N3 (DEST) bits in the processor status word (PSW). This feature is particularly useful for zero extension from QI to HI = mode. This normally requires a shl/shr sequence, but when the register being = extended was modified in the preceding instruction, the single word instruction "and = Rx,#255" can be used. Currently, for unsigned char foo(unsigned char x) { return ~x; } GCC -O2 generates: foo: not r2 shl r2,#8 | shr r2,#8 ret but more optimally could use: foo: not r2 // Rx now means r2 and Rx,#255 // shorter than and r2,#255 ret I doubt this functionality will be supported by the register allocator = and/or scheduler any time soon, but there's plenty that can be done with "macro = instructions", for example, a hypothetical "*onecmplqi_zexthi" which matches the above RTL, something (zero_extend:HI (not:QI (match_operand:QI = "register_operand")), could emit "not %0 | and Rx,#255". Presumably, the semantics of "Rx" are correctly supported by the = xstormy16 simulator? I hope this helps explain things (as I understand them). Thanks again for your help. Roger --