From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from server.nextmovesoftware.com (server.nextmovesoftware.com [162.254.253.69]) by sourceware.org (Postfix) with ESMTPS id 738D4383802D for ; Mon, 30 May 2022 10:06:20 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org 738D4383802D Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=nextmovesoftware.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=nextmovesoftware.com DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=nextmovesoftware.com; s=default; h=Content-Type:MIME-Version:Message-ID: Date:Subject:To:From:Sender:Reply-To:Cc:Content-Transfer-Encoding:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:In-Reply-To:References:List-Id:List-Help:List-Unsubscribe: List-Subscribe:List-Post:List-Owner:List-Archive; bh=fN8y1asz158AF2GsBg3OEkXZzhtmPEB4q2vGou8i9WI=; b=HmZEOvmR83VMNA79nJTmF4jKHL pAit/CZGsaSrkQ+qG+6bxZncInyjvjtcpw/DU19b46omcnWCAmnzt5VjkAhabOPwF66Q0ovz+Ab1Y KA/MS7z64Cqf5MYmXYRqgqx4LHEW8Qzy/rE7oKB+aejgOqc5zUcot+faUCo/DIf8xIZq6NT3kZ2vB Fn/lQ6LaSaoMTXFUz7UGULKjoDSMRMnHmx+JdCo8rAbvP0M63U8gw2M5HnKGLDAENU2q44j1cCEjq uP26BqzLr/ZckCyslYkJtvS9+KCBavnQhrJic3GBb2clTYBspw1sDD8CDs7SSuU9PGzJq3Qn72Fqn ZaCcLncw==; Received: from host109-154-46-241.range109-154.btcentralplus.com ([109.154.46.241]:57884 helo=Dell) by server.nextmovesoftware.com with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1nvcHz-00039q-OC for gcc-patches@gcc.gnu.org; Mon, 30 May 2022 06:06:19 -0400 From: "Roger Sayle" To: "'GCC Patches'" Subject: [PATCH] PR rtl-optimization/7061: Complex number arguments on x86_64-like ABIs. Date: Mon, 30 May 2022 11:06:16 +0100 Message-ID: <00e101d8740c$e785e110$b691a330$@nextmovesoftware.com> MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="----=_NextPart_000_00E2_01D87415.494C9300" X-Mailer: Microsoft Outlook 16.0 Thread-Index: Adh0DJwXN+ss6UwLQn6qeRoW02zEow== Content-Language: en-gb X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - server.nextmovesoftware.com X-AntiAbuse: Original Domain - gcc.gnu.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - nextmovesoftware.com X-Get-Message-Sender-Via: server.nextmovesoftware.com: authenticated_id: roger@nextmovesoftware.com X-Authenticated-Sender: server.nextmovesoftware.com: roger@nextmovesoftware.com X-Source: X-Source-Args: X-Source-Dir: X-Spam-Status: No, score=-12.4 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_SHORT, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 30 May 2022 10:06:22 -0000 This is a multipart message in MIME format. ------=_NextPart_000_00E2_01D87415.494C9300 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit This patch addresses the issue in comment #6 of PR rtl-optimization/7061 (a four digit PR number) from 2006 where on x86_64 complex number arguments are unconditionally spilled to the stack. For the test cases below: float re(float _Complex a) { return __real__ a; } float im(float _Complex a) { return __imag__ a; } GCC with -O2 currently generates: re: movq %xmm0, -8(%rsp) movss -8(%rsp), %xmm0 ret im: movq %xmm0, -8(%rsp) movss -4(%rsp), %xmm0 ret with this patch we now generate: re: ret im: movq %xmm0, %rax shrq $32, %rax movd %eax, %xmm0 ret [Technically, this shift can be performed on %xmm0 in a single instruction, but the backend needs to be taught to do that, the important bit is that the SCmode argument isn't written to the stack]. The patch itself is to emit_group_store where just before RTL expansion commits to writing to the stack, we check if the store group consists of a single scalar integer register that holds a complex mode value; on x86_64 SCmode arguments are passed in DImode registers. If this is the case, we can use a SUBREG to "view_convert" the integer to the equivalent complex mode. An interesting corner case that showed up during testing is that x86_64 also passes HCmode arguments in DImode registers(!), i.e. using modes of different sizes. This is easily handled/supported by first converting to an integer mode of the correct size, and then generating a complex mode SUBREG of this. This is similar in concept to the patch I proposed here: https://gcc.gnu.org/pipermail/gcc-patches/2022-February/590139.html which was almost (but not quite) approved here: https://gcc.gnu.org/pipermail/gcc-patches/2022-March/591139.html This patch has been tested on x86_64-pc-linux-gnu with make bootstrap and make -k check, both with and without --target_board=unix{-m32}, with no new failures. Ok for mainline? 2020-05-30 Roger Sayle gcc/ChangeLog PR rtl-optimization/7061 * expr.cc (emit_group_stote): For groups that consist of a single scalar integer register that hold a complex mode value, use gen_lowpart to generate a SUBREG to "view_convert" to the complex mode. For modes of different sizes, first convert to an integer mode of the appropriate size. gcc/testsuite/ChangeLog PR rtl-optimization/7061 * gcc.target/i386/pr7061-1.c: New test case. * gcc.target/i386/pr7061-2.c: New test case. Thanks in advance, Roger -- ------=_NextPart_000_00E2_01D87415.494C9300 Content-Type: text/plain; name="patchcx.txt" Content-Transfer-Encoding: quoted-printable Content-Disposition: attachment; filename="patchcx.txt" diff --git a/gcc/expr.cc b/gcc/expr.cc=0A= index 7197996..c9df206 100644=0A= --- a/gcc/expr.cc=0A= +++ b/gcc/expr.cc=0A= @@ -2803,10 +2803,26 @@ emit_group_store (rtx orig_dst, rtx src, tree = type ATTRIBUTE_UNUSED,=0A= {=0A= machine_mode dest_mode =3D GET_MODE (dest);=0A= machine_mode tmp_mode =3D GET_MODE (tmps[i]);=0A= + scalar_int_mode imode;=0A= =0A= gcc_assert (known_eq (bytepos, 0) && XVECLEN (src, 0));=0A= =0A= - if (GET_MODE_ALIGNMENT (dest_mode)=0A= + if (finish =3D=3D 1=0A= + && REG_P (tmps[i])=0A= + && COMPLEX_MODE_P (dest_mode)=0A= + && SCALAR_INT_MODE_P (tmp_mode)=0A= + && int_mode_for_mode (dest_mode).exists (&imode))=0A= + {=0A= + if (tmp_mode !=3D imode)=0A= + {=0A= + rtx tmp =3D gen_reg_rtx (imode);=0A= + emit_move_insn (tmp, gen_lowpart (imode, tmps[i]));=0A= + dst =3D gen_lowpart (dest_mode, tmp);=0A= + }=0A= + else=0A= + dst =3D gen_lowpart (dest_mode, tmps[i]);=0A= + }=0A= + else if (GET_MODE_ALIGNMENT (dest_mode)=0A= >=3D GET_MODE_ALIGNMENT (tmp_mode))=0A= {=0A= dest =3D assign_stack_temp (dest_mode,=0A= diff --git a/gcc/testsuite/gcc.target/i386/pr7061-1.c = b/gcc/testsuite/gcc.target/i386/pr7061-1.c=0A= new file mode 100644=0A= index 0000000..ce5f6b2=0A= --- /dev/null=0A= +++ b/gcc/testsuite/gcc.target/i386/pr7061-1.c=0A= @@ -0,0 +1,4 @@=0A= +/* { dg-do compile { target { ! ia32 } } } */=0A= +/* { dg-options "-O2" } */=0A= +float re(float _Complex a) { return __real__ a; }=0A= +/* { dg-final { scan-assembler-not "mov" } } */=0A= diff --git a/gcc/testsuite/gcc.target/i386/pr7061-2.c = b/gcc/testsuite/gcc.target/i386/pr7061-2.c=0A= new file mode 100644=0A= index 0000000..ac33340=0A= --- /dev/null=0A= +++ b/gcc/testsuite/gcc.target/i386/pr7061-2.c=0A= @@ -0,0 +1,5 @@=0A= +/* { dg-do compile { target { ! ia32 } } } */=0A= +/* { dg-options "-O2" } */=0A= +float im(float _Complex a) { return __imag__ a; }=0A= +/* { dg-final { scan-assembler-not "movss" } } */=0A= +/* { dg-final { scan-assembler-not "rsp" } } */=0A= ------=_NextPart_000_00E2_01D87415.494C9300--