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Tested against: 04d6c74564b7eb51660a00b35353aeab706b5a50 Using targets: glibc rv32gcv qemu glibc rv64gcv qemu This patch series does not introduce any new failures. Here's a list of *resolved* failures by this patch series: rv64gcv: FAIL: gfortran.dg/host_assoc_function_7.f90   -O3 -fomit-frame-pointer -funroll-loops -fpeel-loops -ftracer -finline-functions  execution test FAIL: gfortran.dg/host_assoc_function_7.f90   -O3 -g  execution test rv32gcv: FAIL: gcc.target/riscv/rvv/autovec/binop/narrow_run-1.c execution test FAIL: gfortran.dg/host_assoc_function_7.f90   -O3 -fomit-frame-pointer -funroll-loops -fpeel-loops -ftracer -finline-functions  execution test FAIL: gfortran.dg/host_assoc_function_7.f90   -O3 -g  execution test Thanks for the quick revision Lehua! Tested-by: Patrick O'Neill Patrick On 10/19/23 01:50, 钟居哲 wrote: > LGTM now. But wait for Patrick CI testing. > > Hi, @Patrick. Could you apply this patch and trigger CI in your > github  so that we can see the full running result. > > Issues · patrick-rivos/riscv-gnu-toolchain · GitHub > > > ------------------------------------------------------------------------ > juzhe.zhong@rivai.ai > > *From:* Lehua Ding > *Date:* 2023-10-19 16:33 > *To:* gcc-patches > *CC:* juzhe.zhong ; kito.cheng > ; rdapp.gcc > ; palmer ; > jeffreyalaw ; lehua.ding > > *Subject:* [PATCH V3 00/11] Refactor and cleanup vsetvl pass > This patch refactors and cleanups the vsetvl pass in order to make > the code > easier to modify and understand. This patch does several things: > 1. Introducing a virtual CFG for vsetvl infos and Phase 1, 2 and 3 > only maintain >    and modify this virtual CFG. Phase 4 performs insertion, > modification and >    deletion of vsetvl insns based on the virtual CFG. The Basic > block in the >    virtual CFG is called vsetvl_block_info and the vsetvl > information inside >    is called vsetvl_info. > 2. Combine Phase 1 and 2 into a single Phase 1 and unified the > demand system, >    this Phase only fuse local vsetvl info in forward direction. > 3. Refactor Phase 3, change the logic for determining whether to > uplift vsetvl >    info to a pred basic block to a more unified method that there > is a vsetvl >    info in the vsetvl defintion reaching in compatible with it. > 4. Place all modification operations to the RTL in Phase 4 and > Phase 5. >    Phase 4 is responsible for inserting, modifying and deleting vsetvl >    instructions based on fully optimized vsetvl infos. Phase 5 > removes the avl >    operand from the RVV instruction and removes the unused dest > operand >    register from the vsetvl insns. > These modifications resulted in some testcases needing to be > updated. The reasons > for updating are summarized below: > 1. more optimized > vlmax_back_prop-25.c/vlmax_back_prop-26.c/vlmax_conflict-3.c/ >    vlmax_conflict-12.c/vsetvl-13.c/vsetvl-23.c/ > avl_single-23.c/avl_single-89.c/avl_single-95.c/pr109773-1.c > 2. less unnecessary fusion > avl_single-46.c/imm_bb_prop-1.c/pr109743-2.c/vsetvl-18.c > 3. local fuse direction (backward -> forward) >    scalar_move-1.c/ > 4. add some bugfix testcases. >    pr111037-3.c/pr111037-4.c >    avl_single-89.c > PR target/111037 > PR target/111234 > PR target/111725 > Lehua Ding (11): >   RISC-V: P1: Refactor > avl_info/vl_vtype_info/vector_insn_info/vector_block_info >   RISC-V: P2: Refactor and cleanup demand system >   RISC-V: P3: Refactor vector_infos_manager >   RISC-V: P4: move method from pass_vsetvl to pre_vsetvl >   RISC-V: P5: combine phase 1 and 2 >   RISC-V: P6: Add computing reaching definition data flow >   RISC-V: P7: Move earliest fuse and lcm code to pre_vsetvl class >   RISC-V: P8: Refactor emit-vsetvl phase and delete post optimization >   RISC-V: P9: Cleanup and reorganize helper functions >   RISC-V: P10: Delete riscv-vsetvl.h and adjust riscv-vsetvl.def >   RISC-V: P11: Adjust and add testcases > gcc/config/riscv/riscv-vsetvl.cc              | 6502 +++++++---------- > gcc/config/riscv/riscv-vsetvl.def             |  641 +- > gcc/config/riscv/riscv-vsetvl.h               |  488 -- > gcc/config/riscv/t-riscv                      |    2 +- > .../gcc.target/riscv/rvv/base/scalar_move-1.c |    2 +- > .../riscv/rvv/vsetvl/avl_single-104.c         |   35 + > .../riscv/rvv/vsetvl/avl_single-105.c         |   23 + > .../riscv/rvv/vsetvl/avl_single-106.c         |   34 + > .../riscv/rvv/vsetvl/avl_single-107.c         |   41 + > .../riscv/rvv/vsetvl/avl_single-108.c         |   41 + > .../riscv/rvv/vsetvl/avl_single-109.c         |   45 + > .../riscv/rvv/vsetvl/avl_single-23.c          |    7 +- > .../riscv/rvv/vsetvl/avl_single-46.c          |    3 +- > .../riscv/rvv/vsetvl/avl_single-84.c          |    5 +- > .../riscv/rvv/vsetvl/avl_single-89.c          |    8 +- > .../riscv/rvv/vsetvl/avl_single-95.c          |    2 +- > .../riscv/rvv/vsetvl/imm_bb_prop-1.c          |    7 +- > .../gcc.target/riscv/rvv/vsetvl/pr109743-2.c  |    2 +- > .../gcc.target/riscv/rvv/vsetvl/pr109773-1.c  |    2 +- > .../riscv/rvv/{base => vsetvl}/pr111037-1.c   |    0 > .../riscv/rvv/{base => vsetvl}/pr111037-2.c   |    0 > .../gcc.target/riscv/rvv/vsetvl/pr111037-3.c  |   16 + > .../gcc.target/riscv/rvv/vsetvl/pr111037-4.c  |   16 + > .../riscv/rvv/vsetvl/vlmax_back_prop-25.c     |   10 +- > .../riscv/rvv/vsetvl/vlmax_back_prop-26.c     |   10 +- > .../riscv/rvv/vsetvl/vlmax_conflict-12.c      |    1 - > .../riscv/rvv/vsetvl/vlmax_conflict-3.c       |    2 +- > .../gcc.target/riscv/rvv/vsetvl/vsetvl-13.c   |    4 +- > .../gcc.target/riscv/rvv/vsetvl/vsetvl-18.c   |    4 +- > .../gcc.target/riscv/rvv/vsetvl/vsetvl-23.c   |    2 +- > 30 files changed, 3263 insertions(+), 4692 deletions(-) > delete mode 100644 gcc/config/riscv/riscv-vsetvl.h > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-104.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-105.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-106.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-107.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-108.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/avl_single-109.c > rename gcc/testsuite/gcc.target/riscv/rvv/{base => > vsetvl}/pr111037-1.c (100%) > rename gcc/testsuite/gcc.target/riscv/rvv/{base => > vsetvl}/pr111037-2.c (100%) > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-3.c > create mode 100644 > gcc/testsuite/gcc.target/riscv/rvv/vsetvl/pr111037-4.c > -- > 2.36.3 > --------------KxHeeYaD3z2pGNRUUF20h0Oh--