[x86 PATCH] PR rtl-optimization/107991: peephole2 to tweak register allocation.

["Roger Sayle" <roger@nextmovesoftware.com>]

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This patch addresses PR rtl-optimization/107991, which is a P2 regression
where GCC currently requires more "mov" instructions than GCC 7.

The x86's two address ISA creates some interesting challenges for reload.
For example, the tricky "x = y - x" usually needs to be implemented on x86
as

        tmp = x
        x = y
        x -= tmp

where a scratch register and two mov's are required to work around
the lack of a subf (subtract from) or rsub (reverse subtract) insn.

Not uncommonly, if y is dead after this subtraction, register allocation
can be improved by clobbering y.

        y -= x
        x = y

For the testcase in PR 107991, things are slightly more complicated,
where y is not itself dead, but is assigned from (i.e. equivalent to)
a value that is dead.  Hence we have something like:

        y = z
        x = y - x

so, GCC's reload currently generates the expected shuffle (as y is live):

        y = z
        tmp = x
        x = y
        x -= tmp

but we can use a peephole2 that understands that y and z are equivalent,
and that z is dead, to produce the shorter sequence:

        y = z
        z -= x
        x = z

In practice, for the new testcase from PR 107991, which before produced:

foo:    movl    %edx, %ecx
        movl    %esi, %edx
        movl    %esi, %eax
        subl    %ecx, %edx
        testb   %dil, %dil
        cmovne  %edx, %eax
        ret

with this patch/peephole2 we now produce the much improved:

foo:    movl    %esi, %eax
        subl    %edx, %esi
        testb   %dil, %dil
        cmovne  %esi, %eax
        ret


This patch has been tested on x86_64-pc-linux-gnu with make bootstrap
and make -k check, both with and without --target_board=unix{-m32},
with no new failures.  Ok for mainline?


2023-01-09  Roger Sayle  <roger@nextmovesoftware.com>

gcc/ChangeLog
        PR rtl-optimization/107991
        * config/i386/i386.md (peephole2): New peephole2 to avoid register
        shuffling before a subtraction, after a register-to-register move.

gcc/testsuite/ChangeLog
        PR rtl-optimization/107991
        * gcc.target/i386/pr107991.c: New test case.


Thanks in advance,
Roger
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diff --git a/gcc/config/i386/i386.md b/gcc/config/i386/i386.md
index 76f55ec..3090cea 100644
--- a/gcc/config/i386/i386.md
+++ b/gcc/config/i386/i386.md
@@ -7603,6 +7603,31 @@
   "sub{l}\t{%2, %1|%1, %2}"
   [(set_attr "type" "alu")
    (set_attr "mode" "SI")])
+
+;; PR 107991: Use peephole2 to avoid suffling before subtraction.
+;; ax = si; cx = dx; dx = ax; dx -= cx where both si and cx
+;; are dead becomes ax = si; si -= dx; dx = si.
+(define_peephole2
+  [(set (match_operand:SWI 0 "general_reg_operand")
+	(match_operand:SWI 1 "general_reg_operand"))
+   (set (match_operand:SWI 2 "general_reg_operand")
+	(match_operand:SWI 3 "general_reg_operand"))
+   (set (match_dup 3) (match_dup 0))
+   (parallel
+     [(set (match_dup 3) (minus:SWI (match_dup 3) (match_dup 2)))
+      (clobber (reg:CC FLAGS_REG))])]
+  "REGNO (operands[0]) != REGNO (operands[1])
+   && REGNO (operands[0]) != REGNO (operands[2])
+   && REGNO (operands[0]) != REGNO (operands[3])
+   && REGNO (operands[1]) != REGNO (operands[2])
+   && REGNO (operands[1]) != REGNO (operands[3])
+   && REGNO (operands[2]) != REGNO (operands[3])
+   && peep2_reg_dead_p (1, operands[1])
+   && peep2_reg_dead_p (4, operands[2])"
+  [(set (match_dup 0) (match_dup 1))
+   (parallel [(set (match_dup 1) (minus:SWI (match_dup 1) (match_dup 3)))
+	      (clobber (reg:CC FLAGS_REG))])
+   (set (match_dup 3) (match_dup 1))])
 \f
 ;; Add with carry and subtract with borrow
 
diff --git a/gcc/testsuite/gcc.target/i386/pr107991.c b/gcc/testsuite/gcc.target/i386/pr107991.c
new file mode 100644
index 0000000..9d0d9b6
--- /dev/null
+++ b/gcc/testsuite/gcc.target/i386/pr107991.c
@@ -0,0 +1,16 @@
+/* { dg-do compile { target { ! ia32 } } } */
+/* { dg-options "-O2" } */
+
+int foo(_Bool b, int i, int j) {
+    return b ? i - j : i;
+}
+
+int bar(_Bool b, int i, int j) {
+    return i + (b ? -j : 0);
+}
+
+int baz(_Bool b, int i, int j) {
+    return i - (b ? j : 0);
+}
+
+/* { dg-final { scan-assembler-times "movl" 3 } } */