This patch teaches the ARC backend that the contents of the carry flag
can be placed in an integer register conveniently using the "rlc rX,0"
instruction, which is a rotate-left-through-carry using zero as a source.
This is a convenient special case for the LTU form of the scc pattern.

unsigned int foo(unsigned int x, unsigned int y)
{
  return (x+y) < x;
}

With -O2 -mcpu=em this is currently compiled to:

foo:    add.f 0,r0,r1
        mov_s   r0,1    ;3
        j_s.d   [blink]
        mov.hs r0,0

[which after an addition to set the carry flag, sets r0 to 1,
followed by a conditional assignment of r0 to zero if the
carry flag is clear].  With the new define_insn/optimization
in this patch, this becomes:

foo:    add.f 0,r0,r1
        j_s.d   [blink]
        rlc     r0,0

This define_insn is also a useful building block for implementing
shifts and rotates.

Tested on a cross-compiler to arc-linux (hosted on x86_64-pc-linux-gnu),
and a partial tool chain, where the new case passes and there are no
new regressions.  Ok for mainline?


2023-09-29  Roger Sayle  <roger@nextmovesoftware.com>

gcc/ChangeLog
        * config/arc/arc.md (CC_ltu): New mode iterator for CC and CC_C.
        (scc_ltu_<mode>): New define_insn to handle LTU form of scc_insn.
        (*scc_insn): Don't split to a conditional move sequence for LTU.

gcc/testsuite/ChangeLog
        * gcc.target/arc/scc-ltu.c: New test case.


Thanks in advance,
Roger
--