Re: Re: [PATCH V2] RISC-V: Add basic vec_init for VLS RVV auto-vectorization

["juzhe.zhong@rivai.ai" <juzhe.zhong@rivai.ai>]

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I have remove comments related to LLVM and reorg testcases:
https://gcc.gnu.org/pipermail/gcc-patches/2023-May/618256.html 
V3 can you take a look again.

Sorry for sending wrong comments in changelog. Well, I goal is not to disparage LLVM.
I am just used to reading the LLVM implementation while sending patch for GCC to make sure
the implementation is correct.

The slidedown method is totally the same as LLVM. 

Sorry about that, I won't send any information related to LLVM gain. Thanks :)



juzhe.zhong@rivai.ai
 
From: Kito Cheng
Date: 2023-05-12 10:23
To: juzhe.zhong
CC: gcc-patches; palmer; jeffreyalaw; rdapp.gcc
Subject: Re: [PATCH V2] RISC-V: Add basic vec_init for VLS RVV auto-vectorization
> This patch makes vec_init support common init vector handling (using vslide1down to insert element)
> which can handle any cases of initialization vec but it's not optimal for cases.
>
> And support Case 1 optimizaiton:
> https://godbolt.org/z/Yb9PK9jsz
 
Don't use godbolt link in comment, because they are not permanently
preserved on the server, also the reference is not fixed since LLVM
trunk could improve.
 
> LLVM codegen:
> https://godbolt.org/z/xsnavvWqx
>
> ...
> vslide1down.vx (x128 times)
> ...
 
Drop LLVM codegen here, again, it might improve, healthy competition
is good, but I would like to avoid disparaging other compilers in
comments. :)
 
 
> ---
>  gcc/config/riscv/autovec.md                   |  16 ++
>  gcc/config/riscv/riscv-protos.h               |   1 +
>  gcc/config/riscv/riscv-v.cc                   | 127 +++++++++++
>  gcc/config/riscv/vector-iterators.md          |   9 +
>  .../gcc.target/riscv/rvv/autovec/insert-1.c   |  41 ++++
>  .../gcc.target/riscv/rvv/autovec/insert-2.c   |  41 ++++
>  .../gcc.target/riscv/rvv/autovec/insert-3.c   |  41 ++++
>  .../riscv/rvv/autovec/insert_run-1.c          |  46 ++++
>  .../riscv/rvv/autovec/insert_run-2.c          |  46 ++++
>  .../gcc.target/riscv/rvv/autovec/repeat-1.c   |  75 +++++++
>  .../gcc.target/riscv/rvv/autovec/repeat-2.c   |  61 ++++++
>  .../gcc.target/riscv/rvv/autovec/repeat-3.c   |  53 +++++
>  .../gcc.target/riscv/rvv/autovec/repeat-4.c   |  39 ++++
>  .../gcc.target/riscv/rvv/autovec/repeat-5.c   |  74 +++++++
>  .../gcc.target/riscv/rvv/autovec/repeat-6.c   |  78 +++++++
>  .../riscv/rvv/autovec/repeat_run-1.c          | 125 +++++++++++
>  .../riscv/rvv/autovec/repeat_run-2.c          | 145 +++++++++++++
>  .../riscv/rvv/autovec/repeat_run-3.c          | 203 ++++++++++++++++++
>  .../riscv/rvv/autovec/repeat_run-4.c          |  77 +++++++
>  .../riscv/rvv/autovec/repeat_run-5.c          | 124 +++++++++++
>  .../riscv/rvv/autovec/repeat_run-6.c          | 122 +++++++++++
>  21 files changed, 1544 insertions(+)
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/insert-1.c
 
Could you reorg the autovec folder to separate vls-vlmax and vla stuffs?
 
>  create mode 100644 gcc/testsuite/gcc.target/riscv/rvv/autovec/insert-2.c
...
> +/* Initialize register TARGET from the elements in PARALLEL rtx VALS.  */
> +
> +void
> +expand_vec_init (rtx target, rtx vals)
> +{
> +  machine_mode mode = GET_MODE (target);
 
I would like to add some assertion here to ensure only VLS mode here.