From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from server.nextmovesoftware.com (server.nextmovesoftware.com [162.254.253.69]) by sourceware.org (Postfix) with ESMTPS id A21D83857816 for ; Mon, 18 Oct 2021 15:07:25 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org A21D83857816 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=nextmovesoftware.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=nextmovesoftware.com DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=nextmovesoftware.com; s=default; h=Content-Type:MIME-Version:Message-ID: Date:Subject:Cc:To:From:Sender:Reply-To:Content-Transfer-Encoding:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:In-Reply-To:References:List-Id:List-Help:List-Unsubscribe: List-Subscribe:List-Post:List-Owner:List-Archive; bh=JI22Kb1S6PYYwJImpqVzF03tjFrbJUWSncXhfICPUKQ=; b=e47dWhx5tWBmumVzA5hYH131NE mpZUfLb8YHiJXwupUuQClJCu2Z+79U0SvATRGzLl3MQf3Sj8qMWO/8rdxRcsqGQNF5G2rN7R6inwz FsQBRyEzRofCbQKvT429eNLZrIpTIeRqj1XtvokL9GsyljV+6axdgdTA09qJ+zkZjvNGQvCl+vxYC xYlDRSYLp/X7kzhv4VXyBenIzXHIziZkHXAMzSmFRc08swINWkrOWMZlW2TuvA0+ae0n7ZJmjeSZ0 pu30x0okTiQ6hbxAysh2PmMPJ1DlyIV4ejC2LwuG6t1RJPB+n2sdazsxms90k83twvvPFfl1IEY1K NoG7eXYA==; Received: from [185.62.158.67] (port=53681 helo=Dell) by server.nextmovesoftware.com with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1mcUEW-0004GJ-P8; Mon, 18 Oct 2021 11:07:24 -0400 From: "Roger Sayle" To: "'GCC Patches'" Subject: [PATCH] PR target/102785: Correct addsub/subadd patterns on bfin. Date: Mon, 18 Oct 2021 16:07:23 +0100 Message-ID: <01cf01d7c431$db8495e0$928dc1a0$@nextmovesoftware.com> MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="----=_NextPart_000_01D0_01D7C43A.3D4A5D70" X-Mailer: Microsoft Outlook 16.0 Thread-Index: AdfEMdpDFOatgB59Th2dd8H0nEylwA== Content-Language: en-gb X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - server.nextmovesoftware.com X-AntiAbuse: Original Domain - gcc.gnu.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - nextmovesoftware.com X-Get-Message-Sender-Via: server.nextmovesoftware.com: authenticated_id: roger@nextmovesoftware.com X-Authenticated-Sender: server.nextmovesoftware.com: roger@nextmovesoftware.com X-Source: X-Source-Args: X-Source-Dir: X-Spam-Status: No, score=-12.1 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-patches@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-patches mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Mon, 18 Oct 2021 15:07:27 -0000 This is a multipart message in MIME format. ------=_NextPart_000_01D0_01D7C43A.3D4A5D70 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit This patch resolves PR target/102785 where my recent patch to constant fold saturating addition/subtraction exposed a latent bug in the bfin backend. The patterns used for blackfin's V2HI ssaddsub and sssubadd instructions had the indices/operations swapped. This was harmless until we started evaluating these expressions at compile-time, when the mismatch was caught by the testsuite. Many thanks to Jeff Law for confirming that this patch fixes these regressions on bfin-elf. Ok for mainline? 2021-10-18 Roger Sayle gcc/ChangeLog PR target/102785 * config/bfin/bfin.md (addsubv2hi3, subaddv2hi3, ssaddsubv2hi3, sssubaddv2hi3): Swap the order of operators in vec_concat. Thanks again, Roger -- ------=_NextPart_000_01D0_01D7C43A.3D4A5D70 Content-Type: text/plain; name="patchj.txt" Content-Transfer-Encoding: quoted-printable Content-Disposition: attachment; filename="patchj.txt" diff --git a/gcc/config/bfin/bfin.md b/gcc/config/bfin/bfin.md=0A= index 8b311f3..fd65f4d 100644=0A= --- a/gcc/config/bfin/bfin.md=0A= +++ b/gcc/config/bfin/bfin.md=0A= @@ -3018,19 +3018,6 @@=0A= (define_insn "addsubv2hi3"=0A= [(set (match_operand:V2HI 0 "register_operand" "=3Dd")=0A= (vec_concat:V2HI=0A= - (plus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")=0A= - (parallel [(const_int 0)]))=0A= - (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")=0A= - (parallel [(const_int 0)])))=0A= - (minus:HI (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))=0A= - (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]=0A= - ""=0A= - "%0 =3D %1 +|- %2%!"=0A= - [(set_attr "type" "dsp32")])=0A= -=0A= -(define_insn "subaddv2hi3"=0A= - [(set (match_operand:V2HI 0 "register_operand" "=3Dd")=0A= - (vec_concat:V2HI=0A= (minus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")=0A= (parallel [(const_int 0)]))=0A= (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")=0A= @@ -3038,23 +3025,23 @@=0A= (plus:HI (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))=0A= (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]=0A= ""=0A= - "%0 =3D %1 -|+ %2%!"=0A= + "%0 =3D %1 +|- %2%!"=0A= [(set_attr "type" "dsp32")])=0A= =0A= -(define_insn "ssaddsubv2hi3"=0A= +(define_insn "subaddv2hi3"=0A= [(set (match_operand:V2HI 0 "register_operand" "=3Dd")=0A= (vec_concat:V2HI=0A= - (ss_plus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" = "d")=0A= - (parallel [(const_int 0)]))=0A= - (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")=0A= - (parallel [(const_int 0)])))=0A= - (ss_minus:HI (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))=0A= - (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]=0A= + (plus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" "d")=0A= + (parallel [(const_int 0)]))=0A= + (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")=0A= + (parallel [(const_int 0)])))=0A= + (minus:HI (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))=0A= + (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]=0A= ""=0A= - "%0 =3D %1 +|- %2 (S)%!"=0A= + "%0 =3D %1 -|+ %2%!"=0A= [(set_attr "type" "dsp32")])=0A= =0A= -(define_insn "sssubaddv2hi3"=0A= +(define_insn "ssaddsubv2hi3"=0A= [(set (match_operand:V2HI 0 "register_operand" "=3Dd")=0A= (vec_concat:V2HI=0A= (ss_minus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" = "d")=0A= @@ -3064,6 +3051,19 @@=0A= (ss_plus:HI (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))=0A= (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]=0A= ""=0A= + "%0 =3D %1 +|- %2 (S)%!"=0A= + [(set_attr "type" "dsp32")])=0A= +=0A= +(define_insn "sssubaddv2hi3"=0A= + [(set (match_operand:V2HI 0 "register_operand" "=3Dd")=0A= + (vec_concat:V2HI=0A= + (ss_plus:HI (vec_select:HI (match_operand:V2HI 1 "register_operand" = "d")=0A= + (parallel [(const_int 0)]))=0A= + (vec_select:HI (match_operand:V2HI 2 "register_operand" "d")=0A= + (parallel [(const_int 0)])))=0A= + (ss_minus:HI (vec_select:HI (match_dup 1) (parallel [(const_int 1)]))=0A= + (vec_select:HI (match_dup 2) (parallel [(const_int 1)])))))]=0A= + ""=0A= "%0 =3D %1 -|+ %2 (S)%!"=0A= [(set_attr "type" "dsp32")])=0A= =0A= ------=_NextPart_000_01D0_01D7C43A.3D4A5D70--