From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from server.nextmovesoftware.com (server.nextmovesoftware.com [162.254.253.69]) by sourceware.org (Postfix) with ESMTPS id 4CF543858D20 for ; Mon, 6 Nov 2023 17:30:11 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org 4CF543858D20 Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=nextmovesoftware.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=nextmovesoftware.com ARC-Filter: OpenARC Filter v1.0.0 sourceware.org 4CF543858D20 Authentication-Results: server2.sourceware.org; arc=none smtp.remote-ip=162.254.253.69 ARC-Seal: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1699291813; cv=none; b=NyUaUMyhEvhHpxlpY4sqkULIMpqS2sGOnVhUJYpbFCwSe8DR8WueOe4bsyx8qzrGEM4BMtiH/Q3mFXo5engIVafjnZFrqw16p/BdtTB8ddbp0Agw2feWLGUL33eRHWcY2KKLDLZClmt9kOiPodDZCEpI/tsLnXnKtpxH9fPt71U= ARC-Message-Signature: i=1; a=rsa-sha256; d=sourceware.org; s=key; t=1699291813; c=relaxed/simple; bh=+OOpkYDtaWrrb8wx60UhbtYKmgwo69Y0Hku/q1G2HxU=; h=DKIM-Signature:From:To:Subject:Date:Message-ID:MIME-Version; b=jMYoWbTWTpYz7uRNdyGUMFiPj0sNKRoU6+a4iGjmxVkFg8+PS7NxbtazFst9sKorrXR80xm5YBtbIBo3V2SXibgR4H6Dp0PyQ8M8qPem3ZE0jumwaxoA297re7tAsUmGMeYOvS1r5LivR4H1y26gtkoVTBLCsGlueI/G/P7nVJw= ARC-Authentication-Results: i=1; server2.sourceware.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=nextmovesoftware.com; s=default; h=Content-Type:MIME-Version:Message-ID: Date:Subject:Cc:To:From:Sender:Reply-To:Content-Transfer-Encoding:Content-ID: Content-Description:Resent-Date:Resent-From:Resent-Sender:Resent-To:Resent-Cc :Resent-Message-ID:In-Reply-To:References:List-Id:List-Help:List-Unsubscribe: List-Subscribe:List-Post:List-Owner:List-Archive; bh=4o5qUaoSIzwm2xWcL6sGCYvf8Se9UCaGxfkjEzTo72o=; b=nuA8o4VQtLYlRpKJVtjO22c/PQ OQht0BqEq5Ut9qCub/faOnvSsMYieKzzO1t6ni7PCHo9mGimCjDJdKAw7DONefGO7Tf3HwLCUauH9 kRPzNCaVnbRn44wC81DoM6GyDDRlV0qKeFEKM5vKqDq45Ipxd4gju8+zq+RlQy97PRTHIHN6dqqL6 1qU/7VQJ4v9pBkugnt77Zo4GJU+Rc4Nd7GrUIaYy/8DttDCNQbeswQi4No9rOwnFezhykdmVFzvKx ZABPUUPOO1RraGp3SQpNaxBeXpl/+QntXWNS71EkBkWJDq0rP82YwH0r+48XS3wdyGKLeM9t4qLMb AyqPtTLg==; Received: from [185.62.158.67] (port=56109 helo=Dell) by server.nextmovesoftware.com with esmtpsa (TLS1.2) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.96.2) (envelope-from ) id 1r03QQ-0004GV-1A; Mon, 06 Nov 2023 12:30:10 -0500 From: "Roger Sayle" To: Cc: "'Claudiu Zissulescu'" Subject: [ARC PATCH] Improved DImode rotates and right shifts by one bit. Date: Mon, 6 Nov 2023 17:30:06 -0000 Message-ID: <01fd01da10d6$e3c2ef60$ab48ce20$@nextmovesoftware.com> MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="----=_NextPart_000_01FE_01DA10D6.E3C2EF60" X-Mailer: Microsoft Outlook 16.0 Thread-Index: AdoQ1kbkQaagx0c/Q9Kg/JL/RupmRg== Content-Language: en-gb X-AntiAbuse: This header was added to track abuse, please include it with any abuse report X-AntiAbuse: Primary Hostname - server.nextmovesoftware.com X-AntiAbuse: Original Domain - gcc.gnu.org X-AntiAbuse: Originator/Caller UID/GID - [47 12] / [47 12] X-AntiAbuse: Sender Address Domain - nextmovesoftware.com X-Get-Message-Sender-Via: server.nextmovesoftware.com: authenticated_id: roger@nextmovesoftware.com X-Authenticated-Sender: server.nextmovesoftware.com: roger@nextmovesoftware.com X-Source: X-Source-Args: X-Source-Dir: X-Spam-Status: No, score=-12.4 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,KAM_SHORT,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: This is a multipart message in MIME format. ------=_NextPart_000_01FE_01DA10D6.E3C2EF60 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit This patch improves the code generated for DImode right shifts (both arithmetic and logical) by a single bit, and also for DImode rotates (both left and right) by a single bit. In approach, this is similar to the recently added DImode left shift by a single bit patch, but also builds upon i386.md's UNSPEC carry flag representation: https://gcc.gnu.org/pipermail/gcc-patches/2023-October/632169.html The benefits can be seen from the four new test cases: long long ashr(long long x) { return x >> 1; } Before: ashr: asl r2,r1,31 lsr_s r0,r0 or_s r0,r0,r2 j_s.d [blink] asr_s r1,r1,1 After: ashr: asr.f r1,r1 j_s.d [blink] rrc r0,r0 unsigned long long lshr(unsigned long long x) { return x >> 1; } Before: lshr: asl r2,r1,31 lsr_s r0,r0 or_s r0,r0,r2 j_s.d [blink] lsr_s r1,r1 After: lshr: lsr.f r1,r1 j_s.d [blink] rrc r0,r0 unsigned long long rotl(unsigned long long x) { return (x<<1) | (x>>63); } Before: rotl: lsr r12,r1,31 lsr r2,r0,31 asl_s r3,r0,1 asl_s r1,r1,1 or r0,r12,r3 j_s.d [blink] or_s r1,r1,r2 After: rotl: add.f r0,r0,r0 adc.f r1,r1,r1 j_s.d [blink] add.cs r0,r0,1 unsigned long long rotr(unsigned long long x) { return (x>>1) | (x<<63); } Before: rotr: asl r12,r1,31 asl r2,r0,31 lsr_s r3,r0 lsr_s r1,r1 or r0,r12,r3 j_s.d [blink] or_s r1,r1,r2 After: rotr: asr.f 0,r0 rrc.f r1,r1 j_s.d [blink] rrc r0,r0 On CPUs without a barrel shifter the improvements are even better. Tested with a cross-compiler to arc-linux hosted on x86_64, with no new (compile-only) regressions from make -k check. Ok for mainline if this passes Claudiu's nightly testing? 2023-11-06 Roger Sayle gcc/ChangeLog * config/arc/arc.md (UNSPEC_ARC_CC_NEZ): New UNSPEC that represents the carry flag being set if the operand is non-zero. (adc_f): New define_insn representing adc with updated flags. (ashrdi3): New define_expand that only handles shifts by 1. (ashrdi3_cnt1): New pre-reload define_insn_and_split. (lshrdi3): New define_expand that only handles shifts by 1. (lshrdi3_cnt1): New pre-reload define_insn_and_split. (rrcsi2): New define_insn for rrc (SImode rotate right through carry). (rrcsi2_carry): Likewise for rrc.f, as above but updating flags. (rotldi3): New define_expand that only handles rotates by 1. (rotldi3_cnt1): New pre-reload define_insn_and_split. (rotrdi3): New define_expand that only handles rotates by 1. (rotrdi3_cnt1): New pre-reload define_insn_and_split. (lshrsi3_cnt1_carry): New define_insn for lsr.f. (ashrsi3_cnt1_carry): New define_insn for asr.f. (btst_0_carry): New define_insn for asr.f without result. gcc/testsuite/ChangeLog * gcc.target/arc/ashrdi3-1.c: New test case. * gcc.target/arc/lshrdi3-1.c: Likewise. * gcc.target/arc/rotldi3-1.c: Likewise. * gcc.target/arc/rotrdi3-1.c: Likewise. Thanks in advance, Roger -- ------=_NextPart_000_01FE_01DA10D6.E3C2EF60 Content-Type: text/plain; name="patchar3.txt" Content-Transfer-Encoding: quoted-printable Content-Disposition: attachment; filename="patchar3.txt" diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md=0A= index 7702978..97231b9 100644=0A= --- a/gcc/config/arc/arc.md=0A= +++ b/gcc/config/arc/arc.md=0A= @@ -137,6 +137,7 @@=0A= UNSPEC_ARC_VMAC2HU=0A= UNSPEC_ARC_VMPY2H=0A= UNSPEC_ARC_VMPY2HU=0A= + UNSPEC_ARC_CC_NEZ=0A= =0A= VUNSPEC_ARC_RTIE=0A= VUNSPEC_ARC_SYNC=0A= @@ -2790,6 +2791,31 @@ archs4x, archs4xd"=0A= (set_attr "type" "cc_arith")=0A= (set_attr "length" "4,4,4,4,8,8")])=0A= =0A= +(define_insn "adc_f"=0A= + [(set (reg:CC_C CC_REG)=0A= + (compare:CC_C=0A= + (zero_extend:DI=0A= + (plus:SI=0A= + (plus:SI=0A= + (ltu:SI (reg:CC_C CC_REG) (const_int 0))=0A= + (match_operand:SI 1 "register_operand" "%r"))=0A= + (match_operand:SI 2 "register_operand" "r")))=0A= + (plus:DI=0A= + (ltu:DI (reg:CC_C CC_REG) (const_int 0))=0A= + (zero_extend:DI (match_dup 1)))))=0A= + (set (match_operand:SI 0 "register_operand" "=3Dr")=0A= + (plus:SI=0A= + (plus:SI=0A= + (ltu:SI (reg:CC_C CC_REG) (const_int 0))=0A= + (match_dup 1))=0A= + (match_dup 2)))]=0A= + ""=0A= + "adc.f\\t%0,%1,%2"=0A= + [(set_attr "cond" "set")=0A= + (set_attr "predicable" "no")=0A= + (set_attr "type" "cc_arith")=0A= + (set_attr "length" "4")])=0A= +=0A= ; combiner-splitter cmp / scc -> cmp / adc=0A= (define_split=0A= [(set (match_operand:SI 0 "dest_reg_operand" "")=0A= @@ -3530,6 +3556,68 @@ archs4x, archs4xd"=0A= ""=0A= [(set_attr "length" "8")])=0A= =0A= +(define_expand "ashrdi3"=0A= + [(parallel=0A= + [(set (match_operand:DI 0 "register_operand")=0A= + (ashiftrt:DI (match_operand:DI 1 "register_operand")=0A= + (match_operand:QI 2 "const_int_operand")))=0A= + (clobber (reg:CC CC_REG))])]=0A= + ""=0A= +{=0A= + if (operands[2] !=3D const1_rtx)=0A= + FAIL;=0A= +})=0A= +=0A= +;; Split into asr.f hi; rrc lo=0A= +(define_insn_and_split "*ashrdi3_cnt1"=0A= + [(set (match_operand:DI 0 "register_operand")=0A= + (ashiftrt:DI (match_operand:DI 1 "register_operand")=0A= + (const_int 1)))=0A= + (clobber (reg:CC CC_REG))]=0A= + "arc_pre_reload_split ()"=0A= + "#"=0A= + "&& 1"=0A= + [(const_int 0)]=0A= +{=0A= + emit_insn (gen_ashrsi3_cnt1_carry (gen_highpart (SImode, operands[0]),=0A= + gen_highpart (SImode, operands[1])));=0A= + emit_insn (gen_rrcsi2 (gen_lowpart (SImode, operands[0]),=0A= + gen_lowpart (SImode, operands[1])));=0A= + DONE;=0A= +}=0A= + [(set_attr "length" "8")])=0A= +=0A= +(define_expand "lshrdi3"=0A= + [(parallel=0A= + [(set (match_operand:DI 0 "register_operand")=0A= + (lshiftrt:DI (match_operand:DI 1 "register_operand")=0A= + (match_operand:QI 2 "const_int_operand")))=0A= + (clobber (reg:CC CC_REG))])]=0A= + ""=0A= +{=0A= + if (operands[2] !=3D const1_rtx)=0A= + FAIL;=0A= +})=0A= +=0A= +;; Split into lsr.f hi; rrc lo=0A= +(define_insn_and_split "*lshrdi3_cnt1"=0A= + [(set (match_operand:DI 0 "register_operand")=0A= + (lshiftrt:DI (match_operand:DI 1 "register_operand")=0A= + (const_int 1)))=0A= + (clobber (reg:CC CC_REG))]=0A= + "arc_pre_reload_split ()"=0A= + "#"=0A= + "&& 1"=0A= + [(const_int 0)]=0A= +{=0A= + emit_insn (gen_lshrsi3_cnt1_carry (gen_highpart (SImode, operands[0]),=0A= + gen_highpart (SImode, operands[1])));=0A= + emit_insn (gen_rrcsi2 (gen_lowpart (SImode, operands[0]),=0A= + gen_lowpart (SImode, operands[1])));=0A= + DONE;=0A= +}=0A= + [(set_attr "length" "8")])=0A= +=0A= ;; Rotate instructions.=0A= =0A= (define_insn "rotrsi3_insn"=0A= @@ -3571,6 +3659,103 @@ archs4x, archs4xd"=0A= }=0A= })=0A= =0A= +;; Rotate through carry flag=0A= +=0A= +(define_insn "rrcsi2"=0A= + [(set (match_operand:SI 0 "dest_reg_operand" "=3Dr")=0A= + (plus:SI=0A= + (lshiftrt:SI (match_operand:SI 1 "register_operand" "r")=0A= + (const_int 1))=0A= + (ashift:SI (ltu:SI (reg:CC_C CC_REG) (const_int 0))=0A= + (const_int 31))))]=0A= + ""=0A= + "rrc\\t%0,%1"=0A= + [(set_attr "type" "shift")=0A= + (set_attr "predicable" "no")=0A= + (set_attr "length" "4")])=0A= +=0A= +(define_insn "rrcsi2_carry"=0A= + [(set (reg:CC_C CC_REG)=0A= + (unspec:CC_C [(and:SI (match_operand:SI 1 "register_operand" "r")=0A= + (const_int 1))] UNSPEC_ARC_CC_NEZ))=0A= + (set (match_operand:SI 0 "dest_reg_operand" "=3Dr")=0A= + (plus:SI=0A= + (lshiftrt:SI (match_dup 1) (const_int 1))=0A= + (ashift:SI (ltu:SI (reg:CC_C CC_REG) (const_int 0))=0A= + (const_int 31))))]=0A= + ""=0A= + "rrc.f\\t%0,%1"=0A= + [(set_attr "type" "shift")=0A= + (set_attr "predicable" "no")=0A= + (set_attr "length" "4")])=0A= +=0A= +;; DImode Rotate instructions=0A= +=0A= +(define_expand "rotldi3"=0A= + [(parallel=0A= + [(set (match_operand:DI 0 "register_operand")=0A= + (rotate:DI (match_operand:DI 1 "register_operand")=0A= + (match_operand:QI 2 "const_int_operand")))=0A= + (clobber (reg:CC CC_REG))])]=0A= + ""=0A= +{=0A= + if (operands[2] !=3D const1_rtx)=0A= + FAIL;=0A= +})=0A= +=0A= +;; split into add.f lo; adc.f hi; adc lo=0A= +(define_insn_and_split "*rotldi3_cnt1"=0A= + [(set (match_operand:DI 0 "register_operand")=0A= + (rotate:DI (match_operand:DI 1 "register_operand")=0A= + (const_int 1)))=0A= + (clobber (reg:CC CC_REG))]=0A= + "arc_pre_reload_split ()"=0A= + "#"=0A= + "&& 1"=0A= + [(const_int 0)]=0A= +{=0A= + rtx lo0 =3D gen_lowpart (SImode, operands[0]);=0A= + rtx lo1 =3D gen_lowpart (SImode, operands[1]);=0A= + rtx hi1 =3D gen_highpart (SImode, operands[1]);=0A= + emit_insn (gen_add_f (lo0, lo1, lo1));=0A= + emit_insn (gen_adc_f (gen_highpart (SImode, operands[0]), hi1, hi1));=0A= + emit_insn (gen_adc (lo0, lo0, const0_rtx));=0A= + DONE;=0A= +}=0A= + [(set_attr "length" "12")])=0A= +=0A= +(define_expand "rotrdi3"=0A= + [(parallel=0A= + [(set (match_operand:DI 0 "register_operand")=0A= + (rotatert:DI (match_operand:DI 1 "register_operand")=0A= + (match_operand:QI 2 "const_int_operand")))=0A= + (clobber (reg:CC CC_REG))])]=0A= + ""=0A= +{=0A= + if (operands[2] !=3D const1_rtx)=0A= + FAIL;=0A= +})=0A= +=0A= +;; split into asr.f lo; rrc.f hi; rrc lo=0A= +(define_insn_and_split "*rotrdi3_cnt1"=0A= + [(set (match_operand:DI 0 "register_operand")=0A= + (rotatert:DI (match_operand:DI 1 "register_operand")=0A= + (const_int 1)))=0A= + (clobber (reg:CC CC_REG))]=0A= + "arc_pre_reload_split ()"=0A= + "#"=0A= + "&& 1"=0A= + [(const_int 0)]=0A= +{=0A= + rtx lo =3D gen_lowpart (SImode, operands[1]);=0A= + emit_insn (gen_btst_0_carry (lo));=0A= + emit_insn (gen_rrcsi2_carry (gen_highpart (SImode, operands[0]),=0A= + gen_highpart (SImode, operands[1])));=0A= + emit_insn (gen_rrcsi2 (gen_lowpart (SImode, operands[0]), lo));=0A= + DONE;=0A= +}=0A= + [(set_attr "length" "12")])=0A= +=0A= ;; Compare / branch instructions.=0A= =0A= (define_expand "cbranchsi4"=0A= @@ -6022,6 +6207,18 @@ archs4x, archs4xd"=0A= (set_attr "iscompact" "maybe,false")=0A= (set_attr "predicable" "no,no")])=0A= =0A= +(define_insn "lshrsi3_cnt1_carry"=0A= + [(set (reg:CC_C CC_REG)=0A= + (unspec:CC_C [(and:SI (match_operand:SI 1 "register_operand" "r")=0A= + (const_int 1))] UNSPEC_ARC_CC_NEZ))=0A= + (set (match_operand:SI 0 "dest_reg_operand" "=3Dr")=0A= + (lshiftrt:SI (match_dup 1) (const_int 1)))]=0A= + ""=0A= + "lsr.f\\t%0,%1"=0A= + [(set_attr "type" "unary")=0A= + (set_attr "length" "4")=0A= + (set_attr "predicable" "no")])=0A= +=0A= (define_insn "ashrsi3_cnt1"=0A= [(set (match_operand:SI 0 "dest_reg_operand" "=3Dq,w")=0A= (ashiftrt:SI (match_operand:SI 1 "register_operand" "q,c")=0A= @@ -6032,6 +6229,28 @@ archs4x, archs4xd"=0A= (set_attr "iscompact" "maybe,false")=0A= (set_attr "predicable" "no,no")])=0A= =0A= +(define_insn "ashrsi3_cnt1_carry"=0A= + [(set (reg:CC_C CC_REG)=0A= + (unspec:CC_C [(and:SI (match_operand:SI 1 "register_operand" "r")=0A= + (const_int 1))] UNSPEC_ARC_CC_NEZ))=0A= + (set (match_operand:SI 0 "dest_reg_operand" "=3Dr")=0A= + (ashiftrt:SI (match_dup 1) (const_int 1)))]=0A= + ""=0A= + "asr.f\\t%0,%1"=0A= + [(set_attr "type" "unary")=0A= + (set_attr "length" "4")=0A= + (set_attr "predicable" "no")])=0A= +=0A= +(define_insn "btst_0_carry"=0A= + [(set (reg:CC_C CC_REG)=0A= + (unspec:CC_C [(and:SI (match_operand:SI 0 "register_operand" "r")=0A= + (const_int 1))] UNSPEC_ARC_CC_NEZ))]=0A= + ""=0A= + "asr.f\\t0,%0"=0A= + [(set_attr "type" "unary")=0A= + (set_attr "length" "4")=0A= + (set_attr "predicable" "no")])=0A= +=0A= (define_peephole2=0A= [(set (match_operand:SI 0 "register_operand" "")=0A= (zero_extract:SI (match_dup 0)=0A= diff --git a/gcc/testsuite/gcc.target/arc/ashrdi3-1.c = b/gcc/testsuite/gcc.target/arc/ashrdi3-1.c=0A= new file mode 100644=0A= index 0000000..d990bfd=0A= --- /dev/null=0A= +++ b/gcc/testsuite/gcc.target/arc/ashrdi3-1.c=0A= @@ -0,0 +1,10 @@=0A= +/* { dg-do compile } */=0A= +/* { dg-options "-O2" } */=0A= +=0A= +long long foo(long long x)=0A= +{=0A= + return x >> 1;=0A= +}=0A= +=0A= +/* { dg-final { scan-assembler "asr.f\\s+r1,r1" } } */=0A= +/* { dg-final { scan-assembler "rrc\\s+r0,r0" } } */=0A= diff --git a/gcc/testsuite/gcc.target/arc/lshrdi3-1.c = b/gcc/testsuite/gcc.target/arc/lshrdi3-1.c=0A= new file mode 100644=0A= index 0000000..6542ffd=0A= --- /dev/null=0A= +++ b/gcc/testsuite/gcc.target/arc/lshrdi3-1.c=0A= @@ -0,0 +1,10 @@=0A= +/* { dg-do compile } */=0A= +/* { dg-options "-O2" } */=0A= +=0A= +unsigned long long foo(unsigned long long x)=0A= +{=0A= + return x >> 1;=0A= +}=0A= +=0A= +/* { dg-final { scan-assembler "lsr.f\\s+r1,r1" } } */=0A= +/* { dg-final { scan-assembler "rrc\\s+r0,r0" } } */=0A= diff --git a/gcc/testsuite/gcc.target/arc/rotldi3-1.c = b/gcc/testsuite/gcc.target/arc/rotldi3-1.c=0A= new file mode 100644=0A= index 0000000..325996e=0A= --- /dev/null=0A= +++ b/gcc/testsuite/gcc.target/arc/rotldi3-1.c=0A= @@ -0,0 +1,11 @@=0A= +/* { dg-do compile } */=0A= +/* { dg-options "-O2" } */=0A= +=0A= +unsigned long long foo(unsigned long long x)=0A= +{=0A= + return (x << 1) | (x >> 63);=0A= +}=0A= +=0A= +/* { dg-final { scan-assembler "add.f\\s+r0,r0,r0" } } */=0A= +/* { dg-final { scan-assembler "adc.f\\s+r1,r1,r1" } } */=0A= +/* { dg-final { scan-assembler "add.cs\\s+r0,r0,1" } } */=0A= diff --git a/gcc/testsuite/gcc.target/arc/rotrdi3-1.c = b/gcc/testsuite/gcc.target/arc/rotrdi3-1.c=0A= new file mode 100644=0A= index 0000000..cd8e0de=0A= --- /dev/null=0A= +++ b/gcc/testsuite/gcc.target/arc/rotrdi3-1.c=0A= @@ -0,0 +1,11 @@=0A= +/* { dg-do compile } */=0A= +/* { dg-options "-O2" } */=0A= +=0A= +unsigned long long foo(unsigned long long x)=0A= +{=0A= + return (x >> 1) | (x << 63);=0A= +}=0A= +=0A= +/* { dg-final { scan-assembler "asr.f\\s+0,r0" } } */=0A= +/* { dg-final { scan-assembler "rrc.f\\s+r1,r1" } } */=0A= +/* { dg-final { scan-assembler "rrc\\s+r0,r0" } } */=0A= ------=_NextPart_000_01FE_01DA10D6.E3C2EF60--