This patch optimizes a few special cases in avr.md's *insv.any_shift.<mode>
instruction.  This template handles tests for a single bit, where the result
has only a (different) single bit set in the result.  Usually (currently)
this always requires a three-instruction sequence of a BST, a CLR and a BLD
(plus any additional CLR instructions to clear the rest of the result
bytes).
The special cases considered here are those that can be done with only two
instructions (plus CLRs); an ANDI preceded by either a MOV, a SHIFT or a
SWAP.

Hence for C=1 in HImode, GCC with -O2 currently generates:

        bst r24,1
        clr r24
        clr r25
        bld r24,0

with this patch, we now generate:

        lsr r24
        andi r24,1
        clr r25

Likewise, HImode C=4 now becomes:

        swap r24
        andi r24,1
        clr r25

and SImode C=8 now becomes:

        mov r22,r23
        andi r22,1
        clr 23
        clr 24
        clr 25


I've not attempted to model the instruction length accurately for these
special cases; the logic would be ugly, but it's safe to use the current
(1 insn longer) length.

This patch has been (partially) tested with a cross-compiler to avr-elf
hosted on x86_64, without a simulator, where the compile-only tests in
the gcc testsuite show no regressions.  If someone could test this more
thoroughly that would be great.


2023-11-02  Roger Sayle  <roger@nextmovesoftware.com>

gcc/ChangeLog
        * config/avr/avr.md (*insv.any_shift.<mode>): Optimize special
        cases of *insv.any_shift that save one instruction by using
        ANDI with either a MOV, a SHIFT or a SWAP.

gcc/testsuite/ChangeLog
        * gcc.target/avr/insvhi-1.c: New HImode test case.
        * gcc.target/avr/insvhi-2.c: Likewise.
        * gcc.target/avr/insvhi-3.c: Likewise.
        * gcc.target/avr/insvhi-4.c: Likewise.
        * gcc.target/avr/insvhi-5.c: Likewise.
        * gcc.target/avr/insvqi-1.c: New QImode test case.
        * gcc.target/avr/insvqi-2.c: Likewise.
        * gcc.target/avr/insvqi-3.c: Likewise.
        * gcc.target/avr/insvqi-4.c: Likewise.
        * gcc.target/avr/insvsi-1.c: New SImode test case.
        * gcc.target/avr/insvsi-2.c: Likewise.
        * gcc.target/avr/insvsi-3.c: Likewise.
        * gcc.target/avr/insvsi-4.c: Likewise.
        * gcc.target/avr/insvsi-5.c: Likewise.
        * gcc.target/avr/insvsi-6.c: Likewise.


Thanks in advance,
Roger
--